codegen_x86.h revision 9d46314a309aff327f9913789b5f61200c162609
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23namespace art { 24 25class X86Mir2Lir FINAL : public Mir2Lir { 26 public: 27 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen helpers. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 33 LIR* CheckSuspendUsingLoad() OVERRIDE; 34 RegStorage LoadHelper(ThreadOffset<4> offset); 35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, 36 int s_reg); 37 LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg); 38 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 39 OpSize size); 40 // TODO: collapse r_dest, r_dest_hi 41 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 42 RegStorage r_dest, RegStorage r_dest_hi, OpSize size, int s_reg); 43 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 44 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 45 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size); 46 LIR* StoreBaseDispWide(RegStorage r_base, int displacement, RegStorage r_src); 47 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 48 OpSize size); 49 // TODO: collapse r_src, r_src_hi 50 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 51 RegStorage r_src, RegStorage r_src_hi, OpSize size, int s_reg); 52 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 53 54 // Required for target - register utilities. 55 bool IsFpReg(int reg); 56 bool IsFpReg(RegStorage reg); 57 bool SameRegType(int reg1, int reg2); 58 RegStorage AllocTypedTemp(bool fp_hint, int reg_class); 59 RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); 60 int S2d(int low_reg, int high_reg); 61 RegStorage TargetReg(SpecialTargetRegister reg); 62 RegStorage GetArgMappingToPhysicalReg(int arg_num); 63 RegLocation GetReturnAlt(); 64 RegLocation GetReturnWideAlt(); 65 RegLocation LocCReturn(); 66 RegLocation LocCReturnDouble(); 67 RegLocation LocCReturnFloat(); 68 RegLocation LocCReturnWide(); 69 uint32_t FpRegMask(); 70 uint64_t GetRegMaskCommon(int reg); 71 void AdjustSpillMask(); 72 void ClobberCallerSave(); 73 void FlushReg(RegStorage reg); 74 void FlushRegWide(RegStorage reg); 75 void FreeCallTemps(); 76 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 77 void LockCallTemps(); 78 void MarkPreservedSingle(int v_reg, int reg); 79 void CompilerInitializeRegAlloc(); 80 81 // Required for target - miscellaneous. 82 void AssembleLIR(); 83 int AssignInsnOffsets(); 84 void AssignOffsets(); 85 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 86 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); 87 void SetupTargetResourceMasks(LIR* lir, uint64_t flags); 88 const char* GetTargetInstFmt(int opcode); 89 const char* GetTargetInstName(int opcode); 90 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 91 uint64_t GetPCUseDefEncoding(); 92 uint64_t GetTargetInstFlags(int opcode); 93 int GetInsnSize(LIR* lir); 94 bool IsUnconditionalBranch(LIR* lir); 95 96 // Required for target - Dalvik-level generators. 97 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 98 RegLocation rl_src2); 99 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 100 RegLocation rl_dest, int scale); 101 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 102 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 103 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 104 RegLocation rl_src1, RegLocation rl_shift); 105 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 106 RegLocation rl_src2); 107 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 108 RegLocation rl_src2); 109 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 110 RegLocation rl_src2); 111 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 112 RegLocation rl_src2); 113 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 114 RegLocation rl_src2); 115 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 116 RegLocation rl_src2); 117 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 118 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 119 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 120 bool GenInlinedSqrt(CallInfo* info); 121 bool GenInlinedPeek(CallInfo* info, OpSize size); 122 bool GenInlinedPoke(CallInfo* info, OpSize size); 123 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 124 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 125 RegLocation rl_src2); 126 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 127 RegLocation rl_src2); 128 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 129 RegLocation rl_src2); 130 LIR* GenRegMemCheck(ConditionCode c_code, RegStorage reg1, RegStorage base, int offset, 131 ThrowKind kind); 132 LIR* GenMemImmedCheck(ConditionCode c_code, RegStorage base, int offset, int check_value, 133 ThrowKind kind); 134 // TODO: collapse reg_lo, reg_hi 135 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 136 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 137 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 138 void GenDivZeroCheckWide(RegStorage reg); 139 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int len_offset); 140 void GenArrayBoundsCheck(int index, RegStorage array_base, int len_offset); 141 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 142 void GenExitSequence(); 143 void GenSpecialExitSequence(); 144 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 145 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 146 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 147 void GenSelect(BasicBlock* bb, MIR* mir); 148 void GenMemBarrier(MemBarrierKind barrier_kind); 149 void GenMoveException(RegLocation rl_dest); 150 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 151 int first_bit, int second_bit); 152 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 153 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 154 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 155 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 156 157 /* 158 * @brief Generate a two address long operation with a constant value 159 * @param rl_dest location of result 160 * @param rl_src constant source operand 161 * @param op Opcode to be generated 162 */ 163 void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 164 /* 165 * @brief Generate a three address long operation with a constant value 166 * @param rl_dest location of result 167 * @param rl_src1 source operand 168 * @param rl_src2 constant source operand 169 * @param op Opcode to be generated 170 */ 171 void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 172 Instruction::Code op); 173 174 /** 175 * @brief Generate a long arithmetic operation. 176 * @param rl_dest The destination. 177 * @param rl_src1 First operand. 178 * @param rl_src2 Second operand. 179 * @param op The DEX opcode for the operation. 180 * @param is_commutative The sources can be swapped if needed. 181 */ 182 void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 183 Instruction::Code op, bool is_commutative); 184 185 /** 186 * @brief Generate a two operand long arithmetic operation. 187 * @param rl_dest The destination. 188 * @param rl_src Second operand. 189 * @param op The DEX opcode for the operation. 190 */ 191 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 192 193 /** 194 * @brief Generate a long operation. 195 * @param rl_dest The destination. Must be in a register 196 * @param rl_src The other operand. May be in a register or in memory. 197 * @param op The DEX opcode for the operation. 198 */ 199 void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 200 201 /** 202 * @brief Implement instanceof a final class with x86 specific code. 203 * @param use_declaring_class 'true' if we can use the class itself. 204 * @param type_idx Type index to use if use_declaring_class is 'false'. 205 * @param rl_dest Result to be set to 0 or 1. 206 * @param rl_src Object to be tested. 207 */ 208 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 209 RegLocation rl_src); 210 /* 211 * 212 * @brief Implement Set up instanceof a class with x86 specific code. 213 * @param needs_access_check 'true' if we must check the access. 214 * @param type_known_final 'true' if the type is known to be a final class. 215 * @param type_known_abstract 'true' if the type is known to be an abstract class. 216 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 217 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 218 * @param type_idx Type index to use if use_declaring_class is 'false'. 219 * @param rl_dest Result to be set to 0 or 1. 220 * @param rl_src Object to be tested. 221 */ 222 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 223 bool type_known_abstract, bool use_declaring_class, 224 bool can_assume_type_is_in_dex_cache, 225 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 226 227 // Single operation generators. 228 LIR* OpUnconditionalBranch(LIR* target); 229 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 230 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 231 LIR* OpCondBranch(ConditionCode cc, LIR* target); 232 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 233 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 234 LIR* OpIT(ConditionCode cond, const char* guide); 235 void OpEndIT(LIR* it); 236 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 237 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 238 LIR* OpReg(OpKind op, RegStorage r_dest_src); 239 LIR* OpRegCopy(RegStorage r_dest, RegStorage r_src); 240 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 241 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 242 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 243 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 244 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 245 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 246 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 247 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 248 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 249 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 250 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 251 LIR* OpTestSuspend(LIR* target); 252 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); 253 LIR* OpVldm(RegStorage r_base, int count); 254 LIR* OpVstm(RegStorage r_base, int count); 255 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 256 void OpRegCopyWide(RegStorage dest, RegStorage src); 257 void OpTlsCmp(ThreadOffset<4> offset, int val); 258 259 void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset<4> thread_offset); 260 void SpillCoreRegs(); 261 void UnSpillCoreRegs(); 262 static const X86EncodingMap EncodingMap[kX86Last]; 263 bool InexpensiveConstantInt(int32_t value); 264 bool InexpensiveConstantFloat(int32_t value); 265 bool InexpensiveConstantLong(int64_t value); 266 bool InexpensiveConstantDouble(int64_t value); 267 268 RegLocation UpdateLocWide(RegLocation loc); 269 RegLocation EvalLocWide(RegLocation loc, int reg_class, bool update); 270 RegLocation EvalLoc(RegLocation loc, int reg_class, bool update); 271 RegStorage AllocTempDouble(); 272 void ResetDefLocWide(RegLocation rl); 273 274 /* 275 * @brief x86 specific codegen for int operations. 276 * @param opcode Operation to perform. 277 * @param rl_dest Destination for the result. 278 * @param rl_lhs Left hand operand. 279 * @param rl_rhs Right hand operand. 280 */ 281 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 282 RegLocation rl_rhs); 283 284 /* 285 * @brief Dump a RegLocation using printf 286 * @param loc Register location to dump 287 */ 288 static void DumpRegLocation(RegLocation loc); 289 290 /* 291 * @brief Load the Method* of a dex method into the register. 292 * @param target_method The MethodReference of the method to be invoked. 293 * @param type How the method will be invoked. 294 * @param register that will contain the code address. 295 * @note register will be passed to TargetReg to get physical register. 296 */ 297 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 298 SpecialTargetRegister symbolic_reg); 299 300 /* 301 * @brief Load the Class* of a Dex Class type into the register. 302 * @param type How the method will be invoked. 303 * @param register that will contain the code address. 304 * @note register will be passed to TargetReg to get physical register. 305 */ 306 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 307 308 /* 309 * @brief Generate a relative call to the method that will be patched at link time. 310 * @param target_method The MethodReference of the method to be invoked. 311 * @param type How the method will be invoked. 312 * @returns Call instruction 313 */ 314 LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 315 316 /* 317 * @brief Handle x86 specific literals 318 */ 319 void InstallLiteralPools(); 320 321 /* 322 * @brief Generate the debug_frame CFI information. 323 * @returns pointer to vector containing CFE information 324 */ 325 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 326 327 /* 328 * @brief Generate the debug_frame FDE information. 329 * @returns pointer to vector containing CFE information 330 */ 331 std::vector<uint8_t>* ReturnCallFrameInformation(); 332 333 private: 334 void EmitPrefix(const X86EncodingMap* entry); 335 void EmitOpcode(const X86EncodingMap* entry); 336 void EmitPrefixAndOpcode(const X86EncodingMap* entry); 337 void EmitDisp(uint8_t base, int disp); 338 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp); 339 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp); 340 void EmitImm(const X86EncodingMap* entry, int imm); 341 void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg); 342 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); 343 void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp); 344 void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp); 345 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg); 346 void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm); 347 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp); 348 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 349 int scale, int disp); 350 void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 351 uint8_t reg); 352 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp); 353 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2); 354 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 355 void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 356 void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, 357 int32_t imm); 358 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 359 void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm); 360 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 361 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 362 void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl); 363 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl); 364 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition); 365 366 /** 367 * @brief Used for encoding conditional register to register operation. 368 * @param entry The entry in the encoding map for the opcode. 369 * @param reg1 The first physical register. 370 * @param reg2 The second physical register. 371 * @param condition The condition code for operation. 372 */ 373 void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition); 374 375 void EmitJmp(const X86EncodingMap* entry, int rel); 376 void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc); 377 void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp); 378 void EmitCallImmediate(const X86EncodingMap* entry, int disp); 379 void EmitCallThread(const X86EncodingMap* entry, int disp); 380 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, 381 int scale, int table_or_disp); 382 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset); 383 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 384 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 385 int64_t val, ConditionCode ccode); 386 void OpVectorRegCopyWide(uint8_t fp_reg, uint8_t low_reg, uint8_t high_reg); 387 void GenConstWide(RegLocation rl_dest, int64_t value); 388 389 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 390 391 /* 392 * @brief generate inline code for fast case of Strng.indexOf. 393 * @param info Call parameters 394 * @param zero_based 'true' if the index into the string is 0. 395 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 396 * generated. 397 */ 398 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 399 400 /* 401 * @brief Return the correct x86 opcode for the Dex operation 402 * @param op Dex opcode for the operation 403 * @param loc Register location of the operand 404 * @param is_high_op 'true' if this is an operation on the high word 405 * @param value Immediate value for the operation. Used for byte variants 406 * @returns the correct x86 opcode to perform the operation 407 */ 408 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 409 410 /* 411 * @brief Return the correct x86 opcode for the Dex operation 412 * @param op Dex opcode for the operation 413 * @param dest location of the destination. May be register or memory. 414 * @param rhs Location for the rhs of the operation. May be in register or memory. 415 * @param is_high_op 'true' if this is an operation on the high word 416 * @returns the correct x86 opcode to perform the operation 417 * @note at most one location may refer to memory 418 */ 419 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 420 bool is_high_op); 421 422 /* 423 * @brief Is this operation a no-op for this opcode and value 424 * @param op Dex opcode for the operation 425 * @param value Immediate value for the operation. 426 * @returns 'true' if the operation will have no effect 427 */ 428 bool IsNoOp(Instruction::Code op, int32_t value); 429 430 /** 431 * @brief Calculate magic number and shift for a given divisor 432 * @param divisor divisor number for calculation 433 * @param magic hold calculated magic number 434 * @param shift hold calculated shift 435 */ 436 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 437 438 /* 439 * @brief Generate an integer div or rem operation. 440 * @param rl_dest Destination Location. 441 * @param rl_src1 Numerator Location. 442 * @param rl_src2 Divisor Location. 443 * @param is_div 'true' if this is a division, 'false' for a remainder. 444 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 445 */ 446 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 447 bool is_div, bool check_zero); 448 449 /* 450 * @brief Generate an integer div or rem operation by a literal. 451 * @param rl_dest Destination Location. 452 * @param rl_src Numerator Location. 453 * @param lit Divisor. 454 * @param is_div 'true' if this is a division, 'false' for a remainder. 455 */ 456 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 457 458 /* 459 * Generate code to implement long shift operations. 460 * @param opcode The DEX opcode to specify the shift type. 461 * @param rl_dest The destination. 462 * @param rl_src The value to be shifted. 463 * @param shift_amount How much to shift. 464 * @returns the RegLocation of the result. 465 */ 466 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 467 RegLocation rl_src, int shift_amount); 468 /* 469 * Generate an imul of a register by a constant or a better sequence. 470 * @param dest Destination Register. 471 * @param src Source Register. 472 * @param val Constant multiplier. 473 */ 474 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 475 476 /* 477 * Generate an imul of a memory location by a constant or a better sequence. 478 * @param dest Destination Register. 479 * @param sreg Symbolic register. 480 * @param displacement Displacement on stack of Symbolic Register. 481 * @param val Constant multiplier. 482 */ 483 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 484 485 /* 486 * @brief Compare memory to immediate, and branch if condition true. 487 * @param cond The condition code that when true will branch to the target. 488 * @param temp_reg A temporary register that can be used if compare memory is not 489 * supported by the architecture. 490 * @param base_reg The register holding the base address. 491 * @param offset The offset from the base. 492 * @param check_value The immediate to compare to. 493 */ 494 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 495 int offset, int check_value, LIR* target); 496 497 /* 498 * Can this operation be using core registers without temporaries? 499 * @param rl_lhs Left hand operand. 500 * @param rl_rhs Right hand operand. 501 * @returns 'true' if the operation can proceed without needing temporary regs. 502 */ 503 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 504 505 /** 506 * @brief Generates inline code for conversion of long to FP by using x87/ 507 * @param rl_dest The destination of the FP. 508 * @param rl_src The source of the long. 509 * @param is_double 'true' if dealing with double, 'false' for float. 510 */ 511 void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 512 513 /* 514 * @brief Perform MIR analysis before compiling method. 515 * @note Invokes Mir2LiR::Materialize after analysis. 516 */ 517 void Materialize(); 518 519 /* 520 * @brief Analyze MIR before generating code, to prepare for the code generation. 521 */ 522 void AnalyzeMIR(); 523 524 /* 525 * @brief Analyze one basic block. 526 * @param bb Basic block to analyze. 527 */ 528 void AnalyzeBB(BasicBlock * bb); 529 530 /* 531 * @brief Analyze one extended MIR instruction 532 * @param opcode MIR instruction opcode. 533 * @param bb Basic block containing instruction. 534 * @param mir Extended instruction to analyze. 535 */ 536 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 537 538 /* 539 * @brief Analyze one MIR instruction 540 * @param opcode MIR instruction opcode. 541 * @param bb Basic block containing instruction. 542 * @param mir Instruction to analyze. 543 */ 544 void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 545 546 /* 547 * @brief Analyze one MIR float/double instruction 548 * @param opcode MIR instruction opcode. 549 * @param bb Basic block containing instruction. 550 * @param mir Instruction to analyze. 551 */ 552 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 553 554 /* 555 * @brief Analyze one use of a double operand. 556 * @param rl_use Double RegLocation for the operand. 557 */ 558 void AnalyzeDoubleUse(RegLocation rl_use); 559 560 // Information derived from analysis of MIR 561 562 // The compiler temporary for the code address of the method. 563 CompilerTemp *base_of_code_; 564 565 // Have we decided to compute a ptr to code and store in temporary VR? 566 bool store_method_addr_; 567 568 // Have we used the stored method address? 569 bool store_method_addr_used_; 570 571 // Instructions to remove if we didn't use the stored method address. 572 LIR* setup_method_address_[2]; 573 574 // Instructions needing patching with Method* values. 575 GrowableArray<LIR*> method_address_insns_; 576 577 // Instructions needing patching with Class Type* values. 578 GrowableArray<LIR*> class_type_address_insns_; 579 580 // Instructions needing patching with PC relative code addresses. 581 GrowableArray<LIR*> call_method_insns_; 582 583 // Prologue decrement of stack pointer. 584 LIR* stack_decrement_; 585 586 // Epilogue increment of stack pointer. 587 LIR* stack_increment_; 588}; 589 590} // namespace art 591 592#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 593