codegen_x86.h revision a77ee5103532abb197f492c14a9e6fb437054e2a
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23#include <map> 24 25namespace art { 26 27class X86Mir2Lir : public Mir2Lir { 28 protected: 29 class InToRegStorageMapper { 30 public: 31 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide) = 0; 32 virtual ~InToRegStorageMapper() {} 33 }; 34 35 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 36 public: 37 explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} 38 virtual ~InToRegStorageX86_64Mapper() {} 39 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide); 40 protected: 41 Mir2Lir* ml_; 42 private: 43 int cur_core_reg_; 44 int cur_fp_reg_; 45 }; 46 47 class InToRegStorageMapping { 48 public: 49 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 50 initialized_(false) {} 51 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 52 int GetMaxMappedIn() { return max_mapped_in_; } 53 bool IsThereStackMapped() { return is_there_stack_mapped_; } 54 RegStorage Get(int in_position); 55 bool IsInitialized() { return initialized_; } 56 private: 57 std::map<int, RegStorage> mapping_; 58 int max_mapped_in_; 59 bool is_there_stack_mapped_; 60 bool initialized_; 61 }; 62 63 public: 64 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 65 66 // Required for target - codegen helpers. 67 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 68 RegLocation rl_dest, int lit); 69 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 70 LIR* CheckSuspendUsingLoad() OVERRIDE; 71 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 72 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 73 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 74 OpSize size, VolatileKind is_volatile) OVERRIDE; 75 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 76 OpSize size) OVERRIDE; 77 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 78 RegStorage r_dest, OpSize size) OVERRIDE; 79 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 80 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 81 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 82 OpSize size, VolatileKind is_volatile) OVERRIDE; 83 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 84 OpSize size) OVERRIDE; 85 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 86 RegStorage r_src, OpSize size) OVERRIDE; 87 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 88 89 // Required for target - register utilities. 90 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 91 RegStorage TargetReg32(SpecialTargetRegister reg); 92 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, bool is_wide) OVERRIDE { 93 RegStorage reg = TargetReg32(symbolic_reg); 94 if (is_wide) { 95 return (reg.Is64Bit()) ? reg : As64BitReg(reg); 96 } else { 97 return (reg.Is32Bit()) ? reg : As32BitReg(reg); 98 } 99 } 100 RegStorage TargetRefReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 101 return TargetReg(symbolic_reg, cu_->target64); 102 } 103 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 104 return TargetReg(symbolic_reg, cu_->target64); 105 } 106 RegStorage GetArgMappingToPhysicalReg(int arg_num); 107 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 108 RegLocation GetReturnAlt(); 109 RegLocation GetReturnWideAlt(); 110 RegLocation LocCReturn(); 111 RegLocation LocCReturnRef(); 112 RegLocation LocCReturnDouble(); 113 RegLocation LocCReturnFloat(); 114 RegLocation LocCReturnWide(); 115 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 116 void AdjustSpillMask(); 117 void ClobberCallerSave(); 118 void FreeCallTemps(); 119 void LockCallTemps(); 120 void CompilerInitializeRegAlloc(); 121 122 // Required for target - miscellaneous. 123 void AssembleLIR(); 124 int AssignInsnOffsets(); 125 void AssignOffsets(); 126 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 127 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 128 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 129 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 130 const char* GetTargetInstFmt(int opcode); 131 const char* GetTargetInstName(int opcode); 132 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 133 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 134 uint64_t GetTargetInstFlags(int opcode); 135 size_t GetInsnSize(LIR* lir) OVERRIDE; 136 bool IsUnconditionalBranch(LIR* lir); 137 138 // Check support for volatile load/store of a given size. 139 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 140 // Get the register class for load/store of a field. 141 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 142 143 // Required for target - Dalvik-level generators. 144 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 145 RegLocation rl_src2); 146 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 147 RegLocation rl_dest, int scale); 148 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 149 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 150 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 151 RegLocation rl_src1, RegLocation rl_shift); 152 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 153 RegLocation rl_src2); 154 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 155 RegLocation rl_src2); 156 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 157 RegLocation rl_src2); 158 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 159 RegLocation rl_src2); 160 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 161 RegLocation rl_src2); 162 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 163 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 164 RegLocation rl_src2); 165 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 166 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 167 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 168 bool GenInlinedSqrt(CallInfo* info); 169 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 170 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 171 bool GenInlinedPeek(CallInfo* info, OpSize size); 172 bool GenInlinedPoke(CallInfo* info, OpSize size); 173 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 174 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 175 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 176 RegLocation rl_src2); 177 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 178 RegLocation rl_src2); 179 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 180 RegLocation rl_src2); 181 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 182 RegLocation rl_src2, bool is_div); 183 // TODO: collapse reg_lo, reg_hi 184 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 185 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 186 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 187 void GenDivZeroCheckWide(RegStorage reg); 188 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 189 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 190 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 191 void GenExitSequence(); 192 void GenSpecialExitSequence(); 193 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 194 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 195 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 196 void GenSelect(BasicBlock* bb, MIR* mir); 197 bool GenMemBarrier(MemBarrierKind barrier_kind); 198 void GenMoveException(RegLocation rl_dest); 199 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 200 int first_bit, int second_bit); 201 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 202 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 203 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 204 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 205 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src); 206 207 /* 208 * @brief Generate a two address long operation with a constant value 209 * @param rl_dest location of result 210 * @param rl_src constant source operand 211 * @param op Opcode to be generated 212 * @return success or not 213 */ 214 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 215 /* 216 * @brief Generate a three address long operation with a constant value 217 * @param rl_dest location of result 218 * @param rl_src1 source operand 219 * @param rl_src2 constant source operand 220 * @param op Opcode to be generated 221 * @return success or not 222 */ 223 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 224 Instruction::Code op); 225 226 /** 227 * @brief Generate a long arithmetic operation. 228 * @param rl_dest The destination. 229 * @param rl_src1 First operand. 230 * @param rl_src2 Second operand. 231 * @param op The DEX opcode for the operation. 232 * @param is_commutative The sources can be swapped if needed. 233 */ 234 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 235 Instruction::Code op, bool is_commutative); 236 237 /** 238 * @brief Generate a two operand long arithmetic operation. 239 * @param rl_dest The destination. 240 * @param rl_src Second operand. 241 * @param op The DEX opcode for the operation. 242 */ 243 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 244 245 /** 246 * @brief Generate a long operation. 247 * @param rl_dest The destination. Must be in a register 248 * @param rl_src The other operand. May be in a register or in memory. 249 * @param op The DEX opcode for the operation. 250 */ 251 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 252 253 /** 254 * @brief Implement instanceof a final class with x86 specific code. 255 * @param use_declaring_class 'true' if we can use the class itself. 256 * @param type_idx Type index to use if use_declaring_class is 'false'. 257 * @param rl_dest Result to be set to 0 or 1. 258 * @param rl_src Object to be tested. 259 */ 260 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 261 RegLocation rl_src); 262 /* 263 * 264 * @brief Implement Set up instanceof a class with x86 specific code. 265 * @param needs_access_check 'true' if we must check the access. 266 * @param type_known_final 'true' if the type is known to be a final class. 267 * @param type_known_abstract 'true' if the type is known to be an abstract class. 268 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 269 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 270 * @param type_idx Type index to use if use_declaring_class is 'false'. 271 * @param rl_dest Result to be set to 0 or 1. 272 * @param rl_src Object to be tested. 273 */ 274 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 275 bool type_known_abstract, bool use_declaring_class, 276 bool can_assume_type_is_in_dex_cache, 277 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 278 279 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 280 RegLocation rl_src1, RegLocation rl_shift); 281 282 // Single operation generators. 283 LIR* OpUnconditionalBranch(LIR* target); 284 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 285 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 286 LIR* OpCondBranch(ConditionCode cc, LIR* target); 287 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 288 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 289 LIR* OpIT(ConditionCode cond, const char* guide); 290 void OpEndIT(LIR* it); 291 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 292 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 293 LIR* OpReg(OpKind op, RegStorage r_dest_src); 294 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 295 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 296 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 297 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 298 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 299 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 300 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 301 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 302 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 303 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 304 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 305 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 306 LIR* OpTestSuspend(LIR* target); 307 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 308 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 309 LIR* OpVldm(RegStorage r_base, int count); 310 LIR* OpVstm(RegStorage r_base, int count); 311 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 312 void OpRegCopyWide(RegStorage dest, RegStorage src); 313 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 314 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 315 316 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 317 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 318 void SpillCoreRegs(); 319 void UnSpillCoreRegs(); 320 static const X86EncodingMap EncodingMap[kX86Last]; 321 bool InexpensiveConstantInt(int32_t value); 322 bool InexpensiveConstantFloat(int32_t value); 323 bool InexpensiveConstantLong(int64_t value); 324 bool InexpensiveConstantDouble(int64_t value); 325 326 /* 327 * @brief Should try to optimize for two address instructions? 328 * @return true if we try to avoid generating three operand instructions. 329 */ 330 virtual bool GenerateTwoOperandInstructions() const { return true; } 331 332 /* 333 * @brief x86 specific codegen for int operations. 334 * @param opcode Operation to perform. 335 * @param rl_dest Destination for the result. 336 * @param rl_lhs Left hand operand. 337 * @param rl_rhs Right hand operand. 338 */ 339 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 340 RegLocation rl_rhs); 341 342 /* 343 * @brief Dump a RegLocation using printf 344 * @param loc Register location to dump 345 */ 346 static void DumpRegLocation(RegLocation loc); 347 348 /* 349 * @brief Load the Method* of a dex method into the register. 350 * @param target_method The MethodReference of the method to be invoked. 351 * @param type How the method will be invoked. 352 * @param register that will contain the code address. 353 * @note register will be passed to TargetReg to get physical register. 354 */ 355 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 356 SpecialTargetRegister symbolic_reg); 357 358 /* 359 * @brief Load the Class* of a Dex Class type into the register. 360 * @param type How the method will be invoked. 361 * @param register that will contain the code address. 362 * @note register will be passed to TargetReg to get physical register. 363 */ 364 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 365 366 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method); 367 368 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 369 NextCallInsn next_call_insn, 370 const MethodReference& target_method, 371 uint32_t vtable_idx, 372 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 373 bool skip_this); 374 375 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 376 NextCallInsn next_call_insn, 377 const MethodReference& target_method, 378 uint32_t vtable_idx, 379 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 380 bool skip_this); 381 382 /* 383 * @brief Generate a relative call to the method that will be patched at link time. 384 * @param target_method The MethodReference of the method to be invoked. 385 * @param type How the method will be invoked. 386 * @returns Call instruction 387 */ 388 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 389 390 /* 391 * @brief Handle x86 specific literals 392 */ 393 void InstallLiteralPools(); 394 395 /* 396 * @brief Generate the debug_frame CFI information. 397 * @returns pointer to vector containing CFE information 398 */ 399 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 400 401 /* 402 * @brief Generate the debug_frame FDE information. 403 * @returns pointer to vector containing CFE information 404 */ 405 std::vector<uint8_t>* ReturnCallFrameInformation(); 406 407 protected: 408 // Casting of RegStorage 409 RegStorage As32BitReg(RegStorage reg) { 410 DCHECK(!reg.IsPair()); 411 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 412 if (kFailOnSizeError) { 413 LOG(FATAL) << "Expected 64b register " << reg.GetReg(); 414 } else { 415 LOG(WARNING) << "Expected 64b register " << reg.GetReg(); 416 return reg; 417 } 418 } 419 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 420 reg.GetRawBits() & RegStorage::kRegTypeMask); 421 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 422 ->GetReg().GetReg(), 423 ret_val.GetReg()); 424 return ret_val; 425 } 426 427 RegStorage As64BitReg(RegStorage reg) { 428 DCHECK(!reg.IsPair()); 429 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 430 if (kFailOnSizeError) { 431 LOG(FATAL) << "Expected 32b register " << reg.GetReg(); 432 } else { 433 LOG(WARNING) << "Expected 32b register " << reg.GetReg(); 434 return reg; 435 } 436 } 437 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 438 reg.GetRawBits() & RegStorage::kRegTypeMask); 439 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 440 ->GetReg().GetReg(), 441 ret_val.GetReg()); 442 return ret_val; 443 } 444 445 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 446 int32_t raw_base, int32_t displacement); 447 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 448 void EmitPrefix(const X86EncodingMap* entry, 449 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 450 void EmitOpcode(const X86EncodingMap* entry); 451 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 452 int32_t reg_r, int32_t reg_x, int32_t reg_b); 453 void EmitDisp(uint8_t base, int32_t disp); 454 void EmitModrmThread(uint8_t reg_or_opcode); 455 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 456 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 457 int32_t disp); 458 void EmitImm(const X86EncodingMap* entry, int64_t imm); 459 void EmitNullary(const X86EncodingMap* entry); 460 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 461 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 462 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 463 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 464 int32_t disp); 465 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 466 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 467 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 468 int32_t raw_index, int scale, int32_t disp); 469 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 470 int32_t disp, int32_t raw_reg); 471 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 472 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 473 int32_t raw_disp, int32_t imm); 474 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 475 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 476 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 477 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 478 int32_t imm); 479 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 480 int32_t imm); 481 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 482 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 483 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 484 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 485 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 486 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 487 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 488 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 489 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 490 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 491 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 492 int32_t cc); 493 494 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 495 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 496 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 497 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 498 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 499 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 500 int32_t raw_index, int scale, int32_t table_or_disp); 501 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 502 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 503 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 504 int64_t val, ConditionCode ccode); 505 void GenConstWide(RegLocation rl_dest, int64_t value); 506 507 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 508 509 /* 510 * @brief Ensure that a temporary register is byte addressable. 511 * @returns a temporary guarenteed to be byte addressable. 512 */ 513 virtual RegStorage AllocateByteRegister(); 514 515 /* 516 * @brief Check if a register is byte addressable. 517 * @returns true if a register is byte addressable. 518 */ 519 bool IsByteRegister(RegStorage reg); 520 521 /* 522 * @brief generate inline code for fast case of Strng.indexOf. 523 * @param info Call parameters 524 * @param zero_based 'true' if the index into the string is 0. 525 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 526 * generated. 527 */ 528 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 529 530 /* 531 * @brief Load 128 bit constant into vector register. 532 * @param bb The basic block in which the MIR is from. 533 * @param mir The MIR whose opcode is kMirConstVector 534 * @note vA is the TypeSize for the register. 535 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 536 */ 537 void GenConst128(BasicBlock* bb, MIR* mir); 538 539 /* 540 * @brief MIR to move a vectorized register to another. 541 * @param bb The basic block in which the MIR is from. 542 * @param mir The MIR whose opcode is kMirConstVector. 543 * @note vA: TypeSize 544 * @note vB: destination 545 * @note vC: source 546 */ 547 void GenMoveVector(BasicBlock *bb, MIR *mir); 548 549 /* 550 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know the type of the vector. 551 * @param bb The basic block in which the MIR is from. 552 * @param mir The MIR whose opcode is kMirConstVector. 553 * @note vA: TypeSize 554 * @note vB: destination and source 555 * @note vC: source 556 */ 557 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 558 559 /* 560 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. 561 * @param bb The basic block in which the MIR is from. 562 * @param mir The MIR whose opcode is kMirConstVector. 563 * @note vA: TypeSize 564 * @note vB: destination and source 565 * @note vC: source 566 */ 567 void GenAddVector(BasicBlock *bb, MIR *mir); 568 569 /* 570 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. 571 * @param bb The basic block in which the MIR is from. 572 * @param mir The MIR whose opcode is kMirConstVector. 573 * @note vA: TypeSize 574 * @note vB: destination and source 575 * @note vC: source 576 */ 577 void GenSubtractVector(BasicBlock *bb, MIR *mir); 578 579 /* 580 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. 581 * @param bb The basic block in which the MIR is from. 582 * @param mir The MIR whose opcode is kMirConstVector. 583 * @note vA: TypeSize 584 * @note vB: destination and source 585 * @note vC: immediate 586 */ 587 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 588 589 /* 590 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. 591 * @param bb The basic block in which the MIR is from. 592 * @param mir The MIR whose opcode is kMirConstVector. 593 * @note vA: TypeSize 594 * @note vB: destination and source 595 * @note vC: immediate 596 */ 597 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 598 599 /* 600 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. 601 * @param bb The basic block in which the MIR is from.. 602 * @param mir The MIR whose opcode is kMirConstVector. 603 * @note vA: TypeSize 604 * @note vB: destination and source 605 * @note vC: immediate 606 */ 607 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 608 609 /* 610 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. 611 * @note vA: TypeSize 612 * @note vB: destination and source 613 * @note vC: source 614 */ 615 void GenAndVector(BasicBlock *bb, MIR *mir); 616 617 /* 618 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. 619 * @param bb The basic block in which the MIR is from. 620 * @param mir The MIR whose opcode is kMirConstVector. 621 * @note vA: TypeSize 622 * @note vB: destination and source 623 * @note vC: source 624 */ 625 void GenOrVector(BasicBlock *bb, MIR *mir); 626 627 /* 628 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. 629 * @param bb The basic block in which the MIR is from. 630 * @param mir The MIR whose opcode is kMirConstVector. 631 * @note vA: TypeSize 632 * @note vB: destination and source 633 * @note vC: source 634 */ 635 void GenXorVector(BasicBlock *bb, MIR *mir); 636 637 /* 638 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 639 * @param bb The basic block in which the MIR is from. 640 * @param mir The MIR whose opcode is kMirConstVector. 641 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 642 * @note vA: TypeSize 643 * @note vB: destination and source VR (not vector register) 644 * @note vC: source (vector register) 645 */ 646 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 647 648 /* 649 * @brief Extract a packed element into a single VR. 650 * @param bb The basic block in which the MIR is from. 651 * @param mir The MIR whose opcode is kMirConstVector. 652 * @note vA: TypeSize 653 * @note vB: destination VR (not vector register) 654 * @note vC: source (vector register) 655 * @note arg[0]: The index to use for extraction from vector register (which packed element). 656 */ 657 void GenReduceVector(BasicBlock *bb, MIR *mir); 658 659 /* 660 * @brief Create a vector value, with all TypeSize values equal to vC 661 * @param bb The basic block in which the MIR is from. 662 * @param mir The MIR whose opcode is kMirConstVector. 663 * @note vA: TypeSize. 664 * @note vB: destination vector register. 665 * @note vC: source VR (not vector register). 666 */ 667 void GenSetVector(BasicBlock *bb, MIR *mir); 668 669 /* 670 * @brief Generate code for a vector opcode. 671 * @param bb The basic block in which the MIR is from. 672 * @param mir The MIR whose opcode is a non-standard opcode. 673 */ 674 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 675 676 /* 677 * @brief Return the correct x86 opcode for the Dex operation 678 * @param op Dex opcode for the operation 679 * @param loc Register location of the operand 680 * @param is_high_op 'true' if this is an operation on the high word 681 * @param value Immediate value for the operation. Used for byte variants 682 * @returns the correct x86 opcode to perform the operation 683 */ 684 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 685 686 /* 687 * @brief Return the correct x86 opcode for the Dex operation 688 * @param op Dex opcode for the operation 689 * @param dest location of the destination. May be register or memory. 690 * @param rhs Location for the rhs of the operation. May be in register or memory. 691 * @param is_high_op 'true' if this is an operation on the high word 692 * @returns the correct x86 opcode to perform the operation 693 * @note at most one location may refer to memory 694 */ 695 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 696 bool is_high_op); 697 698 /* 699 * @brief Is this operation a no-op for this opcode and value 700 * @param op Dex opcode for the operation 701 * @param value Immediate value for the operation. 702 * @returns 'true' if the operation will have no effect 703 */ 704 bool IsNoOp(Instruction::Code op, int32_t value); 705 706 /** 707 * @brief Calculate magic number and shift for a given divisor 708 * @param divisor divisor number for calculation 709 * @param magic hold calculated magic number 710 * @param shift hold calculated shift 711 */ 712 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 713 714 /* 715 * @brief Generate an integer div or rem operation. 716 * @param rl_dest Destination Location. 717 * @param rl_src1 Numerator Location. 718 * @param rl_src2 Divisor Location. 719 * @param is_div 'true' if this is a division, 'false' for a remainder. 720 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 721 */ 722 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 723 bool is_div, bool check_zero); 724 725 /* 726 * @brief Generate an integer div or rem operation by a literal. 727 * @param rl_dest Destination Location. 728 * @param rl_src Numerator Location. 729 * @param lit Divisor. 730 * @param is_div 'true' if this is a division, 'false' for a remainder. 731 */ 732 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 733 734 /* 735 * Generate code to implement long shift operations. 736 * @param opcode The DEX opcode to specify the shift type. 737 * @param rl_dest The destination. 738 * @param rl_src The value to be shifted. 739 * @param shift_amount How much to shift. 740 * @returns the RegLocation of the result. 741 */ 742 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 743 RegLocation rl_src, int shift_amount); 744 /* 745 * Generate an imul of a register by a constant or a better sequence. 746 * @param dest Destination Register. 747 * @param src Source Register. 748 * @param val Constant multiplier. 749 */ 750 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 751 752 /* 753 * Generate an imul of a memory location by a constant or a better sequence. 754 * @param dest Destination Register. 755 * @param sreg Symbolic register. 756 * @param displacement Displacement on stack of Symbolic Register. 757 * @param val Constant multiplier. 758 */ 759 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 760 761 /* 762 * @brief Compare memory to immediate, and branch if condition true. 763 * @param cond The condition code that when true will branch to the target. 764 * @param temp_reg A temporary register that can be used if compare memory is not 765 * supported by the architecture. 766 * @param base_reg The register holding the base address. 767 * @param offset The offset from the base. 768 * @param check_value The immediate to compare to. 769 */ 770 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 771 int offset, int check_value, LIR* target); 772 773 /* 774 * Can this operation be using core registers without temporaries? 775 * @param rl_lhs Left hand operand. 776 * @param rl_rhs Right hand operand. 777 * @returns 'true' if the operation can proceed without needing temporary regs. 778 */ 779 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 780 781 /** 782 * @brief Generates inline code for conversion of long to FP by using x87/ 783 * @param rl_dest The destination of the FP. 784 * @param rl_src The source of the long. 785 * @param is_double 'true' if dealing with double, 'false' for float. 786 */ 787 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 788 789 /* 790 * @brief Perform MIR analysis before compiling method. 791 * @note Invokes Mir2LiR::Materialize after analysis. 792 */ 793 void Materialize(); 794 795 /* 796 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 797 * without regard to data type. In practice, this can result in UpdateLoc returning a 798 * location record for a Dalvik float value in a core register, and vis-versa. For targets 799 * which can inexpensively move data between core and float registers, this can often be a win. 800 * However, for x86 this is generally not a win. These variants of UpdateLoc() 801 * take a register class argument - and will return an in-register location record only if 802 * the value is live in a temp register of the correct class. Additionally, if the value is in 803 * a temp register of the wrong register class, it will be clobbered. 804 */ 805 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 806 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 807 808 /* 809 * @brief Analyze MIR before generating code, to prepare for the code generation. 810 */ 811 void AnalyzeMIR(); 812 813 /* 814 * @brief Analyze one basic block. 815 * @param bb Basic block to analyze. 816 */ 817 void AnalyzeBB(BasicBlock * bb); 818 819 /* 820 * @brief Analyze one extended MIR instruction 821 * @param opcode MIR instruction opcode. 822 * @param bb Basic block containing instruction. 823 * @param mir Extended instruction to analyze. 824 */ 825 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 826 827 /* 828 * @brief Analyze one MIR instruction 829 * @param opcode MIR instruction opcode. 830 * @param bb Basic block containing instruction. 831 * @param mir Instruction to analyze. 832 */ 833 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 834 835 /* 836 * @brief Analyze one MIR float/double instruction 837 * @param opcode MIR instruction opcode. 838 * @param bb Basic block containing instruction. 839 * @param mir Instruction to analyze. 840 */ 841 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 842 843 /* 844 * @brief Analyze one use of a double operand. 845 * @param rl_use Double RegLocation for the operand. 846 */ 847 void AnalyzeDoubleUse(RegLocation rl_use); 848 849 /* 850 * @brief Analyze one invoke-static MIR instruction 851 * @param opcode MIR instruction opcode. 852 * @param bb Basic block containing instruction. 853 * @param mir Instruction to analyze. 854 */ 855 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 856 857 // Information derived from analysis of MIR 858 859 // The compiler temporary for the code address of the method. 860 CompilerTemp *base_of_code_; 861 862 // Have we decided to compute a ptr to code and store in temporary VR? 863 bool store_method_addr_; 864 865 // Have we used the stored method address? 866 bool store_method_addr_used_; 867 868 // Instructions to remove if we didn't use the stored method address. 869 LIR* setup_method_address_[2]; 870 871 // Instructions needing patching with Method* values. 872 GrowableArray<LIR*> method_address_insns_; 873 874 // Instructions needing patching with Class Type* values. 875 GrowableArray<LIR*> class_type_address_insns_; 876 877 // Instructions needing patching with PC relative code addresses. 878 GrowableArray<LIR*> call_method_insns_; 879 880 // Prologue decrement of stack pointer. 881 LIR* stack_decrement_; 882 883 // Epilogue increment of stack pointer. 884 LIR* stack_increment_; 885 886 // The list of const vector literals. 887 LIR *const_vectors_; 888 889 /* 890 * @brief Search for a matching vector literal 891 * @param mir A kMirOpConst128b MIR instruction to match. 892 * @returns pointer to matching LIR constant, or nullptr if not found. 893 */ 894 LIR *ScanVectorLiteral(MIR *mir); 895 896 /* 897 * @brief Add a constant vector literal 898 * @param mir A kMirOpConst128b MIR instruction to match. 899 */ 900 LIR *AddVectorLiteral(MIR *mir); 901 902 InToRegStorageMapping in_to_reg_storage_mapping_; 903}; 904 905} // namespace art 906 907#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 908