codegen_x86.h revision b14329f90f725af0f67c45dfcb94933a426d63ce
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "x86_lir.h" 22 23namespace art { 24 25class X86Mir2Lir FINAL : public Mir2Lir { 26 public: 27 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 28 29 // Required for target - codegen helpers. 30 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 31 RegLocation rl_dest, int lit); 32 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 33 LIR* CheckSuspendUsingLoad() OVERRIDE; 34 RegStorage LoadHelper(ThreadOffset<4> offset) OVERRIDE; 35 RegStorage LoadHelper(ThreadOffset<8> offset) OVERRIDE; 36 LIR* LoadBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_dest, 37 OpSize size) OVERRIDE; 38 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 39 OpSize size) OVERRIDE; 40 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 41 OpSize size) OVERRIDE; 42 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 43 RegStorage r_dest, OpSize size) OVERRIDE; 44 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 45 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 46 LIR* StoreBaseDispVolatile(RegStorage r_base, int displacement, RegStorage r_src, 47 OpSize size) OVERRIDE; 48 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 49 OpSize size) OVERRIDE; 50 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 51 OpSize size) OVERRIDE; 52 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 53 RegStorage r_src, OpSize size) OVERRIDE; 54 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg); 55 56 // Required for target - register utilities. 57 RegStorage AllocTypedTemp(bool fp_hint, int reg_class); 58 RegStorage AllocTypedTempWide(bool fp_hint, int reg_class); 59 RegStorage TargetReg(SpecialTargetRegister reg); 60 RegStorage GetArgMappingToPhysicalReg(int arg_num); 61 RegLocation GetReturnAlt(); 62 RegLocation GetReturnWideAlt(); 63 RegLocation LocCReturn(); 64 RegLocation LocCReturnDouble(); 65 RegLocation LocCReturnFloat(); 66 RegLocation LocCReturnWide(); 67 uint64_t GetRegMaskCommon(RegStorage reg); 68 void AdjustSpillMask(); 69 void ClobberCallerSave(); 70 void FreeCallTemps(); 71 void FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free); 72 void LockCallTemps(); 73 void MarkPreservedSingle(int v_reg, RegStorage reg); 74 void MarkPreservedDouble(int v_reg, RegStorage reg); 75 void CompilerInitializeRegAlloc(); 76 77 // Required for target - miscellaneous. 78 void AssembleLIR(); 79 int AssignInsnOffsets(); 80 void AssignOffsets(); 81 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 82 void DumpResourceMask(LIR* lir, uint64_t mask, const char* prefix); 83 void SetupTargetResourceMasks(LIR* lir, uint64_t flags); 84 const char* GetTargetInstFmt(int opcode); 85 const char* GetTargetInstName(int opcode); 86 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr); 87 uint64_t GetPCUseDefEncoding(); 88 uint64_t GetTargetInstFlags(int opcode); 89 int GetInsnSize(LIR* lir); 90 bool IsUnconditionalBranch(LIR* lir); 91 92 // Check support for volatile load/store of a given size. 93 bool SupportsVolatileLoadStore(OpSize size) OVERRIDE; 94 // Get the register class for load/store of a field. 95 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 96 97 // Required for target - Dalvik-level generators. 98 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 99 RegLocation rl_src2); 100 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 101 RegLocation rl_dest, int scale); 102 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 103 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark); 104 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 105 RegLocation rl_src1, RegLocation rl_shift); 106 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 107 RegLocation rl_src2); 108 void GenAddLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 109 RegLocation rl_src2); 110 void GenAndLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 111 RegLocation rl_src2); 112 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 113 RegLocation rl_src2); 114 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 115 RegLocation rl_src2); 116 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 117 RegLocation rl_src2); 118 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src); 119 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object); 120 bool GenInlinedMinMaxInt(CallInfo* info, bool is_min); 121 bool GenInlinedSqrt(CallInfo* info); 122 bool GenInlinedPeek(CallInfo* info, OpSize size); 123 bool GenInlinedPoke(CallInfo* info, OpSize size); 124 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 125 void GenOrLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 126 RegLocation rl_src2); 127 void GenSubLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 128 RegLocation rl_src2); 129 void GenXorLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 130 RegLocation rl_src2); 131 // TODO: collapse reg_lo, reg_hi 132 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div); 133 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div); 134 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); 135 void GenDivZeroCheckWide(RegStorage reg); 136 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 137 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 138 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method); 139 void GenExitSequence(); 140 void GenSpecialExitSequence(); 141 void GenFillArrayData(DexOffset table_offset, RegLocation rl_src); 142 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double); 143 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir); 144 void GenSelect(BasicBlock* bb, MIR* mir); 145 bool GenMemBarrier(MemBarrierKind barrier_kind); 146 void GenMoveException(RegLocation rl_dest); 147 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 148 int first_bit, int second_bit); 149 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src); 150 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src); 151 void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 152 void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src); 153 154 /* 155 * @brief Generate a two address long operation with a constant value 156 * @param rl_dest location of result 157 * @param rl_src constant source operand 158 * @param op Opcode to be generated 159 */ 160 void GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 161 /* 162 * @brief Generate a three address long operation with a constant value 163 * @param rl_dest location of result 164 * @param rl_src1 source operand 165 * @param rl_src2 constant source operand 166 * @param op Opcode to be generated 167 */ 168 void GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 169 Instruction::Code op); 170 171 /** 172 * @brief Generate a long arithmetic operation. 173 * @param rl_dest The destination. 174 * @param rl_src1 First operand. 175 * @param rl_src2 Second operand. 176 * @param op The DEX opcode for the operation. 177 * @param is_commutative The sources can be swapped if needed. 178 */ 179 void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 180 Instruction::Code op, bool is_commutative); 181 182 /** 183 * @brief Generate a two operand long arithmetic operation. 184 * @param rl_dest The destination. 185 * @param rl_src Second operand. 186 * @param op The DEX opcode for the operation. 187 */ 188 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 189 190 /** 191 * @brief Generate a long operation. 192 * @param rl_dest The destination. Must be in a register 193 * @param rl_src The other operand. May be in a register or in memory. 194 * @param op The DEX opcode for the operation. 195 */ 196 void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 197 198 /** 199 * @brief Implement instanceof a final class with x86 specific code. 200 * @param use_declaring_class 'true' if we can use the class itself. 201 * @param type_idx Type index to use if use_declaring_class is 'false'. 202 * @param rl_dest Result to be set to 0 or 1. 203 * @param rl_src Object to be tested. 204 */ 205 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 206 RegLocation rl_src); 207 /* 208 * 209 * @brief Implement Set up instanceof a class with x86 specific code. 210 * @param needs_access_check 'true' if we must check the access. 211 * @param type_known_final 'true' if the type is known to be a final class. 212 * @param type_known_abstract 'true' if the type is known to be an abstract class. 213 * @param use_declaring_class 'true' if the type can be loaded off the current Method*. 214 * @param can_assume_type_is_in_dex_cache 'true' if the type is known to be in the cache. 215 * @param type_idx Type index to use if use_declaring_class is 'false'. 216 * @param rl_dest Result to be set to 0 or 1. 217 * @param rl_src Object to be tested. 218 */ 219 void GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 220 bool type_known_abstract, bool use_declaring_class, 221 bool can_assume_type_is_in_dex_cache, 222 uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src); 223 224 // Single operation generators. 225 LIR* OpUnconditionalBranch(LIR* target); 226 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target); 227 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target); 228 LIR* OpCondBranch(ConditionCode cc, LIR* target); 229 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target); 230 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src); 231 LIR* OpIT(ConditionCode cond, const char* guide); 232 void OpEndIT(LIR* it); 233 LIR* OpMem(OpKind op, RegStorage r_base, int disp); 234 LIR* OpPcRelLoad(RegStorage reg, LIR* target); 235 LIR* OpReg(OpKind op, RegStorage r_dest_src); 236 void OpRegCopy(RegStorage r_dest, RegStorage r_src); 237 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src); 238 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value); 239 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 240 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 241 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 242 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2); 243 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type); 244 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type); 245 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src); 246 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); 247 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); 248 LIR* OpTestSuspend(LIR* target); 249 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset) OVERRIDE; 250 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset) OVERRIDE; 251 LIR* OpVldm(RegStorage r_base, int count); 252 LIR* OpVstm(RegStorage r_base, int count); 253 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 254 void OpRegCopyWide(RegStorage dest, RegStorage src); 255 void OpTlsCmp(ThreadOffset<4> offset, int val) OVERRIDE; 256 void OpTlsCmp(ThreadOffset<8> offset, int val) OVERRIDE; 257 258 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 259 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 260 void SpillCoreRegs(); 261 void UnSpillCoreRegs(); 262 static const X86EncodingMap EncodingMap[kX86Last]; 263 bool InexpensiveConstantInt(int32_t value); 264 bool InexpensiveConstantFloat(int32_t value); 265 bool InexpensiveConstantLong(int64_t value); 266 bool InexpensiveConstantDouble(int64_t value); 267 268 /* 269 * @brief x86 specific codegen for int operations. 270 * @param opcode Operation to perform. 271 * @param rl_dest Destination for the result. 272 * @param rl_lhs Left hand operand. 273 * @param rl_rhs Right hand operand. 274 */ 275 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 276 RegLocation rl_rhs); 277 278 /* 279 * @brief Dump a RegLocation using printf 280 * @param loc Register location to dump 281 */ 282 static void DumpRegLocation(RegLocation loc); 283 284 /* 285 * @brief Load the Method* of a dex method into the register. 286 * @param target_method The MethodReference of the method to be invoked. 287 * @param type How the method will be invoked. 288 * @param register that will contain the code address. 289 * @note register will be passed to TargetReg to get physical register. 290 */ 291 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 292 SpecialTargetRegister symbolic_reg); 293 294 /* 295 * @brief Load the Class* of a Dex Class type into the register. 296 * @param type How the method will be invoked. 297 * @param register that will contain the code address. 298 * @note register will be passed to TargetReg to get physical register. 299 */ 300 void LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg); 301 302 /* 303 * @brief Generate a relative call to the method that will be patched at link time. 304 * @param target_method The MethodReference of the method to be invoked. 305 * @param type How the method will be invoked. 306 * @returns Call instruction 307 */ 308 LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 309 310 /* 311 * @brief Handle x86 specific literals 312 */ 313 void InstallLiteralPools(); 314 315 /* 316 * @brief Generate the debug_frame CFI information. 317 * @returns pointer to vector containing CFE information 318 */ 319 static std::vector<uint8_t>* ReturnCommonCallFrameInformation(); 320 321 /* 322 * @brief Generate the debug_frame FDE information. 323 * @returns pointer to vector containing CFE information 324 */ 325 std::vector<uint8_t>* ReturnCallFrameInformation(); 326 327 private: 328 void EmitPrefix(const X86EncodingMap* entry); 329 void EmitOpcode(const X86EncodingMap* entry); 330 void EmitPrefixAndOpcode(const X86EncodingMap* entry); 331 void EmitDisp(uint8_t base, int disp); 332 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int disp); 333 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, int disp); 334 void EmitImm(const X86EncodingMap* entry, int imm); 335 void EmitOpRegOpcode(const X86EncodingMap* entry, uint8_t reg); 336 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); 337 void EmitOpMem(const X86EncodingMap* entry, uint8_t base, int disp); 338 void EmitOpArray(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp); 339 void EmitMemReg(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg); 340 void EmitMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int32_t imm); 341 void EmitRegMem(const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp); 342 void EmitRegArray(const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, 343 int scale, int disp); 344 void EmitArrayReg(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 345 uint8_t reg); 346 void EmitArrayImm(const X86EncodingMap* entry, uint8_t base, uint8_t index, int scale, int disp, 347 int32_t imm); 348 void EmitRegThread(const X86EncodingMap* entry, uint8_t reg, int disp); 349 void EmitRegReg(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2); 350 void EmitRegRegImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 351 void EmitRegRegImmRev(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, int32_t imm); 352 void EmitRegMemImm(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int disp, 353 int32_t imm); 354 void EmitMemRegImm(const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg1, int32_t imm); 355 void EmitRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 356 void EmitThreadImm(const X86EncodingMap* entry, int disp, int imm); 357 void EmitMovRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 358 void EmitShiftRegImm(const X86EncodingMap* entry, uint8_t reg, int imm); 359 void EmitShiftMemImm(const X86EncodingMap* entry, uint8_t base, int disp, int imm); 360 void EmitShiftMemCl(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t cl); 361 void EmitShiftRegCl(const X86EncodingMap* entry, uint8_t reg, uint8_t cl); 362 void EmitRegCond(const X86EncodingMap* entry, uint8_t reg, uint8_t condition); 363 void EmitMemCond(const X86EncodingMap* entry, uint8_t base, int displacement, uint8_t condition); 364 365 /** 366 * @brief Used for encoding conditional register to register operation. 367 * @param entry The entry in the encoding map for the opcode. 368 * @param reg1 The first physical register. 369 * @param reg2 The second physical register. 370 * @param condition The condition code for operation. 371 */ 372 void EmitRegRegCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2, uint8_t condition); 373 374 /** 375 * @brief Used for encoding conditional register to memory operation. 376 * @param entry The entry in the encoding map for the opcode. 377 * @param reg1 The first physical register. 378 * @param base The memory base register. 379 * @param displacement The memory displacement. 380 * @param condition The condition code for operation. 381 */ 382 void EmitRegMemCond(const X86EncodingMap* entry, uint8_t reg1, uint8_t base, int displacement, uint8_t condition); 383 384 void EmitJmp(const X86EncodingMap* entry, int rel); 385 void EmitJcc(const X86EncodingMap* entry, int rel, uint8_t cc); 386 void EmitCallMem(const X86EncodingMap* entry, uint8_t base, int disp); 387 void EmitCallImmediate(const X86EncodingMap* entry, int disp); 388 void EmitCallThread(const X86EncodingMap* entry, int disp); 389 void EmitPcRel(const X86EncodingMap* entry, uint8_t reg, int base_or_table, uint8_t index, 390 int scale, int table_or_disp); 391 void EmitMacro(const X86EncodingMap* entry, uint8_t reg, int offset); 392 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 393 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 394 int64_t val, ConditionCode ccode); 395 void GenConstWide(RegLocation rl_dest, int64_t value); 396 397 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 398 399 /* 400 * @brief generate inline code for fast case of Strng.indexOf. 401 * @param info Call parameters 402 * @param zero_based 'true' if the index into the string is 0. 403 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 404 * generated. 405 */ 406 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 407 408 /* 409 * @brief Return the correct x86 opcode for the Dex operation 410 * @param op Dex opcode for the operation 411 * @param loc Register location of the operand 412 * @param is_high_op 'true' if this is an operation on the high word 413 * @param value Immediate value for the operation. Used for byte variants 414 * @returns the correct x86 opcode to perform the operation 415 */ 416 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 417 418 /* 419 * @brief Return the correct x86 opcode for the Dex operation 420 * @param op Dex opcode for the operation 421 * @param dest location of the destination. May be register or memory. 422 * @param rhs Location for the rhs of the operation. May be in register or memory. 423 * @param is_high_op 'true' if this is an operation on the high word 424 * @returns the correct x86 opcode to perform the operation 425 * @note at most one location may refer to memory 426 */ 427 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 428 bool is_high_op); 429 430 /* 431 * @brief Is this operation a no-op for this opcode and value 432 * @param op Dex opcode for the operation 433 * @param value Immediate value for the operation. 434 * @returns 'true' if the operation will have no effect 435 */ 436 bool IsNoOp(Instruction::Code op, int32_t value); 437 438 /** 439 * @brief Calculate magic number and shift for a given divisor 440 * @param divisor divisor number for calculation 441 * @param magic hold calculated magic number 442 * @param shift hold calculated shift 443 */ 444 void CalculateMagicAndShift(int divisor, int& magic, int& shift); 445 446 /* 447 * @brief Generate an integer div or rem operation. 448 * @param rl_dest Destination Location. 449 * @param rl_src1 Numerator Location. 450 * @param rl_src2 Divisor Location. 451 * @param is_div 'true' if this is a division, 'false' for a remainder. 452 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 453 */ 454 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 455 bool is_div, bool check_zero); 456 457 /* 458 * @brief Generate an integer div or rem operation by a literal. 459 * @param rl_dest Destination Location. 460 * @param rl_src Numerator Location. 461 * @param lit Divisor. 462 * @param is_div 'true' if this is a division, 'false' for a remainder. 463 */ 464 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 465 466 /* 467 * Generate code to implement long shift operations. 468 * @param opcode The DEX opcode to specify the shift type. 469 * @param rl_dest The destination. 470 * @param rl_src The value to be shifted. 471 * @param shift_amount How much to shift. 472 * @returns the RegLocation of the result. 473 */ 474 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 475 RegLocation rl_src, int shift_amount); 476 /* 477 * Generate an imul of a register by a constant or a better sequence. 478 * @param dest Destination Register. 479 * @param src Source Register. 480 * @param val Constant multiplier. 481 */ 482 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 483 484 /* 485 * Generate an imul of a memory location by a constant or a better sequence. 486 * @param dest Destination Register. 487 * @param sreg Symbolic register. 488 * @param displacement Displacement on stack of Symbolic Register. 489 * @param val Constant multiplier. 490 */ 491 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 492 493 /* 494 * @brief Compare memory to immediate, and branch if condition true. 495 * @param cond The condition code that when true will branch to the target. 496 * @param temp_reg A temporary register that can be used if compare memory is not 497 * supported by the architecture. 498 * @param base_reg The register holding the base address. 499 * @param offset The offset from the base. 500 * @param check_value The immediate to compare to. 501 */ 502 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 503 int offset, int check_value, LIR* target); 504 505 /* 506 * Can this operation be using core registers without temporaries? 507 * @param rl_lhs Left hand operand. 508 * @param rl_rhs Right hand operand. 509 * @returns 'true' if the operation can proceed without needing temporary regs. 510 */ 511 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 512 513 /** 514 * @brief Generates inline code for conversion of long to FP by using x87/ 515 * @param rl_dest The destination of the FP. 516 * @param rl_src The source of the long. 517 * @param is_double 'true' if dealing with double, 'false' for float. 518 */ 519 void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 520 521 /* 522 * @brief Perform MIR analysis before compiling method. 523 * @note Invokes Mir2LiR::Materialize after analysis. 524 */ 525 void Materialize(); 526 527 /* 528 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 529 * without regard to data type. In practice, this can result in UpdateLoc returning a 530 * location record for a Dalvik float value in a core register, and vis-versa. For targets 531 * which can inexpensively move data between core and float registers, this can often be a win. 532 * However, for x86 this is generally not a win. These variants of UpdateLoc() 533 * take a register class argument - and will return an in-register location record only if 534 * the value is live in a temp register of the correct class. Additionally, if the value is in 535 * a temp register of the wrong register class, it will be clobbered. 536 */ 537 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 538 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 539 540 /* 541 * @brief Analyze MIR before generating code, to prepare for the code generation. 542 */ 543 void AnalyzeMIR(); 544 545 /* 546 * @brief Analyze one basic block. 547 * @param bb Basic block to analyze. 548 */ 549 void AnalyzeBB(BasicBlock * bb); 550 551 /* 552 * @brief Analyze one extended MIR instruction 553 * @param opcode MIR instruction opcode. 554 * @param bb Basic block containing instruction. 555 * @param mir Extended instruction to analyze. 556 */ 557 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 558 559 /* 560 * @brief Analyze one MIR instruction 561 * @param opcode MIR instruction opcode. 562 * @param bb Basic block containing instruction. 563 * @param mir Instruction to analyze. 564 */ 565 void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 566 567 /* 568 * @brief Analyze one MIR float/double instruction 569 * @param opcode MIR instruction opcode. 570 * @param bb Basic block containing instruction. 571 * @param mir Instruction to analyze. 572 */ 573 void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 574 575 /* 576 * @brief Analyze one use of a double operand. 577 * @param rl_use Double RegLocation for the operand. 578 */ 579 void AnalyzeDoubleUse(RegLocation rl_use); 580 581 // Information derived from analysis of MIR 582 583 // The compiler temporary for the code address of the method. 584 CompilerTemp *base_of_code_; 585 586 // Have we decided to compute a ptr to code and store in temporary VR? 587 bool store_method_addr_; 588 589 // Have we used the stored method address? 590 bool store_method_addr_used_; 591 592 // Instructions to remove if we didn't use the stored method address. 593 LIR* setup_method_address_[2]; 594 595 // Instructions needing patching with Method* values. 596 GrowableArray<LIR*> method_address_insns_; 597 598 // Instructions needing patching with Class Type* values. 599 GrowableArray<LIR*> class_type_address_insns_; 600 601 // Instructions needing patching with PC relative code addresses. 602 GrowableArray<LIR*> call_method_insns_; 603 604 // Prologue decrement of stack pointer. 605 LIR* stack_decrement_; 606 607 // Epilogue increment of stack pointer. 608 LIR* stack_increment_; 609}; 610 611} // namespace art 612 613#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 614