codegen_x86.h revision e39c54ea575ec710d5e84277fcdcc049f8acb3c9
1/* 2 * Copyright (C) 2011 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 18#define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 19 20#include "dex/compiler_internals.h" 21#include "dex/quick/mir_to_lir.h" 22#include "x86_lir.h" 23 24#include <map> 25#include <vector> 26 27namespace art { 28 29class X86Mir2Lir : public Mir2Lir { 30 protected: 31 class InToRegStorageMapper { 32 public: 33 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref) = 0; 34 virtual ~InToRegStorageMapper() {} 35 }; 36 37 class InToRegStorageX86_64Mapper : public InToRegStorageMapper { 38 public: 39 explicit InToRegStorageX86_64Mapper(Mir2Lir* ml) : ml_(ml), cur_core_reg_(0), cur_fp_reg_(0) {} 40 virtual ~InToRegStorageX86_64Mapper() {} 41 virtual RegStorage GetNextReg(bool is_double_or_float, bool is_wide, bool is_ref); 42 protected: 43 Mir2Lir* ml_; 44 private: 45 int cur_core_reg_; 46 int cur_fp_reg_; 47 }; 48 49 class InToRegStorageMapping { 50 public: 51 InToRegStorageMapping() : max_mapped_in_(0), is_there_stack_mapped_(false), 52 initialized_(false) {} 53 void Initialize(RegLocation* arg_locs, int count, InToRegStorageMapper* mapper); 54 int GetMaxMappedIn() { return max_mapped_in_; } 55 bool IsThereStackMapped() { return is_there_stack_mapped_; } 56 RegStorage Get(int in_position); 57 bool IsInitialized() { return initialized_; } 58 private: 59 std::map<int, RegStorage> mapping_; 60 int max_mapped_in_; 61 bool is_there_stack_mapped_; 62 bool initialized_; 63 }; 64 65 class ExplicitTempRegisterLock { 66 public: 67 ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, int n_regs, ...); 68 ~ExplicitTempRegisterLock(); 69 protected: 70 std::vector<RegStorage> temp_regs_; 71 X86Mir2Lir* const mir_to_lir_; 72 }; 73 74 public: 75 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena); 76 77 // Required for target - codegen helpers. 78 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, 79 RegLocation rl_dest, int lit) OVERRIDE; 80 bool EasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) OVERRIDE; 81 LIR* CheckSuspendUsingLoad() OVERRIDE; 82 RegStorage LoadHelper(QuickEntrypointEnum trampoline) OVERRIDE; 83 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, 84 OpSize size, VolatileKind is_volatile) OVERRIDE; 85 LIR* LoadBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_dest, int scale, 86 OpSize size) OVERRIDE; 87 LIR* LoadConstantNoClobber(RegStorage r_dest, int value); 88 LIR* LoadConstantWide(RegStorage r_dest, int64_t value); 89 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, 90 OpSize size, VolatileKind is_volatile) OVERRIDE; 91 LIR* StoreBaseIndexed(RegStorage r_base, RegStorage r_index, RegStorage r_src, int scale, 92 OpSize size) OVERRIDE; 93 void MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) OVERRIDE; 94 void GenImplicitNullCheck(RegStorage reg, int opt_flags) OVERRIDE; 95 96 // Required for target - register utilities. 97 RegStorage TargetReg(SpecialTargetRegister reg) OVERRIDE; 98 RegStorage TargetReg(SpecialTargetRegister symbolic_reg, WideKind wide_kind) OVERRIDE { 99 if (wide_kind == kWide) { 100 if (cu_->target64) { 101 return As64BitReg(TargetReg32(symbolic_reg)); 102 } else { 103 // x86: construct a pair. 104 DCHECK((kArg0 <= symbolic_reg && symbolic_reg < kArg3) || 105 (kFArg0 <= symbolic_reg && symbolic_reg < kFArg3) || 106 (kRet0 == symbolic_reg)); 107 return RegStorage::MakeRegPair(TargetReg32(symbolic_reg), 108 TargetReg32(static_cast<SpecialTargetRegister>(symbolic_reg + 1))); 109 } 110 } else if (wide_kind == kRef && cu_->target64) { 111 return As64BitReg(TargetReg32(symbolic_reg)); 112 } else { 113 return TargetReg32(symbolic_reg); 114 } 115 } 116 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { 117 return TargetReg(symbolic_reg, cu_->target64 ? kWide : kNotWide); 118 } 119 120 RegStorage GetArgMappingToPhysicalReg(int arg_num) OVERRIDE; 121 122 RegLocation GetReturnAlt() OVERRIDE; 123 RegLocation GetReturnWideAlt() OVERRIDE; 124 RegLocation LocCReturn() OVERRIDE; 125 RegLocation LocCReturnRef() OVERRIDE; 126 RegLocation LocCReturnDouble() OVERRIDE; 127 RegLocation LocCReturnFloat() OVERRIDE; 128 RegLocation LocCReturnWide() OVERRIDE; 129 130 ResourceMask GetRegMaskCommon(const RegStorage& reg) const OVERRIDE; 131 void AdjustSpillMask() OVERRIDE; 132 void ClobberCallerSave() OVERRIDE; 133 void FreeCallTemps() OVERRIDE; 134 void LockCallTemps() OVERRIDE; 135 136 void CompilerInitializeRegAlloc() OVERRIDE; 137 int VectorRegisterSize() OVERRIDE; 138 int NumReservableVectorRegisters(bool long_or_fp) OVERRIDE; 139 140 // Required for target - miscellaneous. 141 void AssembleLIR() OVERRIDE; 142 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE; 143 void SetupTargetResourceMasks(LIR* lir, uint64_t flags, 144 ResourceMask* use_mask, ResourceMask* def_mask) OVERRIDE; 145 const char* GetTargetInstFmt(int opcode) OVERRIDE; 146 const char* GetTargetInstName(int opcode) OVERRIDE; 147 std::string BuildInsnString(const char* fmt, LIR* lir, unsigned char* base_addr) OVERRIDE; 148 ResourceMask GetPCUseDefEncoding() const OVERRIDE; 149 uint64_t GetTargetInstFlags(int opcode) OVERRIDE; 150 size_t GetInsnSize(LIR* lir) OVERRIDE; 151 bool IsUnconditionalBranch(LIR* lir) OVERRIDE; 152 153 // Get the register class for load/store of a field. 154 RegisterClass RegClassForFieldLoadStore(OpSize size, bool is_volatile) OVERRIDE; 155 156 // Required for target - Dalvik-level generators. 157 void GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, 158 RegLocation rl_dest, int scale) OVERRIDE; 159 void GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array, 160 RegLocation rl_index, RegLocation rl_src, int scale, bool card_mark) OVERRIDE; 161 162 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 163 RegLocation rl_src2) OVERRIDE; 164 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 165 RegLocation rl_src2) OVERRIDE; 166 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 167 RegLocation rl_src2) OVERRIDE; 168 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 169 170 bool GenInlinedCas(CallInfo* info, bool is_long, bool is_object) OVERRIDE; 171 bool GenInlinedMinMax(CallInfo* info, bool is_min, bool is_long) OVERRIDE; 172 bool GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) OVERRIDE; 173 bool GenInlinedReverseBits(CallInfo* info, OpSize size) OVERRIDE; 174 bool GenInlinedSqrt(CallInfo* info) OVERRIDE; 175 bool GenInlinedAbsFloat(CallInfo* info) OVERRIDE; 176 bool GenInlinedAbsDouble(CallInfo* info) OVERRIDE; 177 bool GenInlinedPeek(CallInfo* info, OpSize size) OVERRIDE; 178 bool GenInlinedPoke(CallInfo* info, OpSize size) OVERRIDE; 179 bool GenInlinedCharAt(CallInfo* info) OVERRIDE; 180 181 // Long instructions. 182 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 183 RegLocation rl_src2) OVERRIDE; 184 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 185 RegLocation rl_src2) OVERRIDE; 186 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 187 RegLocation rl_src1, RegLocation rl_shift) OVERRIDE; 188 void GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) OVERRIDE; 189 void GenIntToLong(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 190 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 191 RegLocation rl_src1, RegLocation rl_shift) OVERRIDE; 192 193 /* 194 * @brief Generate a two address long operation with a constant value 195 * @param rl_dest location of result 196 * @param rl_src constant source operand 197 * @param op Opcode to be generated 198 * @return success or not 199 */ 200 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 201 202 /* 203 * @brief Generate a three address long operation with a constant value 204 * @param rl_dest location of result 205 * @param rl_src1 source operand 206 * @param rl_src2 constant source operand 207 * @param op Opcode to be generated 208 * @return success or not 209 */ 210 bool GenLongLongImm(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 211 Instruction::Code op); 212 /** 213 * @brief Generate a long arithmetic operation. 214 * @param rl_dest The destination. 215 * @param rl_src1 First operand. 216 * @param rl_src2 Second operand. 217 * @param op The DEX opcode for the operation. 218 * @param is_commutative The sources can be swapped if needed. 219 */ 220 virtual void GenLongArith(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 221 Instruction::Code op, bool is_commutative); 222 223 /** 224 * @brief Generate a two operand long arithmetic operation. 225 * @param rl_dest The destination. 226 * @param rl_src Second operand. 227 * @param op The DEX opcode for the operation. 228 */ 229 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 230 231 /** 232 * @brief Generate a long operation. 233 * @param rl_dest The destination. Must be in a register 234 * @param rl_src The other operand. May be in a register or in memory. 235 * @param op The DEX opcode for the operation. 236 */ 237 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op); 238 239 240 // TODO: collapse reg_lo, reg_hi 241 RegLocation GenDivRem(RegLocation rl_dest, RegStorage reg_lo, RegStorage reg_hi, bool is_div) 242 OVERRIDE; 243 RegLocation GenDivRemLit(RegLocation rl_dest, RegStorage reg_lo, int lit, bool is_div) OVERRIDE; 244 void GenDivZeroCheckWide(RegStorage reg) OVERRIDE; 245 void GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; 246 void GenExitSequence() OVERRIDE; 247 void GenSpecialExitSequence() OVERRIDE; 248 void GenFillArrayData(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 249 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double) OVERRIDE; 250 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) OVERRIDE; 251 void GenSelect(BasicBlock* bb, MIR* mir) OVERRIDE; 252 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, 253 int32_t true_val, int32_t false_val, RegStorage rs_dest, 254 int dest_reg_class) OVERRIDE; 255 bool GenMemBarrier(MemBarrierKind barrier_kind) OVERRIDE; 256 void GenMoveException(RegLocation rl_dest) OVERRIDE; 257 void GenMultiplyByTwoBitMultiplier(RegLocation rl_src, RegLocation rl_result, int lit, 258 int first_bit, int second_bit) OVERRIDE; 259 void GenNegDouble(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 260 void GenNegFloat(RegLocation rl_dest, RegLocation rl_src) OVERRIDE; 261 void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 262 void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) OVERRIDE; 263 264 /** 265 * @brief Implement instanceof a final class with x86 specific code. 266 * @param use_declaring_class 'true' if we can use the class itself. 267 * @param type_idx Type index to use if use_declaring_class is 'false'. 268 * @param rl_dest Result to be set to 0 or 1. 269 * @param rl_src Object to be tested. 270 */ 271 void GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 272 RegLocation rl_src) OVERRIDE; 273 274 // Single operation generators. 275 LIR* OpUnconditionalBranch(LIR* target) OVERRIDE; 276 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE; 277 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE; 278 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE; 279 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE; 280 LIR* OpFpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 281 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE; 282 void OpEndIT(LIR* it) OVERRIDE; 283 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE; 284 LIR* OpPcRelLoad(RegStorage reg, LIR* target) OVERRIDE; 285 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE; 286 void OpRegCopy(RegStorage r_dest, RegStorage r_src) OVERRIDE; 287 LIR* OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) OVERRIDE; 288 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE; 289 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE; 290 LIR* OpMovRegMem(RegStorage r_dest, RegStorage r_base, int offset, MoveType move_type) OVERRIDE; 291 LIR* OpMovMemReg(RegStorage r_base, int offset, RegStorage r_src, MoveType move_type) OVERRIDE; 292 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE; 293 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE; 294 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE; 295 LIR* OpTestSuspend(LIR* target) OVERRIDE; 296 LIR* OpVldm(RegStorage r_base, int count) OVERRIDE; 297 LIR* OpVstm(RegStorage r_base, int count) OVERRIDE; 298 void OpRegCopyWide(RegStorage dest, RegStorage src) OVERRIDE; 299 bool GenInlinedCurrentThread(CallInfo* info) OVERRIDE; 300 301 bool InexpensiveConstantInt(int32_t value) OVERRIDE; 302 bool InexpensiveConstantFloat(int32_t value) OVERRIDE; 303 bool InexpensiveConstantLong(int64_t value) OVERRIDE; 304 bool InexpensiveConstantDouble(int64_t value) OVERRIDE; 305 306 /* 307 * @brief Should try to optimize for two address instructions? 308 * @return true if we try to avoid generating three operand instructions. 309 */ 310 virtual bool GenerateTwoOperandInstructions() const { return true; } 311 312 /* 313 * @brief x86 specific codegen for int operations. 314 * @param opcode Operation to perform. 315 * @param rl_dest Destination for the result. 316 * @param rl_lhs Left hand operand. 317 * @param rl_rhs Right hand operand. 318 */ 319 void GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_lhs, 320 RegLocation rl_rhs) OVERRIDE; 321 322 /* 323 * @brief Load the Method* of a dex method into the register. 324 * @param target_method The MethodReference of the method to be invoked. 325 * @param type How the method will be invoked. 326 * @param register that will contain the code address. 327 * @note register will be passed to TargetReg to get physical register. 328 */ 329 void LoadMethodAddress(const MethodReference& target_method, InvokeType type, 330 SpecialTargetRegister symbolic_reg) OVERRIDE; 331 332 /* 333 * @brief Load the Class* of a Dex Class type into the register. 334 * @param dex DexFile that contains the class type. 335 * @param type How the method will be invoked. 336 * @param register that will contain the code address. 337 * @note register will be passed to TargetReg to get physical register. 338 */ 339 void LoadClassType(const DexFile& dex_file, uint32_t type_idx, 340 SpecialTargetRegister symbolic_reg) OVERRIDE; 341 342 void FlushIns(RegLocation* ArgLocs, RegLocation rl_method) OVERRIDE; 343 344 int GenDalvikArgsNoRange(CallInfo* info, int call_state, LIR** pcrLabel, 345 NextCallInsn next_call_insn, 346 const MethodReference& target_method, 347 uint32_t vtable_idx, 348 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 349 bool skip_this) OVERRIDE; 350 351 int GenDalvikArgsRange(CallInfo* info, int call_state, LIR** pcrLabel, 352 NextCallInsn next_call_insn, 353 const MethodReference& target_method, 354 uint32_t vtable_idx, 355 uintptr_t direct_code, uintptr_t direct_method, InvokeType type, 356 bool skip_this) OVERRIDE; 357 358 /* 359 * @brief Generate a relative call to the method that will be patched at link time. 360 * @param target_method The MethodReference of the method to be invoked. 361 * @param type How the method will be invoked. 362 * @returns Call instruction 363 */ 364 virtual LIR * CallWithLinkerFixup(const MethodReference& target_method, InvokeType type); 365 366 /* 367 * @brief Handle x86 specific literals 368 */ 369 void InstallLiteralPools() OVERRIDE; 370 371 /* 372 * @brief Generate the debug_frame FDE information. 373 * @returns pointer to vector containing CFE information 374 */ 375 std::vector<uint8_t>* ReturnFrameDescriptionEntry() OVERRIDE; 376 377 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE; 378 379 protected: 380 RegStorage TargetReg32(SpecialTargetRegister reg); 381 // Casting of RegStorage 382 RegStorage As32BitReg(RegStorage reg) { 383 DCHECK(!reg.IsPair()); 384 if ((kFailOnSizeError || kReportSizeError) && !reg.Is64Bit()) { 385 if (kFailOnSizeError) { 386 LOG(FATAL) << "Expected 64b register " << reg.GetReg(); 387 } else { 388 LOG(WARNING) << "Expected 64b register " << reg.GetReg(); 389 return reg; 390 } 391 } 392 RegStorage ret_val = RegStorage(RegStorage::k32BitSolo, 393 reg.GetRawBits() & RegStorage::kRegTypeMask); 394 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k32SoloStorageMask) 395 ->GetReg().GetReg(), 396 ret_val.GetReg()); 397 return ret_val; 398 } 399 400 RegStorage As64BitReg(RegStorage reg) { 401 DCHECK(!reg.IsPair()); 402 if ((kFailOnSizeError || kReportSizeError) && !reg.Is32Bit()) { 403 if (kFailOnSizeError) { 404 LOG(FATAL) << "Expected 32b register " << reg.GetReg(); 405 } else { 406 LOG(WARNING) << "Expected 32b register " << reg.GetReg(); 407 return reg; 408 } 409 } 410 RegStorage ret_val = RegStorage(RegStorage::k64BitSolo, 411 reg.GetRawBits() & RegStorage::kRegTypeMask); 412 DCHECK_EQ(GetRegInfo(reg)->FindMatchingView(RegisterInfo::k64SoloStorageMask) 413 ->GetReg().GetReg(), 414 ret_val.GetReg()); 415 return ret_val; 416 } 417 418 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 419 RegStorage r_dest, OpSize size); 420 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement, 421 RegStorage r_src, OpSize size, int opt_flags = 0); 422 423 RegStorage GetCoreArgMappingToPhysicalReg(int core_arg_num); 424 425 int AssignInsnOffsets(); 426 void AssignOffsets(); 427 AssemblerStatus AssembleInstructions(CodeOffset start_addr); 428 429 size_t ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, 430 int32_t raw_base, int32_t displacement); 431 void CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg); 432 void EmitPrefix(const X86EncodingMap* entry, 433 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b); 434 void EmitOpcode(const X86EncodingMap* entry); 435 void EmitPrefixAndOpcode(const X86EncodingMap* entry, 436 int32_t reg_r, int32_t reg_x, int32_t reg_b); 437 void EmitDisp(uint8_t base, int32_t disp); 438 void EmitModrmThread(uint8_t reg_or_opcode); 439 void EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp); 440 void EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index, int scale, 441 int32_t disp); 442 void EmitImm(const X86EncodingMap* entry, int64_t imm); 443 void EmitNullary(const X86EncodingMap* entry); 444 void EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg); 445 void EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg); 446 void EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 447 void EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 448 int32_t disp); 449 void EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_reg); 450 void EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, int32_t disp); 451 void EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base, 452 int32_t raw_index, int scale, int32_t disp); 453 void EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 454 int32_t disp, int32_t raw_reg); 455 void EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 456 void EmitArrayImm(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index, int scale, 457 int32_t raw_disp, int32_t imm); 458 void EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp); 459 void EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2); 460 void EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t imm); 461 void EmitRegMemImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 462 int32_t imm); 463 void EmitMemRegImm(const X86EncodingMap* entry, int32_t base, int32_t disp, int32_t raw_reg1, 464 int32_t imm); 465 void EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 466 void EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm); 467 void EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm); 468 void EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm); 469 void EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl); 470 void EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t raw_cl); 471 void EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, 472 int32_t raw_cl); 473 void EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t imm); 474 void EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc); 475 void EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp, int32_t cc); 476 void EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t cc); 477 void EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base, int32_t disp, 478 int32_t cc); 479 480 void EmitJmp(const X86EncodingMap* entry, int32_t rel); 481 void EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc); 482 void EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp); 483 void EmitCallImmediate(const X86EncodingMap* entry, int32_t disp); 484 void EmitCallThread(const X86EncodingMap* entry, int32_t disp); 485 void EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table, 486 int32_t raw_index, int scale, int32_t table_or_disp); 487 void EmitMacro(const X86EncodingMap* entry, int32_t raw_reg, int32_t offset); 488 void EmitUnimplemented(const X86EncodingMap* entry, LIR* lir); 489 void GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, 490 int64_t val, ConditionCode ccode); 491 void GenConstWide(RegLocation rl_dest, int64_t value); 492 void GenMultiplyVectorSignedByte(RegStorage rs_dest_src1, RegStorage rs_src2); 493 void GenMultiplyVectorLong(RegStorage rs_dest_src1, RegStorage rs_src2); 494 void GenShiftByteVector(BasicBlock *bb, MIR *mir); 495 void AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, 496 uint32_t m4); 497 void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, 498 uint32_t m3, uint32_t m4); 499 void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); 500 virtual void LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, OpSize opsize, 501 int op_mov); 502 503 static bool ProvidesFullMemoryBarrier(X86OpCode opcode); 504 505 /* 506 * @brief Ensure that a temporary register is byte addressable. 507 * @returns a temporary guarenteed to be byte addressable. 508 */ 509 virtual RegStorage AllocateByteRegister(); 510 511 /* 512 * @brief Use a wide temporary as a 128-bit register 513 * @returns a 128-bit temporary register. 514 */ 515 virtual RegStorage Get128BitRegister(RegStorage reg); 516 517 /* 518 * @brief Check if a register is byte addressable. 519 * @returns true if a register is byte addressable. 520 */ 521 bool IsByteRegister(RegStorage reg); 522 523 void GenDivRemLongLit(RegLocation rl_dest, RegLocation rl_src, int64_t imm, bool is_div); 524 525 bool GenInlinedArrayCopyCharArray(CallInfo* info) OVERRIDE; 526 527 /* 528 * @brief generate inline code for fast case of Strng.indexOf. 529 * @param info Call parameters 530 * @param zero_based 'true' if the index into the string is 0. 531 * @returns 'true' if the call was inlined, 'false' if a regular call needs to be 532 * generated. 533 */ 534 bool GenInlinedIndexOf(CallInfo* info, bool zero_based); 535 536 /** 537 * @brief Used to reserve a range of vector registers. 538 * @see kMirOpReserveVectorRegisters 539 * @param mir The extended MIR for reservation. 540 */ 541 void ReserveVectorRegisters(MIR* mir); 542 543 /** 544 * @brief Used to return a range of vector registers. 545 * @see kMirOpReturnVectorRegisters 546 * @param mir The extended MIR for returning vector regs. 547 */ 548 void ReturnVectorRegisters(MIR* mir); 549 550 /* 551 * @brief Load 128 bit constant into vector register. 552 * @param bb The basic block in which the MIR is from. 553 * @param mir The MIR whose opcode is kMirConstVector 554 * @note vA is the TypeSize for the register. 555 * @note vB is the destination XMM register. arg[0..3] are 32 bit constant values. 556 */ 557 void GenConst128(BasicBlock* bb, MIR* mir); 558 559 /* 560 * @brief MIR to move a vectorized register to another. 561 * @param bb The basic block in which the MIR is from. 562 * @param mir The MIR whose opcode is kMirConstVector. 563 * @note vA: TypeSize 564 * @note vB: destination 565 * @note vC: source 566 */ 567 void GenMoveVector(BasicBlock *bb, MIR *mir); 568 569 /* 570 * @brief Packed multiply of units in two vector registers: vB = vB .* @note vC using vA to know 571 * the type of the vector. 572 * @param bb The basic block in which the MIR is from. 573 * @param mir The MIR whose opcode is kMirConstVector. 574 * @note vA: TypeSize 575 * @note vB: destination and source 576 * @note vC: source 577 */ 578 void GenMultiplyVector(BasicBlock *bb, MIR *mir); 579 580 /* 581 * @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the 582 * type of the vector. 583 * @param bb The basic block in which the MIR is from. 584 * @param mir The MIR whose opcode is kMirConstVector. 585 * @note vA: TypeSize 586 * @note vB: destination and source 587 * @note vC: source 588 */ 589 void GenAddVector(BasicBlock *bb, MIR *mir); 590 591 /* 592 * @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the 593 * type of the vector. 594 * @param bb The basic block in which the MIR is from. 595 * @param mir The MIR whose opcode is kMirConstVector. 596 * @note vA: TypeSize 597 * @note vB: destination and source 598 * @note vC: source 599 */ 600 void GenSubtractVector(BasicBlock *bb, MIR *mir); 601 602 /* 603 * @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the 604 * type of the vector. 605 * @param bb The basic block in which the MIR is from. 606 * @param mir The MIR whose opcode is kMirConstVector. 607 * @note vA: TypeSize 608 * @note vB: destination and source 609 * @note vC: immediate 610 */ 611 void GenShiftLeftVector(BasicBlock *bb, MIR *mir); 612 613 /* 614 * @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to 615 * know the type of the vector. 616 * @param bb The basic block in which the MIR is from. 617 * @param mir The MIR whose opcode is kMirConstVector. 618 * @note vA: TypeSize 619 * @note vB: destination and source 620 * @note vC: immediate 621 */ 622 void GenSignedShiftRightVector(BasicBlock *bb, MIR *mir); 623 624 /* 625 * @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA 626 * to know the type of the vector. 627 * @param bb The basic block in which the MIR is from.. 628 * @param mir The MIR whose opcode is kMirConstVector. 629 * @note vA: TypeSize 630 * @note vB: destination and source 631 * @note vC: immediate 632 */ 633 void GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir); 634 635 /* 636 * @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the 637 * type of the vector. 638 * @note vA: TypeSize 639 * @note vB: destination and source 640 * @note vC: source 641 */ 642 void GenAndVector(BasicBlock *bb, MIR *mir); 643 644 /* 645 * @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the 646 * type of the vector. 647 * @param bb The basic block in which the MIR is from. 648 * @param mir The MIR whose opcode is kMirConstVector. 649 * @note vA: TypeSize 650 * @note vB: destination and source 651 * @note vC: source 652 */ 653 void GenOrVector(BasicBlock *bb, MIR *mir); 654 655 /* 656 * @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the 657 * type of the vector. 658 * @param bb The basic block in which the MIR is from. 659 * @param mir The MIR whose opcode is kMirConstVector. 660 * @note vA: TypeSize 661 * @note vB: destination and source 662 * @note vC: source 663 */ 664 void GenXorVector(BasicBlock *bb, MIR *mir); 665 666 /* 667 * @brief Reduce a 128-bit packed element into a single VR by taking lower bits 668 * @param bb The basic block in which the MIR is from. 669 * @param mir The MIR whose opcode is kMirConstVector. 670 * @details Instruction does a horizontal addition of the packed elements and then adds it to VR. 671 * @note vA: TypeSize 672 * @note vB: destination and source VR (not vector register) 673 * @note vC: source (vector register) 674 */ 675 void GenAddReduceVector(BasicBlock *bb, MIR *mir); 676 677 /* 678 * @brief Extract a packed element into a single VR. 679 * @param bb The basic block in which the MIR is from. 680 * @param mir The MIR whose opcode is kMirConstVector. 681 * @note vA: TypeSize 682 * @note vB: destination VR (not vector register) 683 * @note vC: source (vector register) 684 * @note arg[0]: The index to use for extraction from vector register (which packed element). 685 */ 686 void GenReduceVector(BasicBlock *bb, MIR *mir); 687 688 /* 689 * @brief Create a vector value, with all TypeSize values equal to vC 690 * @param bb The basic block in which the MIR is from. 691 * @param mir The MIR whose opcode is kMirConstVector. 692 * @note vA: TypeSize. 693 * @note vB: destination vector register. 694 * @note vC: source VR (not vector register). 695 */ 696 void GenSetVector(BasicBlock *bb, MIR *mir); 697 698 /** 699 * @brief Used to generate code for kMirOpPackedArrayGet. 700 * @param bb The basic block of MIR. 701 * @param mir The mir whose opcode is kMirOpPackedArrayGet. 702 */ 703 void GenPackedArrayGet(BasicBlock *bb, MIR *mir); 704 705 /** 706 * @brief Used to generate code for kMirOpPackedArrayPut. 707 * @param bb The basic block of MIR. 708 * @param mir The mir whose opcode is kMirOpPackedArrayPut. 709 */ 710 void GenPackedArrayPut(BasicBlock *bb, MIR *mir); 711 712 /* 713 * @brief Generate code for a vector opcode. 714 * @param bb The basic block in which the MIR is from. 715 * @param mir The MIR whose opcode is a non-standard opcode. 716 */ 717 void GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir); 718 719 /* 720 * @brief Return the correct x86 opcode for the Dex operation 721 * @param op Dex opcode for the operation 722 * @param loc Register location of the operand 723 * @param is_high_op 'true' if this is an operation on the high word 724 * @param value Immediate value for the operation. Used for byte variants 725 * @returns the correct x86 opcode to perform the operation 726 */ 727 X86OpCode GetOpcode(Instruction::Code op, RegLocation loc, bool is_high_op, int32_t value); 728 729 /* 730 * @brief Return the correct x86 opcode for the Dex operation 731 * @param op Dex opcode for the operation 732 * @param dest location of the destination. May be register or memory. 733 * @param rhs Location for the rhs of the operation. May be in register or memory. 734 * @param is_high_op 'true' if this is an operation on the high word 735 * @returns the correct x86 opcode to perform the operation 736 * @note at most one location may refer to memory 737 */ 738 X86OpCode GetOpcode(Instruction::Code op, RegLocation dest, RegLocation rhs, 739 bool is_high_op); 740 741 /* 742 * @brief Is this operation a no-op for this opcode and value 743 * @param op Dex opcode for the operation 744 * @param value Immediate value for the operation. 745 * @returns 'true' if the operation will have no effect 746 */ 747 bool IsNoOp(Instruction::Code op, int32_t value); 748 749 /** 750 * @brief Calculate magic number and shift for a given divisor 751 * @param divisor divisor number for calculation 752 * @param magic hold calculated magic number 753 * @param shift hold calculated shift 754 * @param is_long 'true' if divisor is jlong, 'false' for jint. 755 */ 756 void CalculateMagicAndShift(int64_t divisor, int64_t& magic, int& shift, bool is_long); 757 758 /* 759 * @brief Generate an integer div or rem operation. 760 * @param rl_dest Destination Location. 761 * @param rl_src1 Numerator Location. 762 * @param rl_src2 Divisor Location. 763 * @param is_div 'true' if this is a division, 'false' for a remainder. 764 * @param check_zero 'true' if an exception should be generated if the divisor is 0. 765 */ 766 RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, 767 bool is_div, bool check_zero); 768 769 /* 770 * @brief Generate an integer div or rem operation by a literal. 771 * @param rl_dest Destination Location. 772 * @param rl_src Numerator Location. 773 * @param lit Divisor. 774 * @param is_div 'true' if this is a division, 'false' for a remainder. 775 */ 776 RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src, int lit, bool is_div); 777 778 /* 779 * Generate code to implement long shift operations. 780 * @param opcode The DEX opcode to specify the shift type. 781 * @param rl_dest The destination. 782 * @param rl_src The value to be shifted. 783 * @param shift_amount How much to shift. 784 * @returns the RegLocation of the result. 785 */ 786 RegLocation GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, 787 RegLocation rl_src, int shift_amount); 788 /* 789 * Generate an imul of a register by a constant or a better sequence. 790 * @param dest Destination Register. 791 * @param src Source Register. 792 * @param val Constant multiplier. 793 */ 794 void GenImulRegImm(RegStorage dest, RegStorage src, int val); 795 796 /* 797 * Generate an imul of a memory location by a constant or a better sequence. 798 * @param dest Destination Register. 799 * @param sreg Symbolic register. 800 * @param displacement Displacement on stack of Symbolic Register. 801 * @param val Constant multiplier. 802 */ 803 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val); 804 805 /* 806 * @brief Compare memory to immediate, and branch if condition true. 807 * @param cond The condition code that when true will branch to the target. 808 * @param temp_reg A temporary register that can be used if compare memory is not 809 * supported by the architecture. 810 * @param base_reg The register holding the base address. 811 * @param offset The offset from the base. 812 * @param check_value The immediate to compare to. 813 * @param target branch target (or nullptr) 814 * @param compare output for getting LIR for comparison (or nullptr) 815 */ 816 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, 817 int offset, int check_value, LIR* target, LIR** compare); 818 819 void GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_double); 820 821 /* 822 * Can this operation be using core registers without temporaries? 823 * @param rl_lhs Left hand operand. 824 * @param rl_rhs Right hand operand. 825 * @returns 'true' if the operation can proceed without needing temporary regs. 826 */ 827 bool IsOperationSafeWithoutTemps(RegLocation rl_lhs, RegLocation rl_rhs); 828 829 /** 830 * @brief Generates inline code for conversion of long to FP by using x87/ 831 * @param rl_dest The destination of the FP. 832 * @param rl_src The source of the long. 833 * @param is_double 'true' if dealing with double, 'false' for float. 834 */ 835 virtual void GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double); 836 837 void GenArrayBoundsCheck(RegStorage index, RegStorage array_base, int32_t len_offset); 838 void GenArrayBoundsCheck(int32_t index, RegStorage array_base, int32_t len_offset); 839 840 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegStorage r_base, int offset); 841 LIR* OpRegMem(OpKind op, RegStorage r_dest, RegLocation value); 842 LIR* OpMemReg(OpKind op, RegLocation rl_dest, int value); 843 LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); 844 LIR* OpThreadMem(OpKind op, ThreadOffset<8> thread_offset); 845 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<4> thread_offset); 846 void OpRegThreadMem(OpKind op, RegStorage r_dest, ThreadOffset<8> thread_offset); 847 void OpTlsCmp(ThreadOffset<4> offset, int val); 848 void OpTlsCmp(ThreadOffset<8> offset, int val); 849 850 void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); 851 852 // Try to do a long multiplication where rl_src2 is a constant. This simplified setup might fail, 853 // in which case false will be returned. 854 bool GenMulLongConst(RegLocation rl_dest, RegLocation rl_src1, int64_t val); 855 void GenMulLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1, 856 RegLocation rl_src2); 857 void GenNotLong(RegLocation rl_dest, RegLocation rl_src); 858 void GenNegLong(RegLocation rl_dest, RegLocation rl_src); 859 void GenDivRemLong(Instruction::Code, RegLocation rl_dest, RegLocation rl_src1, 860 RegLocation rl_src2, bool is_div); 861 862 void SpillCoreRegs(); 863 void UnSpillCoreRegs(); 864 void UnSpillFPRegs(); 865 void SpillFPRegs(); 866 867 /* 868 * @brief Perform MIR analysis before compiling method. 869 * @note Invokes Mir2LiR::Materialize after analysis. 870 */ 871 void Materialize(); 872 873 /* 874 * Mir2Lir's UpdateLoc() looks to see if the Dalvik value is currently live in any temp register 875 * without regard to data type. In practice, this can result in UpdateLoc returning a 876 * location record for a Dalvik float value in a core register, and vis-versa. For targets 877 * which can inexpensively move data between core and float registers, this can often be a win. 878 * However, for x86 this is generally not a win. These variants of UpdateLoc() 879 * take a register class argument - and will return an in-register location record only if 880 * the value is live in a temp register of the correct class. Additionally, if the value is in 881 * a temp register of the wrong register class, it will be clobbered. 882 */ 883 RegLocation UpdateLocTyped(RegLocation loc, int reg_class); 884 RegLocation UpdateLocWideTyped(RegLocation loc, int reg_class); 885 886 /* 887 * @brief Analyze MIR before generating code, to prepare for the code generation. 888 */ 889 void AnalyzeMIR(); 890 891 /* 892 * @brief Analyze one basic block. 893 * @param bb Basic block to analyze. 894 */ 895 void AnalyzeBB(BasicBlock * bb); 896 897 /* 898 * @brief Analyze one extended MIR instruction 899 * @param opcode MIR instruction opcode. 900 * @param bb Basic block containing instruction. 901 * @param mir Extended instruction to analyze. 902 */ 903 void AnalyzeExtendedMIR(int opcode, BasicBlock * bb, MIR *mir); 904 905 /* 906 * @brief Analyze one MIR instruction 907 * @param opcode MIR instruction opcode. 908 * @param bb Basic block containing instruction. 909 * @param mir Instruction to analyze. 910 */ 911 virtual void AnalyzeMIR(int opcode, BasicBlock * bb, MIR *mir); 912 913 /* 914 * @brief Analyze one MIR float/double instruction 915 * @param opcode MIR instruction opcode. 916 * @param bb Basic block containing instruction. 917 * @param mir Instruction to analyze. 918 */ 919 virtual void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); 920 921 /* 922 * @brief Analyze one use of a double operand. 923 * @param rl_use Double RegLocation for the operand. 924 */ 925 void AnalyzeDoubleUse(RegLocation rl_use); 926 927 /* 928 * @brief Analyze one invoke-static MIR instruction 929 * @param opcode MIR instruction opcode. 930 * @param bb Basic block containing instruction. 931 * @param mir Instruction to analyze. 932 */ 933 void AnalyzeInvokeStatic(int opcode, BasicBlock * bb, MIR *mir); 934 935 // Information derived from analysis of MIR 936 937 // The compiler temporary for the code address of the method. 938 CompilerTemp *base_of_code_; 939 940 // Have we decided to compute a ptr to code and store in temporary VR? 941 bool store_method_addr_; 942 943 // Have we used the stored method address? 944 bool store_method_addr_used_; 945 946 // Instructions to remove if we didn't use the stored method address. 947 LIR* setup_method_address_[2]; 948 949 // Instructions needing patching with Method* values. 950 ArenaVector<LIR*> method_address_insns_; 951 952 // Instructions needing patching with Class Type* values. 953 ArenaVector<LIR*> class_type_address_insns_; 954 955 // Instructions needing patching with PC relative code addresses. 956 ArenaVector<LIR*> call_method_insns_; 957 958 // Prologue decrement of stack pointer. 959 LIR* stack_decrement_; 960 961 // Epilogue increment of stack pointer. 962 LIR* stack_increment_; 963 964 // The list of const vector literals. 965 LIR* const_vectors_; 966 967 /* 968 * @brief Search for a matching vector literal 969 * @param constants An array of size 4 which contains all of 32-bit constants. 970 * @returns pointer to matching LIR constant, or nullptr if not found. 971 */ 972 LIR* ScanVectorLiteral(int32_t* constants); 973 974 /* 975 * @brief Add a constant vector literal 976 * @param constants An array of size 4 which contains all of 32-bit constants. 977 */ 978 LIR* AddVectorLiteral(int32_t* constants); 979 980 InToRegStorageMapping in_to_reg_storage_mapping_; 981 982 bool WideGPRsAreAliases() OVERRIDE { 983 return cu_->target64; // On 64b, we have 64b GPRs. 984 } 985 bool WideFPRsAreAliases() OVERRIDE { 986 return true; // xmm registers have 64b views even on x86. 987 } 988 989 /* 990 * @brief Dump a RegLocation using printf 991 * @param loc Register location to dump 992 */ 993 static void DumpRegLocation(RegLocation loc); 994 995 static const X86EncodingMap EncodingMap[kX86Last]; 996 997 private: 998 void SwapBits(RegStorage result_reg, int shift, int32_t value); 999 void SwapBits64(RegStorage result_reg, int shift, int64_t value); 1000}; 1001 1002} // namespace art 1003 1004#endif // ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ 1005