ih264e_api.c revision b0aadd0c45cb959d102cbe39ab870e4e3292ce97
1/****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19*/ 20 21/** 22******************************************************************************* 23* @file 24* ih264e_api.c 25* 26* @brief 27* Contains api function definitions for H264 encoder 28* 29* @author 30* ittiam 31* 32* @par List of Functions: 33* - api_check_struct_sanity() 34* - ih264e_codec_update_config() 35* - ih264e_set_default_params() 36* - ih264e_init() 37* - ih264e_get_num_rec() 38* - ih264e_fill_num_mem_rec() 39* - ih264e_init_mem_rec() 40* - ih264e_retrieve_memrec() 41* - ih264e_set_flush_mode() 42* - ih264e_get_buf_info() 43* - ih264e_set_dimensions() 44* - ih264e_set_frame_rate() 45* - ih264e_set_bit_rate() 46* - ih264e_set_frame_type() 47* - ih264e_set_qp() 48* - ih264e_set_enc_mode() 49* - ih264e_set_vbv_params() 50* - ih264_set_air_params() 51* - ih264_set_me_params() 52* - ih264_set_ipe_params() 53* - ih264_set_gop_params() 54* - ih264_set_profile_params() 55* - ih264_set_deblock_params() 56* - ih264e_set_num_cores() 57* - ih264e_reset() 58* - ih264e_ctl() 59* - ih264e_api_function() 60* 61* @remarks 62* None 63* 64******************************************************************************* 65*/ 66 67/*****************************************************************************/ 68/* File Includes */ 69/*****************************************************************************/ 70 71/* System Include Files */ 72#include <stdio.h> 73#include <stddef.h> 74#include <stdlib.h> 75#include <string.h> 76#include <assert.h> 77 78/* User Include Files */ 79#include "ih264e_config.h" 80#include "ih264_typedefs.h" 81#include "ih264_size_defs.h" 82#include "iv2.h" 83#include "ive2.h" 84#include "ih264e.h" 85#include "ithread.h" 86#include "ih264_debug.h" 87#include "ih264_defs.h" 88#include "ih264_error.h" 89#include "ih264_structs.h" 90#include "ih264_trans_quant_itrans_iquant.h" 91#include "ih264_inter_pred_filters.h" 92#include "ih264_mem_fns.h" 93#include "ih264_padding.h" 94#include "ih264_intra_pred_filters.h" 95#include "ih264_deblk_edge_filters.h" 96#include "ih264_cabac_tables.h" 97#include "ih264_macros.h" 98#include "ih264e_defs.h" 99#include "ih264e_globals.h" 100#include "ih264_buf_mgr.h" 101#include "irc_mem_req_and_acq.h" 102#include "irc_cntrl_param.h" 103#include "irc_frame_info_collector.h" 104#include "irc_rate_control_api.h" 105#include "ih264e_time_stamp.h" 106#include "ih264e_modify_frm_rate.h" 107#include "ih264e_rate_control.h" 108#include "ih264e_error.h" 109#include "ih264e_bitstream.h" 110#include "ime_defs.h" 111#include "ime_distortion_metrics.h" 112#include "ime_structs.h" 113#include "ih264e_cabac_structs.h" 114#include "ih264e_structs.h" 115#include "ih264e_utils.h" 116#include "ih264e_core_coding.h" 117#include "ih264_platform_macros.h" 118#include "ih264e_platform_macros.h" 119#include "ih264_list.h" 120#include "ih264_dpb_mgr.h" 121#include "ih264_cavlc_tables.h" 122#include "ih264e_cavlc.h" 123#include "ih264_common_tables.h" 124#include "ih264e_master.h" 125#include "ih264e_fmt_conv.h" 126#include "ih264e_version.h" 127 128 129/*****************************************************************************/ 130/* Function Declarations */ 131/*****************************************************************************/ 132WORD32 ih264e_get_rate_control_mem_tab(void *pv_rate_control, 133 iv_mem_rec_t *ps_mem, 134 ITT_FUNC_TYPE_E e_func_type); 135 136 137/*****************************************************************************/ 138/* Function Definitions */ 139/*****************************************************************************/ 140 141/** 142******************************************************************************* 143* 144* @brief 145* Used to test arguments for corresponding API call 146* 147* @par Description: 148* For each command the arguments are validated 149* 150* @param[in] ps_handle 151* Codec handle at API level 152* 153* @param[in] pv_api_ip 154* Pointer to input structure 155* 156* @param[out] pv_api_op 157* Pointer to output structure 158* 159* @returns error status 160* 161* @remarks none 162* 163******************************************************************************* 164*/ 165static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 166 void *pv_api_ip, 167 void *pv_api_op) 168{ 169 /* api call */ 170 WORD32 command = IV_CMD_NA; 171 172 /* input structure expected by the api call */ 173 UWORD32 *pu4_api_ip = pv_api_ip; 174 175 /* output structure expected by the api call */ 176 UWORD32 *pu4_api_op = pv_api_op; 177 178 /* temp var */ 179 WORD32 i, j; 180 181 if (NULL == pv_api_op || NULL == pv_api_ip) 182 { 183 return (IV_FAIL); 184 } 185 186 /* get command */ 187 command = pu4_api_ip[1]; 188 189 /* set error code */ 190 pu4_api_op[1] = 0; 191 192 /* error checks on handle */ 193 switch (command) 194 { 195 case IV_CMD_GET_NUM_MEM_REC: 196 case IV_CMD_FILL_NUM_MEM_REC: 197 break; 198 199 case IV_CMD_INIT: 200 if (ps_handle == NULL) 201 { 202 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 203 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL; 204 return IV_FAIL; 205 } 206 207 if (ps_handle->u4_size != sizeof(iv_obj_t)) 208 { 209 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 210 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT; 211 return IV_FAIL; 212 } 213 break; 214 215 case IVE_CMD_QUEUE_INPUT: 216 case IVE_CMD_QUEUE_OUTPUT: 217 case IVE_CMD_DEQUEUE_OUTPUT: 218 case IVE_CMD_GET_RECON: 219 case IV_CMD_RETRIEVE_MEMREC: 220 case IVE_CMD_VIDEO_CTL: 221 case IVE_CMD_VIDEO_ENCODE: 222 223 if (ps_handle == NULL) 224 { 225 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 226 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL; 227 return IV_FAIL; 228 } 229 230 if (ps_handle->u4_size != sizeof(iv_obj_t)) 231 { 232 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 233 *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT; 234 return IV_FAIL; 235 } 236 237 if (ps_handle->pv_fxns != ih264e_api_function) 238 { 239 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 240 *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL; 241 return IV_FAIL; 242 } 243 244 if (ps_handle->pv_codec_handle == NULL) 245 { 246 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 247 *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE; 248 return IV_FAIL; 249 } 250 break; 251 252 default: 253 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 254 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD; 255 return IV_FAIL; 256 } 257 258 /* error checks on input output structures */ 259 switch (command) 260 { 261 case IV_CMD_GET_NUM_MEM_REC: 262 { 263 ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip; 264 ih264e_num_mem_rec_op_t *ps_op = pv_api_op; 265 266 ps_op->s_ive_op.u4_error_code = 0; 267 268 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t)) 269 { 270 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 271 ps_op->s_ive_op.u4_error_code |= 272 IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT; 273 return (IV_FAIL); 274 } 275 276 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t)) 277 { 278 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 279 ps_op->s_ive_op.u4_error_code |= 280 IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT; 281 return (IV_FAIL); 282 } 283 break; 284 } 285 286 case IV_CMD_FILL_NUM_MEM_REC: 287 { 288 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip; 289 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op; 290 291 iv_mem_rec_t *ps_mem_rec = NULL; 292 293 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); 294 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); 295 296 ps_op->s_ive_op.u4_error_code = 0; 297 298 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t)) 299 { 300 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 301 ps_op->s_ive_op.u4_error_code |= 302 IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT; 303 return (IV_FAIL); 304 } 305 306 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t)) 307 { 308 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 309 ps_op->s_ive_op.u4_error_code |= 310 IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT; 311 return (IV_FAIL); 312 } 313 314 if (max_wd < MIN_WD || max_wd > MAX_WD) 315 { 316 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 317 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED; 318 return (IV_FAIL); 319 } 320 321 if (max_ht < MIN_HT || max_ht > MAX_HT) 322 { 323 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 324 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED; 325 return (IV_FAIL); 326 } 327 328 /* verify number of mem rec ptr */ 329 if (NULL == ps_ip->s_ive_ip.ps_mem_rec) 330 { 331 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 332 ps_op->s_ive_op.u4_error_code |= 333 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL; 334 return (IV_FAIL); 335 } 336 337 /* verify number of mem records */ 338 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT) 339 { 340 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 341 ps_op->s_ive_op.u4_error_code |= 342 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT; 343 return IV_FAIL; 344 } 345 346 /* check mem records sizes are correct */ 347 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec; 348 for (i = 0; i < MEM_REC_CNT; i++) 349 { 350 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 351 { 352 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 353 ps_op->s_ive_op.u4_error_code |= 354 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT; 355 return IV_FAIL; 356 } 357 } 358 break; 359 } 360 361 case IV_CMD_INIT: 362 { 363 ih264e_init_ip_t *ps_ip = pv_api_ip; 364 ih264e_init_op_t *ps_op = pv_api_op; 365 366 iv_mem_rec_t *ps_mem_rec = NULL; 367 368 WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); 369 WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); 370 371 ps_op->s_ive_op.u4_error_code = 0; 372 373 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t)) 374 { 375 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 376 ps_op->s_ive_op.u4_error_code |= 377 IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT; 378 return (IV_FAIL); 379 } 380 381 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t)) 382 { 383 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 384 ps_op->s_ive_op.u4_error_code |= 385 IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT; 386 return (IV_FAIL); 387 } 388 389 if (max_wd < MIN_WD || max_wd > MAX_WD) 390 { 391 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 392 ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED; 393 return (IV_FAIL); 394 } 395 396 if (max_ht < MIN_HT || max_ht > MAX_HT) 397 { 398 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 399 ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED; 400 return (IV_FAIL); 401 } 402 403 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT || 404 ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT) 405 { 406 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 407 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED; 408 return (IV_FAIL); 409 } 410 411 if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0) 412 { 413 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 414 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED; 415 return (IV_FAIL); 416 } 417 418 if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10) 419 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B) 420 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11) 421 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12) 422 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13) 423 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20) 424 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21) 425 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22) 426 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30) 427 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31) 428 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32) 429 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40) 430 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41) 431 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42) 432 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50) 433 && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51)) 434 { 435 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 436 ps_op->s_ive_op.u4_error_code |= 437 IH264E_CODEC_LEVEL_NOT_SUPPORTED; 438 return (IV_FAIL); 439 } 440 441 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) 442 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE) 443 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV) 444 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU)) 445 { 446 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 447 ps_op->s_ive_op.u4_error_code |= 448 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED; 449 return (IV_FAIL); 450 } 451 452 if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P) 453 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV) 454 && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU)) 455 { 456 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 457 ps_op->s_ive_op.u4_error_code |= 458 IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED; 459 return (IV_FAIL); 460 } 461 462 if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE) 463 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE) 464 && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY)) 465 { 466 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 467 ps_op->s_ive_op.u4_error_code |= 468 IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED; 469 return (IV_FAIL); 470 } 471 472 if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE) 473 { 474 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 475 ps_op->s_ive_op.u4_error_code |= 476 IH264E_FRAME_RATE_NOT_SUPPORTED; 477 return (IV_FAIL); 478 } 479 480 if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE) 481 { 482 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 483 ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED; 484 return (IV_FAIL); 485 } 486 487 if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES) 488 { 489 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 490 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED; 491 return (IV_FAIL); 492 } 493 494 if (ps_ip->s_ive_ip.u4_num_bframes 495 && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2)) 496 { 497 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 498 ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED; 499 return (IV_FAIL); 500 } 501 502 if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE) 503 { 504 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 505 ps_op->s_ive_op.u4_error_code |= 506 IH264E_CONTENT_TYPE_NOT_SUPPORTED; 507 return (IV_FAIL); 508 } 509 510 if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X) 511 { 512 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 513 ps_op->s_ive_op.u4_error_code |= 514 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED; 515 return (IV_FAIL); 516 } 517 518 if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y) 519 { 520 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 521 ps_op->s_ive_op.u4_error_code |= 522 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED; 523 return (IV_FAIL); 524 } 525 526 if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE) 527 && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS)) 528 { 529 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 530 ps_op->s_ive_op.u4_error_code |= 531 IH264E_SLICE_TYPE_INPUT_INVALID; 532 return (IV_FAIL); 533 } 534 535 if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS) 536 { 537 if (ps_ip->s_ive_ip.u4_slice_param == 0 538 || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4)) 539 { 540 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 541 ps_op->s_ive_op.u4_error_code |= 542 IH264E_SLICE_PARAM_INPUT_INVALID; 543 return (IV_FAIL); 544 } 545 } 546 547 if (NULL == ps_ip->s_ive_ip.ps_mem_rec) 548 { 549 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 550 ps_op->s_ive_op.u4_error_code |= 551 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL; 552 return (IV_FAIL); 553 } 554 555 /* verify number of mem records */ 556 if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT) 557 { 558 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 559 ps_op->s_ive_op.u4_error_code |= 560 IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT; 561 return (IV_FAIL); 562 } 563 564 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec; 565 566 /* check memrecords sizes are correct */ 567 for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++) 568 { 569 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 570 { 571 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 572 ps_op->s_ive_op.u4_error_code |= 573 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT; 574 return IV_FAIL; 575 } 576 577 /* check memrecords pointers are not NULL */ 578 if (ps_mem_rec[i].pv_base == NULL) 579 { 580 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 581 ps_op->s_ive_op.u4_error_code |= 582 IVE_ERR_MEM_REC_BASE_POINTER_NULL; 583 return IV_FAIL; 584 } 585 } 586 587 /* verify memtabs for overlapping regions */ 588 { 589 void *start[MEM_REC_CNT]; 590 void *end[MEM_REC_CNT]; 591 592 start[0] = (ps_mem_rec[0].pv_base); 593 end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base) 594 + ps_mem_rec[0].u4_mem_size - 1; 595 596 for (i = 1; i < MEM_REC_CNT; i++) 597 { 598 /* This array is populated to check memtab overlap */ 599 start[i] = (ps_mem_rec[i].pv_base); 600 end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base) 601 + ps_mem_rec[i].u4_mem_size - 1; 602 603 for (j = 0; j < i; j++) 604 { 605 if ((start[i] >= start[j]) && (start[i] <= end[j])) 606 { 607 ps_op->s_ive_op.u4_error_code |= 1 608 << IVE_UNSUPPORTEDPARAM; 609 ps_op->s_ive_op.u4_error_code |= 610 IVE_ERR_MEM_REC_OVERLAP_ERR; 611 return IV_FAIL; 612 } 613 614 if ((end[i] >= start[j]) && (end[i] <= end[j])) 615 { 616 ps_op->s_ive_op.u4_error_code |= 1 617 << IVE_UNSUPPORTEDPARAM; 618 ps_op->s_ive_op.u4_error_code |= 619 IVE_ERR_MEM_REC_OVERLAP_ERR; 620 return IV_FAIL; 621 } 622 623 if ((start[i] < start[j]) && (end[i] > end[j])) 624 { 625 ps_op->s_ive_op.u4_error_code |= 1 626 << IVE_UNSUPPORTEDPARAM; 627 ps_op->s_ive_op.u4_error_code |= 628 IVE_ERR_MEM_REC_OVERLAP_ERR; 629 return IV_FAIL; 630 } 631 } 632 } 633 } 634 635 /* re-validate mem records with init config */ 636 { 637 /* mem records */ 638 iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT]; 639 640 /* api interface structs */ 641 ih264e_fill_mem_rec_ip_t s_ip; 642 ih264e_fill_mem_rec_op_t s_op; 643 644 /* error status */ 645 IV_STATUS_T e_status; 646 647 /* temp var */ 648 WORD32 i; 649 650 s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t); 651 s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t); 652 653 s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC; 654 s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api; 655 s_ip.s_ive_ip.u4_max_wd = max_wd; 656 s_ip.s_ive_ip.u4_max_ht = max_ht; 657 s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec; 658 s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level; 659 s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt; 660 s_ip.s_ive_ip.u4_max_reorder_cnt = 661 ps_ip->s_ive_ip.u4_max_reorder_cnt; 662 s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt; 663 s_ip.s_ive_ip.u4_max_srch_rng_x = 664 ps_ip->s_ive_ip.u4_max_srch_rng_x; 665 s_ip.s_ive_ip.u4_max_srch_rng_y = 666 ps_ip->s_ive_ip.u4_max_srch_rng_y; 667 668 for (i = 0; i < MEM_REC_CNT; i++) 669 { 670 s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); 671 } 672 673 /* fill mem records */ 674 e_status = ih264e_api_function(NULL, (void *) &s_ip, 675 (void *) &s_op); 676 677 if (IV_FAIL == e_status) 678 { 679 ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code; 680 return (IV_FAIL); 681 } 682 683 /* verify mem records */ 684 for (i = 0; i < MEM_REC_CNT; i++) 685 { 686 if (ps_mem_rec[i].u4_mem_size 687 < s_mem_rec_ittiam_api[i].u4_mem_size) 688 { 689 ps_op->s_ive_op.u4_error_code |= 1 690 << IVE_UNSUPPORTEDPARAM; 691 ps_op->s_ive_op.u4_error_code |= 692 IVE_ERR_MEM_REC_INSUFFICIENT_SIZE; 693 694 return IV_FAIL; 695 } 696 697 if (ps_mem_rec[i].u4_mem_alignment 698 != s_mem_rec_ittiam_api[i].u4_mem_alignment) 699 { 700 ps_op->s_ive_op.u4_error_code |= 1 701 << IVE_UNSUPPORTEDPARAM; 702 ps_op->s_ive_op.u4_error_code |= 703 IVE_ERR_MEM_REC_ALIGNMENT_ERR; 704 705 return IV_FAIL; 706 } 707 708 if (ps_mem_rec[i].e_mem_type 709 != s_mem_rec_ittiam_api[i].e_mem_type) 710 { 711 UWORD32 check = IV_SUCCESS; 712 UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type 713 - ps_mem_rec[i].e_mem_type; 714 715 if ((ps_mem_rec[i].e_mem_type 716 <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) 717 && (s_mem_rec_ittiam_api[i].e_mem_type 718 >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM)) 719 { 720 check = IV_FAIL; 721 } 722 723 if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4)) 724 { 725 /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or 726 * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */ 727 728 if ((diff < 1) || (diff > 3)) 729 { 730 /* Difference between 1 and 3 is okay for all cases other than the 731 * two filtered with the MOD condition above */ 732 check = IV_FAIL; 733 } 734 } 735 else 736 { 737 if (diff == 1) 738 { 739 /* This particular case is when codec asked for External Persistent, 740 * but got Internal Scratch */ 741 check = IV_FAIL; 742 } 743 if ((diff != 2) && (diff != 3)) 744 { 745 check = IV_FAIL; 746 } 747 } 748 749 if (check == IV_FAIL) 750 { 751 ps_op->s_ive_op.u4_error_code |= 1 752 << IVE_UNSUPPORTEDPARAM; 753 ps_op->s_ive_op.u4_error_code |= 754 IVE_ERR_MEM_REC_INCORRECT_TYPE; 755 756 return IV_FAIL; 757 } 758 } 759 } 760 } 761 break; 762 } 763 764 case IVE_CMD_QUEUE_INPUT: 765 case IVE_CMD_QUEUE_OUTPUT: 766 case IVE_CMD_DEQUEUE_OUTPUT: 767 case IVE_CMD_GET_RECON: 768 break; 769 770 case IV_CMD_RETRIEVE_MEMREC: 771 { 772 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip; 773 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op; 774 775 iv_mem_rec_t *ps_mem_rec = NULL; 776 777 ps_op->s_ive_op.u4_error_code = 0; 778 779 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t)) 780 { 781 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 782 ps_op->s_ive_op.u4_error_code |= 783 IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT; 784 return (IV_FAIL); 785 } 786 787 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t)) 788 { 789 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 790 ps_op->s_ive_op.u4_error_code |= 791 IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT; 792 return (IV_FAIL); 793 } 794 795 if (NULL == ps_ip->s_ive_ip.ps_mem_rec) 796 { 797 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 798 ps_op->s_ive_op.u4_error_code |= 799 IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL; 800 return (IV_FAIL); 801 } 802 803 ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec; 804 805 /* check memrecords sizes are correct */ 806 for (i = 0; i < MEM_REC_CNT; i++) 807 { 808 if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) 809 { 810 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 811 ps_op->s_ive_op.u4_error_code |= 812 IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT; 813 return IV_FAIL; 814 } 815 } 816 break; 817 } 818 819 case IVE_CMD_VIDEO_ENCODE: 820 { 821 ih264e_video_encode_ip_t *ps_ip = pv_api_ip; 822 ih264e_video_encode_op_t *ps_op = pv_api_op; 823 824 if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t)) 825 { 826 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 827 ps_op->s_ive_op.u4_error_code |= 828 IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT; 829 return (IV_FAIL); 830 } 831 832 if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t)) 833 { 834 ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; 835 ps_op->s_ive_op.u4_error_code |= 836 IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT; 837 return (IV_FAIL); 838 } 839 break; 840 } 841 842 case IVE_CMD_VIDEO_CTL: 843 { 844 /* ptr to input structure */ 845 WORD32 *pu4_ptr_cmd = pv_api_ip; 846 847 /* sub command */ 848 WORD32 sub_command = pu4_ptr_cmd[2]; 849 850 switch (sub_command) 851 { 852 case IVE_CMD_CTL_SETDEFAULT: 853 { 854 ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip; 855 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op; 856 857 if (ps_ip->s_ive_ip.u4_size 858 != sizeof(ih264e_ctl_setdefault_ip_t)) 859 { 860 ps_op->s_ive_op.u4_error_code |= 1 861 << IVE_UNSUPPORTEDPARAM; 862 ps_op->s_ive_op.u4_error_code |= 863 IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT; 864 return IV_FAIL; 865 } 866 867 if (ps_op->s_ive_op.u4_size 868 != sizeof(ih264e_ctl_setdefault_op_t)) 869 { 870 ps_op->s_ive_op.u4_error_code |= 1 871 << IVE_UNSUPPORTEDPARAM; 872 ps_op->s_ive_op.u4_error_code |= 873 IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT; 874 return IV_FAIL; 875 } 876 break; 877 } 878 879 case IVE_CMD_CTL_GETBUFINFO: 880 { 881 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle); 882 883 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip; 884 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op; 885 886 if (ps_ip->s_ive_ip.u4_size 887 != sizeof(ih264e_ctl_getbufinfo_ip_t)) 888 { 889 ps_op->s_ive_op.u4_error_code |= 1 890 << IVE_UNSUPPORTEDPARAM; 891 ps_op->s_ive_op.u4_error_code |= 892 IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT; 893 return IV_FAIL; 894 } 895 896 if (ps_op->s_ive_op.u4_size 897 != sizeof(ih264e_ctl_getbufinfo_op_t)) 898 { 899 ps_op->s_ive_op.u4_error_code |= 1 900 << IVE_UNSUPPORTEDPARAM; 901 ps_op->s_ive_op.u4_error_code |= 902 IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT; 903 return IV_FAIL; 904 } 905 906 if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD) 907 { 908 ps_op->s_ive_op.u4_error_code |= 1 909 << IVE_UNSUPPORTEDPARAM; 910 ps_op->s_ive_op.u4_error_code |= 911 IH264E_WIDTH_NOT_SUPPORTED; 912 return (IV_FAIL); 913 } 914 915 if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd) 916 { 917 ps_op->s_ive_op.u4_error_code |= 1 918 << IVE_UNSUPPORTEDPARAM; 919 ps_op->s_ive_op.u4_error_code |= 920 IH264E_WIDTH_NOT_SUPPORTED; 921 return (IV_FAIL); 922 } 923 924 if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT) 925 { 926 ps_op->s_ive_op.u4_error_code |= 1 927 << IVE_UNSUPPORTEDPARAM; 928 ps_op->s_ive_op.u4_error_code |= 929 IH264E_HEIGHT_NOT_SUPPORTED; 930 return (IV_FAIL); 931 } 932 933 if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht) 934 { 935 ps_op->s_ive_op.u4_error_code |= 1 936 << IVE_UNSUPPORTEDPARAM; 937 ps_op->s_ive_op.u4_error_code |= 938 IH264E_HEIGHT_NOT_SUPPORTED; 939 return (IV_FAIL); 940 } 941 942 if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) 943 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE) 944 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV) 945 && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU)) 946 { 947 ps_op->s_ive_op.u4_error_code |= 1 948 << IVE_UNSUPPORTEDPARAM; 949 ps_op->s_ive_op.u4_error_code |= 950 IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED; 951 return (IV_FAIL); 952 } 953 break; 954 } 955 956 case IVE_CMD_CTL_GETVERSION: 957 { 958 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip; 959 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op; 960 961 if (ps_ip->s_ive_ip.u4_size 962 != sizeof(ih264e_ctl_getversioninfo_ip_t)) 963 { 964 ps_op->s_ive_op.u4_error_code |= 1 965 << IVE_UNSUPPORTEDPARAM; 966 ps_op->s_ive_op.u4_error_code |= 967 IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT; 968 return IV_FAIL; 969 } 970 971 if (ps_op->s_ive_op.u4_size 972 != sizeof(ih264e_ctl_getversioninfo_op_t)) 973 { 974 ps_op->s_ive_op.u4_error_code |= 1 975 << IVE_UNSUPPORTEDPARAM; 976 ps_op->s_ive_op.u4_error_code |= 977 IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT; 978 return IV_FAIL; 979 } 980 981 if (ps_ip->s_ive_ip.pu1_version == NULL) 982 { 983 ps_op->s_ive_op.u4_error_code |= 1 984 << IVE_UNSUPPORTEDPARAM; 985 ps_op->s_ive_op.u4_error_code |= 986 IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL; 987 return IV_FAIL; 988 } 989 990 break; 991 } 992 993 case IVE_CMD_CTL_FLUSH: 994 { 995 ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip; 996 ih264e_ctl_flush_op_t *ps_op = pv_api_op; 997 998 if (ps_ip->s_ive_ip.u4_size 999 != sizeof(ih264e_ctl_flush_ip_t)) 1000 { 1001 ps_op->s_ive_op.u4_error_code |= 1 1002 << IVE_UNSUPPORTEDPARAM; 1003 ps_op->s_ive_op.u4_error_code |= 1004 IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT; 1005 return IV_FAIL; 1006 } 1007 1008 if (ps_op->s_ive_op.u4_size 1009 != sizeof(ih264e_ctl_flush_op_t)) 1010 { 1011 ps_op->s_ive_op.u4_error_code |= 1 1012 << IVE_UNSUPPORTEDPARAM; 1013 ps_op->s_ive_op.u4_error_code |= 1014 IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT; 1015 return IV_FAIL; 1016 } 1017 1018 break; 1019 } 1020 1021 case IVE_CMD_CTL_RESET: 1022 { 1023 ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip; 1024 ih264e_ctl_reset_op_t *ps_op = pv_api_op; 1025 1026 if (ps_ip->s_ive_ip.u4_size 1027 != sizeof(ih264e_ctl_reset_ip_t)) 1028 { 1029 ps_op->s_ive_op.u4_error_code |= 1 1030 << IVE_UNSUPPORTEDPARAM; 1031 ps_op->s_ive_op.u4_error_code |= 1032 IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT; 1033 return IV_FAIL; 1034 } 1035 1036 if (ps_op->s_ive_op.u4_size 1037 != sizeof(ih264e_ctl_reset_op_t)) 1038 { 1039 ps_op->s_ive_op.u4_error_code |= 1 1040 << IVE_UNSUPPORTEDPARAM; 1041 ps_op->s_ive_op.u4_error_code |= 1042 IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT; 1043 return IV_FAIL; 1044 } 1045 1046 break; 1047 } 1048 1049 case IVE_CMD_CTL_SET_NUM_CORES: 1050 { 1051 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip; 1052 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op; 1053 1054 if (ps_ip->s_ive_ip.u4_size 1055 != sizeof(ih264e_ctl_set_num_cores_ip_t)) 1056 { 1057 ps_op->s_ive_op.u4_error_code |= 1 1058 << IVE_UNSUPPORTEDPARAM; 1059 ps_op->s_ive_op.u4_error_code |= 1060 IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT; 1061 return IV_FAIL; 1062 } 1063 1064 if (ps_op->s_ive_op.u4_size 1065 != sizeof(ih264e_ctl_set_num_cores_op_t)) 1066 { 1067 ps_op->s_ive_op.u4_error_code |= 1 1068 << IVE_UNSUPPORTEDPARAM; 1069 ps_op->s_ive_op.u4_error_code |= 1070 IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT; 1071 return IV_FAIL; 1072 } 1073 1074 if ((ps_ip->s_ive_ip.u4_num_cores < 1) 1075 || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES)) 1076 { 1077 ps_op->s_ive_op.u4_error_code |= 1 1078 << IVE_UNSUPPORTEDPARAM; 1079 ps_op->s_ive_op.u4_error_code |= 1080 IH264E_INVALID_NUM_CORES; 1081 return IV_FAIL; 1082 } 1083 1084 break; 1085 } 1086 1087 case IVE_CMD_CTL_SET_DIMENSIONS: 1088 { 1089 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle); 1090 1091 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip; 1092 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op; 1093 1094 if (ps_ip->s_ive_ip.u4_size 1095 != sizeof(ih264e_ctl_set_dimensions_ip_t)) 1096 { 1097 ps_op->s_ive_op.u4_error_code |= 1 1098 << IVE_UNSUPPORTEDPARAM; 1099 ps_op->s_ive_op.u4_error_code |= 1100 IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT; 1101 return IV_FAIL; 1102 } 1103 1104 if (ps_op->s_ive_op.u4_size 1105 != sizeof(ih264e_ctl_set_dimensions_op_t)) 1106 { 1107 ps_op->s_ive_op.u4_error_code |= 1 1108 << IVE_UNSUPPORTEDPARAM; 1109 ps_op->s_ive_op.u4_error_code |= 1110 IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT; 1111 return IV_FAIL; 1112 } 1113 1114 if (ps_ip->s_ive_ip.u4_wd < MIN_WD) 1115 { 1116 ps_op->s_ive_op.u4_error_code |= 1 1117 << IVE_UNSUPPORTEDPARAM; 1118 ps_op->s_ive_op.u4_error_code |= 1119 IH264E_WIDTH_NOT_SUPPORTED; 1120 return (IV_FAIL); 1121 } 1122 1123 if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd) 1124 { 1125 ps_op->s_ive_op.u4_error_code |= 1 1126 << IVE_UNSUPPORTEDPARAM; 1127 ps_op->s_ive_op.u4_error_code |= 1128 IH264E_WIDTH_NOT_SUPPORTED; 1129 return (IV_FAIL); 1130 } 1131 1132 if (ps_ip->s_ive_ip.u4_ht < MIN_HT) 1133 { 1134 ps_op->s_ive_op.u4_error_code |= 1 1135 << IVE_UNSUPPORTEDPARAM; 1136 ps_op->s_ive_op.u4_error_code |= 1137 IH264E_HEIGHT_NOT_SUPPORTED; 1138 return (IV_FAIL); 1139 } 1140 1141 if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht) 1142 { 1143 ps_op->s_ive_op.u4_error_code |= 1 1144 << IVE_UNSUPPORTEDPARAM; 1145 ps_op->s_ive_op.u4_error_code |= 1146 IH264E_HEIGHT_NOT_SUPPORTED; 1147 return (IV_FAIL); 1148 } 1149 1150 break; 1151 } 1152 1153 case IVE_CMD_CTL_SET_FRAMERATE: 1154 { 1155 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip; 1156 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op; 1157 1158 if (ps_ip->s_ive_ip.u4_size 1159 != sizeof(ih264e_ctl_set_frame_rate_ip_t)) 1160 { 1161 ps_op->s_ive_op.u4_error_code |= 1 1162 << IVE_UNSUPPORTEDPARAM; 1163 ps_op->s_ive_op.u4_error_code |= 1164 IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT; 1165 return IV_FAIL; 1166 } 1167 1168 if (ps_op->s_ive_op.u4_size 1169 != sizeof(ih264e_ctl_set_frame_rate_op_t)) 1170 { 1171 ps_op->s_ive_op.u4_error_code |= 1 1172 << IVE_UNSUPPORTEDPARAM; 1173 ps_op->s_ive_op.u4_error_code |= 1174 IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT; 1175 return IV_FAIL; 1176 } 1177 1178 if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE) 1179 || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)) 1180 { 1181 ps_op->s_ive_op.u4_error_code |= 1 1182 << IVE_UNSUPPORTEDPARAM; 1183 ps_op->s_ive_op.u4_error_code |= 1184 IH264E_FRAME_RATE_NOT_SUPPORTED; 1185 return (IV_FAIL); 1186 } 1187 1188 if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0) 1189 || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0)) 1190 { 1191 ps_op->s_ive_op.u4_error_code |= 1 1192 << IVE_UNSUPPORTEDPARAM; 1193 ps_op->s_ive_op.u4_error_code |= 1194 IH264E_FRAME_RATE_NOT_SUPPORTED; 1195 return (IV_FAIL); 1196 } 1197 1198 if (ps_ip->s_ive_ip.u4_tgt_frame_rate 1199 > ps_ip->s_ive_ip.u4_src_frame_rate) 1200 { 1201 ps_op->s_ive_op.u4_error_code |= 1 1202 << IVE_UNSUPPORTEDPARAM; 1203 ps_op->s_ive_op.u4_error_code |= 1204 IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE; 1205 return (IV_FAIL); 1206 } 1207 1208 break; 1209 } 1210 1211 case IVE_CMD_CTL_SET_BITRATE: 1212 { 1213 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip; 1214 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op; 1215 1216 if (ps_ip->s_ive_ip.u4_size 1217 != sizeof(ih264e_ctl_set_bitrate_ip_t)) 1218 { 1219 ps_op->s_ive_op.u4_error_code |= 1 1220 << IVE_UNSUPPORTEDPARAM; 1221 ps_op->s_ive_op.u4_error_code |= 1222 IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT; 1223 return IV_FAIL; 1224 } 1225 1226 if (ps_op->s_ive_op.u4_size 1227 != sizeof(ih264e_ctl_set_bitrate_op_t)) 1228 { 1229 ps_op->s_ive_op.u4_error_code |= 1 1230 << IVE_UNSUPPORTEDPARAM; 1231 ps_op->s_ive_op.u4_error_code |= 1232 IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT; 1233 return IV_FAIL; 1234 } 1235 1236 if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE) 1237 || (ps_ip->s_ive_ip.u4_target_bitrate == 0)) 1238 { 1239 ps_op->s_ive_op.u4_error_code |= 1 1240 << IVE_UNSUPPORTEDPARAM; 1241 ps_op->s_ive_op.u4_error_code |= 1242 IH264E_BITRATE_NOT_SUPPORTED; 1243 return (IV_FAIL); 1244 } 1245 1246 break; 1247 } 1248 1249 case IVE_CMD_CTL_SET_FRAMETYPE: 1250 { 1251 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip; 1252 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op; 1253 1254 if (ps_ip->s_ive_ip.u4_size 1255 != sizeof(ih264e_ctl_set_frame_type_ip_t)) 1256 { 1257 ps_op->s_ive_op.u4_error_code |= 1 1258 << IVE_UNSUPPORTEDPARAM; 1259 ps_op->s_ive_op.u4_error_code |= 1260 IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT; 1261 return IV_FAIL; 1262 } 1263 1264 if (ps_op->s_ive_op.u4_size 1265 != sizeof(ih264e_ctl_set_frame_type_op_t)) 1266 { 1267 ps_op->s_ive_op.u4_error_code |= 1 1268 << IVE_UNSUPPORTEDPARAM; 1269 ps_op->s_ive_op.u4_error_code |= 1270 IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT; 1271 return IV_FAIL; 1272 } 1273 1274 if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME) 1275 && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME) 1276 && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME) 1277 && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME)) 1278 { 1279 ps_op->s_ive_op.u4_error_code |= 1 1280 << IVE_UNSUPPORTEDPARAM; 1281 ps_op->s_ive_op.u4_error_code |= 1282 IH264E_INVALID_FORCE_FRAME_INPUT; 1283 return IV_FAIL; 1284 } 1285 break; 1286 } 1287 1288 case IVE_CMD_CTL_SET_ME_PARAMS: 1289 { 1290 codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle); 1291 1292 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip; 1293 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op; 1294 1295 if (ps_ip->s_ive_ip.u4_size 1296 != sizeof(ih264e_ctl_set_me_params_ip_t)) 1297 { 1298 ps_op->s_ive_op.u4_error_code |= 1 1299 << IVE_UNSUPPORTEDPARAM; 1300 ps_op->s_ive_op.u4_error_code |= 1301 IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT; 1302 return IV_FAIL; 1303 } 1304 1305 if (ps_op->s_ive_op.u4_size 1306 != sizeof(ih264e_ctl_set_me_params_op_t)) 1307 { 1308 ps_op->s_ive_op.u4_error_code |= 1 1309 << IVE_UNSUPPORTEDPARAM; 1310 ps_op->s_ive_op.u4_error_code |= 1311 IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT; 1312 return IV_FAIL; 1313 } 1314 1315 if ((ps_ip->s_ive_ip.u4_me_speed_preset != FULL_SRCH) 1316 && (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH) 1317 && (ps_ip->s_ive_ip.u4_me_speed_preset != HEX_SRCH)) 1318 { 1319 ps_op->s_ive_op.u4_error_code |= 1 1320 << IVE_UNSUPPORTEDPARAM; 1321 ps_op->s_ive_op.u4_error_code |= 1322 IH264E_INVALID_ME_SPEED_PRESET; 1323 return IV_FAIL; 1324 } 1325 1326 if ((ps_ip->s_ive_ip.u4_enable_hpel != 0) 1327 && (ps_ip->s_ive_ip.u4_enable_hpel != 1)) 1328 { 1329 ps_op->s_ive_op.u4_error_code |= 1 1330 << IVE_UNSUPPORTEDPARAM; 1331 ps_op->s_ive_op.u4_error_code |= 1332 IH264E_INVALID_HALFPEL_OPTION; 1333 return IV_FAIL; 1334 } 1335 1336 if ((ps_ip->s_ive_ip.u4_enable_qpel != 0) 1337 && (ps_ip->s_ive_ip.u4_enable_qpel != 1)) 1338 { 1339 ps_op->s_ive_op.u4_error_code |= 1 1340 << IVE_UNSUPPORTEDPARAM; 1341 ps_op->s_ive_op.u4_error_code |= 1342 IH264E_INVALID_QPEL_OPTION; 1343 return IV_FAIL; 1344 } 1345 1346 if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0) 1347 && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1)) 1348 { 1349 ps_op->s_ive_op.u4_error_code |= 1 1350 << IVE_UNSUPPORTEDPARAM; 1351 ps_op->s_ive_op.u4_error_code |= 1352 IH264E_INVALID_FAST_SAD_OPTION; 1353 return IV_FAIL; 1354 } 1355 1356 if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255) 1357 { 1358 ps_op->s_ive_op.u4_error_code |= 1 1359 << IVE_UNSUPPORTEDPARAM; 1360 ps_op->s_ive_op.u4_error_code |= 1361 IH264E_INVALID_ALT_REF_OPTION; 1362 return IV_FAIL; 1363 } 1364 1365 if (ps_ip->s_ive_ip.u4_srch_rng_x 1366 > ps_codec->s_cfg.u4_max_srch_rng_x) 1367 { 1368 ps_op->s_ive_op.u4_error_code |= 1 1369 << IVE_UNSUPPORTEDPARAM; 1370 ps_op->s_ive_op.u4_error_code |= 1371 IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED; 1372 return (IV_FAIL); 1373 } 1374 1375 if (ps_ip->s_ive_ip.u4_srch_rng_y 1376 > ps_codec->s_cfg.u4_max_srch_rng_y) 1377 { 1378 ps_op->s_ive_op.u4_error_code |= 1 1379 << IVE_UNSUPPORTEDPARAM; 1380 ps_op->s_ive_op.u4_error_code |= 1381 IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED; 1382 return (IV_FAIL); 1383 } 1384 1385 break; 1386 } 1387 1388 case IVE_CMD_CTL_SET_IPE_PARAMS: 1389 { 1390 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip; 1391 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op; 1392 1393 if (ps_ip->s_ive_ip.u4_size 1394 != sizeof(ih264e_ctl_set_ipe_params_ip_t)) 1395 { 1396 ps_op->s_ive_op.u4_error_code |= 1 1397 << IVE_UNSUPPORTEDPARAM; 1398 ps_op->s_ive_op.u4_error_code |= 1399 IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT; 1400 return IV_FAIL; 1401 } 1402 1403 if (ps_op->s_ive_op.u4_size 1404 != sizeof(ih264e_ctl_set_ipe_params_op_t)) 1405 { 1406 ps_op->s_ive_op.u4_error_code |= 1 1407 << IVE_UNSUPPORTEDPARAM; 1408 ps_op->s_ive_op.u4_error_code |= 1409 IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT; 1410 return IV_FAIL; 1411 } 1412 1413 if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0) 1414 && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1)) 1415 { 1416 ps_op->s_ive_op.u4_error_code |= 1 1417 << IVE_UNSUPPORTEDPARAM; 1418 ps_op->s_ive_op.u4_error_code |= 1419 IH264E_INVALID_INTRA4x4_OPTION; 1420 return IV_FAIL; 1421 } 1422 1423 if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG) 1424 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST) 1425 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL) 1426 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST) 1427 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED) 1428 && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST)) 1429 { 1430 ps_op->s_ive_op.u4_error_code |= 1 1431 << IVE_UNSUPPORTEDPARAM; 1432 ps_op->s_ive_op.u4_error_code |= 1433 IH264E_INVALID_ENC_SPEED_PRESET; 1434 return IV_FAIL; 1435 } 1436 1437 break; 1438 } 1439 1440 case IVE_CMD_CTL_SET_GOP_PARAMS: 1441 { 1442 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip; 1443 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op; 1444 1445 if (ps_ip->s_ive_ip.u4_size 1446 != sizeof(ih264e_ctl_set_gop_params_ip_t)) 1447 { 1448 ps_op->s_ive_op.u4_error_code |= 1 1449 << IVE_UNSUPPORTEDPARAM; 1450 ps_op->s_ive_op.u4_error_code |= 1451 IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT; 1452 return IV_FAIL; 1453 } 1454 1455 if (ps_op->s_ive_op.u4_size 1456 != sizeof(ih264e_ctl_set_gop_params_op_t)) 1457 { 1458 ps_op->s_ive_op.u4_error_code |= 1 1459 << IVE_UNSUPPORTEDPARAM; 1460 ps_op->s_ive_op.u4_error_code |= 1461 IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT; 1462 return IV_FAIL; 1463 } 1464 1465 if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) 1466 || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE)) 1467 { 1468 ps_op->s_ive_op.u4_error_code |= 1 1469 << IVE_UNSUPPORTEDPARAM; 1470 ps_op->s_ive_op.u4_error_code |= 1471 IH264E_INVALID_INTRA_FRAME_INTERVAL; 1472 return IV_FAIL; 1473 } 1474 1475 if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) 1476 || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE)) 1477 { 1478 ps_op->s_ive_op.u4_error_code |= 1 1479 << IVE_UNSUPPORTEDPARAM; 1480 ps_op->s_ive_op.u4_error_code |= 1481 IH264E_INVALID_IDR_FRAME_INTERVAL; 1482 return IV_FAIL; 1483 } 1484 1485 break; 1486 } 1487 1488 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS: 1489 { 1490 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip; 1491 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op; 1492 1493 if (ps_ip->s_ive_ip.u4_size 1494 != sizeof(ih264e_ctl_set_deblock_params_ip_t)) 1495 { 1496 ps_op->s_ive_op.u4_error_code |= 1 1497 << IVE_UNSUPPORTEDPARAM; 1498 ps_op->s_ive_op.u4_error_code |= 1499 IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT; 1500 return IV_FAIL; 1501 } 1502 1503 if (ps_op->s_ive_op.u4_size 1504 != sizeof(ih264e_ctl_set_deblock_params_op_t)) 1505 { 1506 ps_op->s_ive_op.u4_error_code |= 1 1507 << IVE_UNSUPPORTEDPARAM; 1508 ps_op->s_ive_op.u4_error_code |= 1509 IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT; 1510 return IV_FAIL; 1511 } 1512 1513 if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0) 1514 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2) 1515 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3) 1516 && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4)) 1517 { 1518 ps_op->s_ive_op.u4_error_code |= 1 1519 << IVE_UNSUPPORTEDPARAM; 1520 ps_op->s_ive_op.u4_error_code |= 1521 IH264E_INVALID_DEBLOCKING_TYPE_INPUT; 1522 return IV_FAIL; 1523 } 1524 1525 break; 1526 } 1527 1528 case IVE_CMD_CTL_SET_QP: 1529 { 1530 ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip; 1531 ih264e_ctl_set_qp_op_t *ps_op = pv_api_op; 1532 1533 if (ps_ip->s_ive_ip.u4_size 1534 != sizeof(ih264e_ctl_set_qp_ip_t)) 1535 { 1536 ps_op->s_ive_op.u4_error_code |= 1 1537 << IVE_UNSUPPORTEDPARAM; 1538 ps_op->s_ive_op.u4_error_code |= 1539 IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT; 1540 return IV_FAIL; 1541 } 1542 1543 if (ps_op->s_ive_op.u4_size 1544 != sizeof(ih264e_ctl_set_qp_op_t)) 1545 { 1546 ps_op->s_ive_op.u4_error_code |= 1 1547 << IVE_UNSUPPORTEDPARAM; 1548 ps_op->s_ive_op.u4_error_code |= 1549 IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT; 1550 return IV_FAIL; 1551 } 1552 1553 if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP) 1554 || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP) 1555 || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP)) 1556 { 1557 ps_op->s_ive_op.u4_error_code |= 1 1558 << IVE_UNSUPPORTEDPARAM; 1559 ps_op->s_ive_op.u4_error_code |= 1560 IH264E_INVALID_MAX_FRAME_QP; 1561 return IV_FAIL; 1562 } 1563 1564 /* We donot support QP < 4 */ 1565 if ((ps_ip->s_ive_ip.u4_i_qp_min < 4) 1566 || (ps_ip->s_ive_ip.u4_p_qp_min < 4) 1567 || (ps_ip->s_ive_ip.u4_b_qp_min < 4) 1568 || (ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max) 1569 || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max) 1570 || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max)) 1571 { 1572 ps_op->s_ive_op.u4_error_code |= 1 1573 << IVE_UNSUPPORTEDPARAM; 1574 ps_op->s_ive_op.u4_error_code |= 1575 IH264E_INVALID_MIN_FRAME_QP; 1576 return IV_FAIL; 1577 } 1578 1579 if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max) 1580 || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max) 1581 || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max)) 1582 { 1583 ps_op->s_ive_op.u4_error_code |= 1 1584 << IVE_UNSUPPORTEDPARAM; 1585 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP; 1586 return IV_FAIL; 1587 } 1588 1589 if ((ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min) 1590 || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min) 1591 || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min)) 1592 { 1593 ps_op->s_ive_op.u4_error_code |= 1 1594 << IVE_UNSUPPORTEDPARAM; 1595 ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP; 1596 return IV_FAIL; 1597 } 1598 1599 break; 1600 } 1601 1602 case IVE_CMD_CTL_SET_ENC_MODE: 1603 { 1604 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip; 1605 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op; 1606 1607 if (ps_ip->s_ive_ip.u4_size 1608 != sizeof(ih264e_ctl_set_enc_mode_ip_t)) 1609 { 1610 ps_op->s_ive_op.u4_error_code |= 1 1611 << IVE_UNSUPPORTEDPARAM; 1612 ps_op->s_ive_op.u4_error_code |= 1613 IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT; 1614 return IV_FAIL; 1615 } 1616 1617 if (ps_op->s_ive_op.u4_size 1618 != sizeof(ih264e_ctl_set_enc_mode_op_t)) 1619 { 1620 ps_op->s_ive_op.u4_error_code |= 1 1621 << IVE_UNSUPPORTEDPARAM; 1622 ps_op->s_ive_op.u4_error_code |= 1623 IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT; 1624 return IV_FAIL; 1625 } 1626 1627 if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER) 1628 && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE)) 1629 { 1630 ps_op->s_ive_op.u4_error_code |= 1 1631 << IVE_UNSUPPORTEDPARAM; 1632 ps_op->s_ive_op.u4_error_code |= 1633 IH264E_INVALID_ENC_OPERATION_MODE; 1634 return IV_FAIL; 1635 } 1636 1637 break; 1638 } 1639 1640 case IVE_CMD_CTL_SET_VBV_PARAMS: 1641 { 1642 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip; 1643 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op; 1644 1645 if (ps_ip->s_ive_ip.u4_size 1646 != sizeof(ih264e_ctl_set_vbv_params_ip_t)) 1647 { 1648 ps_op->s_ive_op.u4_error_code |= 1 1649 << IVE_UNSUPPORTEDPARAM; 1650 ps_op->s_ive_op.u4_error_code |= 1651 IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT; 1652 return IV_FAIL; 1653 } 1654 1655 if (ps_op->s_ive_op.u4_size 1656 != sizeof(ih264e_ctl_set_vbv_params_op_t)) 1657 { 1658 ps_op->s_ive_op.u4_error_code |= 1 1659 << IVE_UNSUPPORTEDPARAM; 1660 ps_op->s_ive_op.u4_error_code |= 1661 IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT; 1662 return IV_FAIL; 1663 } 1664 1665 if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY) 1666 || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY)) 1667 { 1668 ps_op->s_ive_op.u4_error_code |= 1 1669 << IVE_UNSUPPORTEDPARAM; 1670 ps_op->s_ive_op.u4_error_code |= 1671 IH264E_INVALID_BUFFER_DELAY; 1672 return IV_FAIL; 1673 } 1674 1675 break; 1676 } 1677 1678 case IVE_CMD_CTL_SET_AIR_PARAMS: 1679 { 1680 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip; 1681 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op; 1682 1683 if (ps_ip->s_ive_ip.u4_size 1684 != sizeof(ih264e_ctl_set_air_params_ip_t)) 1685 { 1686 ps_op->s_ive_op.u4_error_code |= 1 1687 << IVE_UNSUPPORTEDPARAM; 1688 ps_op->s_ive_op.u4_error_code |= 1689 IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT; 1690 return IV_FAIL; 1691 } 1692 1693 if (ps_op->s_ive_op.u4_size 1694 != sizeof(ih264e_ctl_set_air_params_op_t)) 1695 { 1696 ps_op->s_ive_op.u4_error_code |= 1 1697 << IVE_UNSUPPORTEDPARAM; 1698 ps_op->s_ive_op.u4_error_code |= 1699 IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT; 1700 return IV_FAIL; 1701 } 1702 1703 if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE) 1704 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC) 1705 && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM)) 1706 { 1707 ps_op->s_ive_op.u4_error_code |= 1 1708 << IVE_UNSUPPORTEDPARAM; 1709 ps_op->s_ive_op.u4_error_code |= 1710 IH264E_INVALID_AIR_MODE; 1711 return IV_FAIL; 1712 } 1713 1714 if (ps_ip->s_ive_ip.u4_air_refresh_period == 0) 1715 { 1716 ps_op->s_ive_op.u4_error_code |= 1 1717 << IVE_UNSUPPORTEDPARAM; 1718 ps_op->s_ive_op.u4_error_code |= 1719 IH264E_INVALID_AIR_REFRESH_PERIOD; 1720 return IV_FAIL; 1721 } 1722 1723 break; 1724 } 1725 1726 case IVE_CMD_CTL_SET_PROFILE_PARAMS: 1727 { 1728 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip; 1729 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op; 1730 1731 if (ps_ip->s_ive_ip.u4_size 1732 != sizeof(ih264e_ctl_set_profile_params_ip_t)) 1733 { 1734 ps_op->s_ive_op.u4_error_code |= 1 1735 << IVE_UNSUPPORTEDPARAM; 1736 ps_op->s_ive_op.u4_error_code |= 1737 IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT; 1738 return IV_FAIL; 1739 } 1740 1741 if (ps_op->s_ive_op.u4_size 1742 != sizeof(ih264e_ctl_set_profile_params_op_t)) 1743 { 1744 ps_op->s_ive_op.u4_error_code |= 1 1745 << IVE_UNSUPPORTEDPARAM; 1746 ps_op->s_ive_op.u4_error_code |= 1747 IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT; 1748 return IV_FAIL; 1749 } 1750 1751 if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE && 1752 ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN) 1753 { 1754 ps_op->s_ive_op.u4_error_code |= 1 1755 << IVE_UNSUPPORTEDPARAM; 1756 ps_op->s_ive_op.u4_error_code |= 1757 IH264E_PROFILE_NOT_SUPPORTED; 1758 return IV_FAIL; 1759 } 1760 1761 break; 1762 } 1763 1764 default: 1765 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 1766 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD; 1767 return IV_FAIL; 1768 } 1769 1770 break; 1771 } 1772 1773 default: 1774 *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; 1775 *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD; 1776 return IV_FAIL; 1777 } 1778 1779 return IV_SUCCESS; 1780} 1781 1782/** 1783******************************************************************************* 1784* 1785* @brief update encoder configuration parameters 1786* 1787* @par Description: 1788* updates encoder configuration parameters from the given config set. 1789* Initialize/reinitialize codec parameters according to new configurations. 1790* 1791* @param[in] ps_codec 1792* Pointer to codec context 1793* 1794* @param[in] ps_cfg 1795* Pointer to config param set 1796* 1797* @remarks none 1798* 1799******************************************************************************* 1800*/ 1801IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec, 1802 cfg_params_t *ps_cfg) 1803{ 1804 /* config params */ 1805 cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg; 1806 1807 /* error status */ 1808 IH264E_ERROR_T err = IH264E_SUCCESS; 1809 1810 /* temp var */ 1811 UWORD32 u4_init_rc = 0; 1812 1813 /***********************/ 1814 /* UPDATE CODEC CONFIG */ 1815 /***********************/ 1816 if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS) 1817 { 1818 UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd); 1819 UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht); 1820 1821 if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln 1822 || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd 1823 || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht) 1824 { 1825 ps_curr_cfg->u4_wd = wd_aln; 1826 ps_curr_cfg->u4_ht = ht_aln; 1827 1828 ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd; 1829 ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht; 1830 1831 ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4; 1832 ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4; 1833 1834 ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD; 1835 1836 /* If number of MBs in a frame changes the air map also changes. 1837 * Hence recompute air map also reset air pic cnt */ 1838 if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE) 1839 { 1840 /* re-init the air map */ 1841 ih264e_init_air_map(ps_codec); 1842 1843 /* reset air counter */ 1844 ps_codec->i4_air_pic_cnt = -1; 1845 } 1846 1847 /* initialize mv bank buffer manager */ 1848 err = ih264e_mv_buf_mgr_add_bufs(ps_codec); 1849 if (err != IH264E_SUCCESS) 1850 return err; 1851 1852 /* initialize ref bank buffer manager */ 1853 err = ih264e_pic_buf_mgr_add_bufs(ps_codec); 1854 if (err != IH264E_SUCCESS) 1855 return err; 1856 1857 /* since dimension changed, start new sequence by forcing IDR */ 1858 ps_codec->force_curr_frame_type = IV_IDR_FRAME; 1859 1860 /* in case dimension changes, we need to reinitialize RC as the 1861 * old model shall not fit further */ 1862 u4_init_rc = 1; 1863 1864 /* when the dimension changes, the header needs to be regenerated */ 1865 ps_codec->i4_gen_header = 1; 1866 } 1867 } 1868 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE) 1869 { 1870 /* temp var */ 1871 UWORD32 u4_src_ticks, u4_tgt_ticks; 1872 1873 u4_src_ticks = ih264e_frame_time_get_src_ticks( 1874 ps_codec->s_rate_control.pps_frame_time); 1875 1876 u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks( 1877 ps_codec->s_rate_control.pps_frame_time); 1878 1879 /* Change frame rate */ 1880 if (ps_codec->s_cfg.u4_src_frame_rate 1881 != ps_cfg->u4_src_frame_rate * 1000) 1882 { 1883 ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate 1884 * 1000; 1885 1886 ih264e_frame_time_update_src_frame_rate( 1887 ps_codec->s_rate_control.pps_frame_time, 1888 ps_codec->s_cfg.u4_src_frame_rate); 1889 1890 ih264_time_stamp_update_frame_rate( 1891 ps_codec->s_rate_control.pps_time_stamp, 1892 ps_codec->s_cfg.u4_src_frame_rate); 1893 1894 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api, 1895 ps_codec->s_cfg.u4_src_frame_rate, 1896 u4_src_ticks, u4_tgt_ticks); 1897 } 1898 1899 if (ps_codec->s_cfg.u4_tgt_frame_rate 1900 != ps_cfg->u4_tgt_frame_rate * 1000) 1901 { 1902 ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate 1903 * 1000; 1904 1905 ih264e_frame_time_update_tgt_frame_rate( 1906 ps_codec->s_rate_control.pps_frame_time, 1907 ps_codec->s_cfg.u4_tgt_frame_rate); 1908 1909 irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api, 1910 ps_codec->s_cfg.u4_src_frame_rate, 1911 u4_src_ticks, u4_tgt_ticks); 1912 1913 irc_change_frm_rate_for_bit_alloc( 1914 ps_codec->s_rate_control.pps_rate_control_api, 1915 ps_codec->s_cfg.u4_tgt_frame_rate); 1916 } 1917 1918 } 1919 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE) 1920 { 1921 if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate) 1922 { 1923 if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode) 1924 irc_change_avg_bit_rate( 1925 ps_codec->s_rate_control.pps_rate_control_api, 1926 ps_cfg->u4_target_bitrate); 1927 1928 ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate; 1929 } 1930 } 1931 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE) 1932 { 1933 switch (ps_cfg->e_frame_type) 1934 { 1935 case IV_I_FRAME: 1936 ps_codec->force_curr_frame_type = IV_I_FRAME; 1937 break; 1938 1939 case IV_IDR_FRAME: 1940 ps_codec->force_curr_frame_type = IV_IDR_FRAME; 1941 break; 1942 1943 case IV_P_FRAME: 1944 default: 1945 break; 1946 } 1947 } 1948 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS) 1949 { 1950 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG) 1951 { 1952 ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel; 1953 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad; 1954 ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset; 1955 ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel; 1956 } 1957 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST) 1958 { 1959 ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad; 1960 } 1961 ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x; 1962 ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y; 1963 1964 if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref) 1965 { 1966 ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref; 1967 ps_codec->u4_is_curr_frm_ref = 1; 1968 } 1969 } 1970 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS) 1971 { 1972 ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset; 1973 1974 if (ps_curr_cfg->u4_enc_speed_preset == IVE_SLOWEST) 1975 {/* high quality */ 1976 /* enable diamond search */ 1977 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH; 1978 ps_curr_cfg->u4_enable_fast_sad = 0; 1979 1980 /* disable intra 4x4 */ 1981 ps_curr_cfg->u4_enable_intra_4x4 = 1; 1982 ps_codec->luma_energy_compaction[1] = 1983 ih264e_code_luma_intra_macroblock_4x4_rdopt_on; 1984 1985 /* sub pel off */ 1986 ps_curr_cfg->u4_enable_hpel = 1; 1987 1988 /* deblocking off */ 1989 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0; 1990 1991 /* disabled intra inter gating in Inter slices */ 1992 ps_codec->u4_inter_gate = 0; 1993 } 1994 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_NORMAL) 1995 {/* normal */ 1996 /* enable diamond search */ 1997 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH; 1998 ps_curr_cfg->u4_enable_fast_sad = 0; 1999 2000 /* disable intra 4x4 */ 2001 ps_curr_cfg->u4_enable_intra_4x4 = 1; 2002 2003 /* sub pel off */ 2004 ps_curr_cfg->u4_enable_hpel = 1; 2005 2006 /* deblocking off */ 2007 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0; 2008 2009 /* disabled intra inter gating in Inter slices */ 2010 ps_codec->u4_inter_gate = 0; 2011 } 2012 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FAST) 2013 {/* normal */ 2014 /* enable diamond search */ 2015 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH; 2016 ps_curr_cfg->u4_enable_fast_sad = 0; 2017 2018 /* disable intra 4x4 */ 2019 ps_curr_cfg->u4_enable_intra_4x4 = 0; 2020 2021 /* sub pel off */ 2022 ps_curr_cfg->u4_enable_hpel = 1; 2023 2024 /* deblocking off */ 2025 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_0; 2026 2027 /* disabled intra inter gating in Inter slices */ 2028 ps_codec->u4_inter_gate = 1; 2029 } 2030 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_HIGH_SPEED) 2031 {/* fast */ 2032 /* enable diamond search */ 2033 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH; 2034 ps_curr_cfg->u4_enable_fast_sad = 0; 2035 2036 /* disable intra 4x4 */ 2037 ps_curr_cfg->u4_enable_intra_4x4 = 0; 2038 2039 /* sub pel off */ 2040 ps_curr_cfg->u4_enable_hpel = 0; 2041 2042 /* deblocking off */ 2043 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4; 2044 2045 /* disabled intra inter gating in Inter slices */ 2046 ps_codec->u4_inter_gate = 0; 2047 } 2048 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST) 2049 {/* fastest */ 2050 /* enable diamond search */ 2051 ps_curr_cfg->u4_me_speed_preset = DMND_SRCH; 2052 //u4_num_layers = 4; 2053 2054 /* disable intra 4x4 */ 2055 ps_curr_cfg->u4_enable_intra_4x4 = 0; 2056 2057 /* sub pel off */ 2058 ps_curr_cfg->u4_enable_hpel = 0; 2059 2060 /* deblocking off */ 2061 ps_curr_cfg->u4_disable_deblock_level = DISABLE_DEBLK_LEVEL_4; 2062 2063 /* disabled intra inter gating in Inter slices */ 2064 ps_codec->u4_inter_gate = 1; 2065 } 2066 else if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG) 2067 { 2068 ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4; 2069 } 2070 } 2071 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS) 2072 { 2073 if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval) 2074 { 2075 ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval; 2076 2077 /* reset air counter */ 2078 ps_codec->i4_air_pic_cnt = -1; 2079 2080 /* re-init air map */ 2081 ih264e_init_air_map(ps_codec); 2082 2083 /*Effect intra frame interval change*/ 2084 2085 irc_change_intra_frm_int_call( 2086 ps_codec->s_rate_control.pps_rate_control_api, 2087 ps_curr_cfg->u4_i_frm_interval); 2088 } 2089 2090 ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval; 2091 2092 } 2093 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS) 2094 { 2095 if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG) 2096 { 2097 ps_curr_cfg->u4_disable_deblock_level = 2098 ps_cfg->u4_disable_deblock_level; 2099 } 2100 } 2101 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP) 2102 { 2103 UWORD8 au1_init_qp[MAX_PIC_TYPE]; 2104 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE]; 2105 2106 ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max; 2107 ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min; 2108 ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp; 2109 2110 ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max; 2111 ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min; 2112 ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp; 2113 2114 ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max; 2115 ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min; 2116 ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp; 2117 2118 /* update rc lib with modified qp */ 2119 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp]; 2120 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp]; 2121 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp]; 2122 2123 irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api, 2124 au1_init_qp); 2125 2126 au1_min_max_qp[2 * I_PIC] = 2127 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min]; 2128 au1_min_max_qp[2 * I_PIC + 1] = 2129 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max]; 2130 2131 au1_min_max_qp[2 * P_PIC] = 2132 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min]; 2133 au1_min_max_qp[2 * P_PIC + 1] = 2134 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max]; 2135 2136 au1_min_max_qp[2 * B_PIC] = 2137 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min]; 2138 au1_min_max_qp[2 * B_PIC + 1] = 2139 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max]; 2140 2141 irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api, 2142 au1_min_max_qp); 2143 } 2144 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE) 2145 { 2146 ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode; 2147 2148 if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER) 2149 { 2150 ps_codec->i4_header_mode = 1; 2151 ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE; 2152 } 2153 else 2154 { 2155 ps_codec->i4_header_mode = 0; 2156 } 2157 } 2158 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS 2159 && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode) 2160 { 2161 ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size; 2162 ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay; 2163 2164 // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay); 2165 2166 // TODO: remove this when the support for changing buffer dynamically 2167 // is yet to be added. 2168 u4_init_rc = 1; 2169 } 2170 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS) 2171 { 2172 if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode 2173 || ps_curr_cfg->u4_air_refresh_period 2174 != ps_cfg->u4_air_refresh_period) 2175 { 2176 ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode; 2177 ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period; 2178 2179 ih264e_init_air_map(ps_codec); 2180 2181 /* reset air counter */ 2182 ps_codec->i4_air_pic_cnt = -1; 2183 } 2184 } 2185 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS) 2186 { 2187 ps_codec->s_cfg.e_profile = ps_cfg->e_profile; 2188 ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode; 2189 } 2190 else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES) 2191 { 2192 ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores; 2193 } 2194 2195 /* reset RC model */ 2196 if (u4_init_rc) 2197 { 2198 /* init qp */ 2199 UWORD8 au1_init_qp[MAX_PIC_TYPE]; 2200 2201 /* min max qp */ 2202 UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE]; 2203 2204 /* init i,p,b qp */ 2205 au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp]; 2206 au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp]; 2207 au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp]; 2208 2209 /* init min max qp */ 2210 au1_min_max_qp[2 * I_PIC] = 2211 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min]; 2212 au1_min_max_qp[2 * I_PIC + 1] = 2213 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max]; 2214 2215 au1_min_max_qp[2 * P_PIC] = 2216 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min]; 2217 au1_min_max_qp[2 * P_PIC + 1] = 2218 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max]; 2219 2220 au1_min_max_qp[2 * B_PIC] = 2221 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min]; 2222 au1_min_max_qp[2 * B_PIC + 1] = 2223 gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max]; 2224 2225 /* get rc mode */ 2226 switch (ps_codec->s_cfg.e_rc_mode) 2227 { 2228 case IVE_RC_STORAGE: 2229 ps_codec->s_rate_control.e_rc_type = VBR_STORAGE; 2230 break; 2231 2232 case IVE_RC_CBR_NON_LOW_DELAY: 2233 ps_codec->s_rate_control.e_rc_type = CBR_NLDRC; 2234 break; 2235 2236 case IVE_RC_CBR_LOW_DELAY: 2237 ps_codec->s_rate_control.e_rc_type = CBR_LDRC; 2238 break; 2239 2240 case IVE_RC_NONE: 2241 ps_codec->s_rate_control.e_rc_type = CONST_QP; 2242 break; 2243 2244 default: 2245 break; 2246 } 2247 2248 /* init rate control */ 2249 ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api, 2250 ps_codec->s_rate_control.pps_frame_time, 2251 ps_codec->s_rate_control.pps_time_stamp, 2252 ps_codec->s_rate_control.pps_pd_frm_rate, 2253 ps_codec->s_cfg.u4_max_framerate, 2254 ps_codec->s_cfg.u4_src_frame_rate, 2255 ps_codec->s_cfg.u4_tgt_frame_rate, 2256 ps_codec->s_rate_control.e_rc_type, 2257 ps_codec->s_cfg.u4_target_bitrate, 2258 ps_codec->s_cfg.u4_max_bitrate, 2259 ps_codec->s_cfg.u4_vbv_buffer_delay, 2260 ps_codec->s_cfg.u4_i_frm_interval, 2261 ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp, 2262 ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp, 2263 ps_codec->s_cfg.u4_max_level); 2264 } 2265 2266 return err; 2267} 2268 2269/** 2270******************************************************************************* 2271* 2272* @brief 2273* Sets default encoder config parameters 2274* 2275* @par Description: 2276* Sets default dynamic parameters. Will be called in ih264e_init() to ensure 2277* that even if set_params is not called, codec continues to work 2278* 2279* @param[in] ps_cfg 2280* Pointer to encoder config params 2281* 2282* @returns error status 2283* 2284* @remarks none 2285* 2286******************************************************************************* 2287*/ 2288static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg) 2289{ 2290 WORD32 ret = IV_SUCCESS; 2291 2292 ps_cfg->u4_max_wd = MAX_WD; 2293 ps_cfg->u4_max_ht = MAX_HT; 2294 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT; 2295 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT; 2296 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL; 2297 ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV; 2298 ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE; 2299 ps_cfg->e_recon_color_fmt = IV_YUV_420P; 2300 ps_cfg->u4_enc_speed_preset = IVE_FASTEST; 2301 ps_cfg->e_rc_mode = DEFAULT_RC; 2302 ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE; 2303 ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE; 2304 ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES; 2305 ps_cfg->e_content_type = IV_PROGRESSIVE; 2306 ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X; 2307 ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y; 2308 ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE; 2309 ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM; 2310 ps_cfg->e_arch = ih264e_default_arch(); 2311 ps_cfg->e_soc = SOC_GENERIC; 2312 ps_cfg->u4_disp_wd = MAX_WD; 2313 ps_cfg->u4_disp_ht = MAX_HT; 2314 ps_cfg->u4_wd = MAX_WD; 2315 ps_cfg->u4_ht = MAX_HT; 2316 ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE; 2317 ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE; 2318 ps_cfg->u4_target_bitrate = DEFAULT_BITRATE; 2319 ps_cfg->e_frame_type = IV_NA_FRAME; 2320 ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT; 2321 ps_cfg->u4_i_qp = DEFAULT_I_QP; 2322 ps_cfg->u4_p_qp = DEFAULT_P_QP; 2323 ps_cfg->u4_b_qp = DEFAULT_B_QP; 2324 ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN; 2325 ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX; 2326 ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN; 2327 ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX; 2328 ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN; 2329 ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX; 2330 ps_cfg->e_air_mode = DEFAULT_AIR_MODE; 2331 ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD; 2332 ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY; 2333 ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE; 2334 ps_cfg->u4_num_cores = DEFAULT_NUM_CORES; 2335 ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET; 2336 ps_cfg->u4_enable_hpel = DEFAULT_HPEL; 2337 ps_cfg->u4_enable_qpel = DEFAULT_QPEL; 2338 ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4; 2339 ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8; 2340 ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16; 2341 ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD; 2342 ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD; 2343 ps_cfg->i4_min_sad = 2344 (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ? 2345 DEFAULT_MIN_SAD_ENABLE : 2346 DEFAULT_MIN_SAD_DISABLE; 2347 ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X; 2348 ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y; 2349 ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL; 2350 ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL; 2351 ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL; 2352 ps_cfg->e_profile = DEFAULT_PROFILE; 2353 ps_cfg->u4_timestamp_low = 0; 2354 ps_cfg->u4_timestamp_high = 0; 2355 ps_cfg->u4_is_valid = 1; 2356 ps_cfg->e_cmd = IVE_CMD_CT_NA; 2357 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4; 2358 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4; 2359 ps_cfg->u4_entropy_coding_mode = CAVLC; 2360 ps_cfg->u4_weighted_prediction = 0; 2361 ps_cfg->u4_constrained_intra_pred = 0; 2362 ps_cfg->u4_pic_info_type = 0; 2363 ps_cfg->u4_mb_info_type = 0; 2364 2365 return ret; 2366} 2367 2368/** 2369******************************************************************************* 2370* 2371* @brief 2372* Initialize encoder context. This will be called by init_mem_rec and during 2373* codec reset 2374* 2375* @par Description: 2376* Initializes the context 2377* 2378* @param[in] ps_codec 2379* Codec context pointer 2380* 2381* @returns error status 2382* 2383* @remarks none 2384* 2385******************************************************************************* 2386*/ 2387static WORD32 ih264e_init(codec_t *ps_codec) 2388{ 2389 /* enc config param set */ 2390 cfg_params_t *ps_cfg = &(ps_codec->s_cfg); 2391 2392 /* temp var */ 2393 WORD32 i; 2394 2395 /* coded pic count */ 2396 ps_codec->i4_poc = 0; 2397 2398 /* Number of API calls to encode are made */ 2399 ps_codec->i4_encode_api_call_cnt = -1; 2400 2401 /* Indicates no header has been generated yet */ 2402 ps_codec->u4_header_generated = 0; 2403 2404 /* Number of pictures encoded */ 2405 ps_codec->i4_pic_cnt = -1; 2406 2407 /* Number of threads created */ 2408 ps_codec->i4_proc_thread_cnt = 0; 2409 2410 /* ctl mutex init */ 2411 ithread_mutex_init(ps_codec->pv_ctl_mutex); 2412 2413 /* Set encoder chroma format */ 2414 ps_codec->e_codec_color_format = 2415 (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ? 2416 IV_YUV_420SP_VU : IV_YUV_420SP_UV; 2417 2418 /* Number of continuous frames where deblocking was disabled */ 2419 ps_codec->i4_disable_deblk_pic_cnt = 0; 2420 2421 /* frame num */ 2422 ps_codec->i4_frame_num = 0; 2423 2424 /* set the current frame type to I frame, since we are going to start encoding*/ 2425 ps_codec->force_curr_frame_type = IV_NA_FRAME; 2426 2427 /* idr_pic_id */ 2428 ps_codec->i4_idr_pic_id = -1; 2429 2430 /* Flush mode */ 2431 ps_codec->i4_flush_mode = 0; 2432 2433 /* Encode header mode */ 2434 ps_codec->i4_header_mode = 0; 2435 2436 /* Encode generate header */ 2437 ps_codec->i4_gen_header = 0; 2438 2439 /* To signal successful completion of init */ 2440 ps_codec->i4_init_done = 1; 2441 2442 /* To signal that at least one picture was decoded */ 2443 ps_codec->i4_first_pic_done = 0; 2444 2445 /* Reset Codec */ 2446 ps_codec->i4_reset_flag = 0; 2447 2448 /* Current error code */ 2449 ps_codec->i4_error_code = IH264E_SUCCESS; 2450 2451 /* threshold residue */ 2452 ps_codec->u4_thres_resi = 1; 2453 2454 /* inter gating enable */ 2455 ps_codec->u4_inter_gate = 0; 2456 2457 /* entropy mutex init */ 2458 ithread_mutex_init(ps_codec->pv_entropy_mutex); 2459 2460 /* sps id */ 2461 ps_codec->i4_sps_id = 0; 2462 2463 /* sps id */ 2464 ps_codec->i4_pps_id = 0; 2465 2466 /* Process thread created status */ 2467 memset(ps_codec->ai4_process_thread_created, 0, MAX_PROCESS_THREADS); 2468 2469 /* Number of MBs processed together */ 2470 ps_codec->i4_proc_nmb = 8; 2471 2472 /* Previous POC msb */ 2473 ps_codec->i4_prev_poc_msb = 0; 2474 2475 /* Previous POC lsb */ 2476 ps_codec->i4_prev_poc_lsb = -1; 2477 2478 /* max Previous POC lsb */ 2479 ps_codec->i4_max_prev_poc_lsb = -1; 2480 2481 /* sps, pps status */ 2482 { 2483 sps_t *ps_sps = ps_codec->ps_sps_base; 2484 pps_t *ps_pps = ps_codec->ps_pps_base; 2485 2486 for (i = 0; i < MAX_SPS_CNT; i++) 2487 { 2488 ps_sps->i1_sps_valid = 0; 2489 ps_sps++; 2490 } 2491 2492 for (i = 0; i < MAX_PPS_CNT; i++) 2493 { 2494 ps_pps->i1_pps_valid = 0; 2495 ps_pps++; 2496 } 2497 } 2498 2499 { 2500 WORD32 max_mb_rows = ps_cfg->i4_ht_mbs; 2501 2502 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS; 2503 WORD32 clz; 2504 2505 /* Use next power of two number of entries*/ 2506 clz = CLZ(num_jobs); 2507 num_jobs = 1 << (32 - clz); 2508 2509 /* init process jobq */ 2510 ps_codec->pv_proc_jobq = ih264_list_init( 2511 ps_codec->pv_proc_jobq_buf, 2512 ps_codec->i4_proc_jobq_buf_size, num_jobs, 2513 sizeof(job_t), 10); 2514 RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL); 2515 ih264_list_reset(ps_codec->pv_proc_jobq); 2516 2517 /* init entropy jobq */ 2518 ps_codec->pv_entropy_jobq = ih264_list_init( 2519 ps_codec->pv_entropy_jobq_buf, 2520 ps_codec->i4_entropy_jobq_buf_size, num_jobs, 2521 sizeof(job_t), 10); 2522 RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL); 2523 ih264_list_reset(ps_codec->pv_entropy_jobq); 2524 } 2525 2526 /* Update the jobq context to all the threads */ 2527 for (i = 0; i < MAX_PROCESS_CTXT; i++) 2528 { 2529 ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq; 2530 ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq; 2531 2532 /* i4_id always stays between 0 and MAX_PROCESS_THREADS */ 2533 ps_codec->as_process[i].i4_id = 2534 (i >= MAX_PROCESS_THREADS) ? 2535 (i - MAX_PROCESS_THREADS) : i; 2536 ps_codec->as_process[i].ps_codec = ps_codec; 2537 2538 ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq; 2539 ps_codec->as_process[i].s_entropy.pv_entropy_jobq = 2540 ps_codec->pv_entropy_jobq; 2541 ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1; 2542 } 2543 2544 /* Initialize MV Bank buffer manager */ 2545 ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base); 2546 2547 /* Initialize Picture buffer manager for reference buffers*/ 2548 ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init( 2549 ps_codec->pv_ref_buf_mgr_base); 2550 2551 /* Initialize Picture buffer manager for input buffers*/ 2552 ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init( 2553 ps_codec->pv_inp_buf_mgr_base); 2554 2555 /* Initialize buffer manager for output buffers*/ 2556 ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init( 2557 ps_codec->pv_out_buf_mgr_base); 2558 2559 /* buffer cnt in buffer manager */ 2560 ps_codec->i4_inp_buf_cnt = 0; 2561 ps_codec->i4_out_buf_cnt = 0; 2562 ps_codec->i4_ref_buf_cnt = 0; 2563 2564 ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base; 2565 memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t)); 2566 2567 /* Initialize dpb manager */ 2568 ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr); 2569 2570 memset(ps_codec->as_ref_set, 0, 2571 sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS)); 2572 for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++) 2573 { 2574 ps_codec->as_ref_set[i].i4_pic_cnt = -1; 2575 } 2576 2577 /* fn ptr init */ 2578 ih264e_init_function_ptr(ps_codec); 2579 2580 /* reset status flags */ 2581 for (i = 0; i < MAX_CTXT_SETS; i++) 2582 { 2583 ps_codec->au4_entropy_thread_active[i] = 0; 2584 ps_codec->ai4_pic_cnt[i] = -1; 2585 2586 ps_codec->s_rate_control.pre_encode_skip[i] = 0; 2587 ps_codec->s_rate_control.post_encode_skip[i] = 0; 2588 } 2589 2590 ps_codec->s_rate_control.num_intra_in_prev_frame = 0; 2591 ps_codec->s_rate_control.i4_avg_activity = 0; 2592 2593 return IV_SUCCESS; 2594} 2595 2596/** 2597******************************************************************************* 2598* 2599* @brief 2600* Gets number of memory records required by the codec 2601* 2602* @par Description: 2603* Gets codec memory requirements 2604* 2605* @param[in] pv_api_ip 2606* Pointer to input argument structure 2607* 2608* @param[out] pv_api_op 2609* Pointer to output argument structure 2610* 2611* @returns status 2612* 2613* @remarks 2614* 2615******************************************************************************* 2616*/ 2617static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op) 2618{ 2619 /* api call I/O structures */ 2620 ih264e_num_mem_rec_op_t *ps_op = pv_api_op; 2621 2622 UNUSED(pv_api_ip); 2623 2624 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT; 2625 2626 return IV_SUCCESS; 2627} 2628 2629/** 2630******************************************************************************* 2631* 2632* @brief 2633* Fills memory records of the codec 2634* 2635* @par Description: 2636* Fills codec memory requirements 2637* 2638* @param[in] pv_api_ip 2639* Pointer to input argument structure 2640* 2641* @param[out] pv_api_op 2642* Pointer to output argument structure 2643* 2644* @returns error status 2645* 2646* @remarks none 2647* 2648******************************************************************************* 2649*/ 2650static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op) 2651{ 2652 /* api call I/O structures */ 2653 ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip; 2654 ih264e_fill_mem_rec_op_t *ps_op = pv_api_op; 2655 2656 /* profile / level info */ 2657 WORD32 level; 2658 WORD32 num_reorder_frames; 2659 WORD32 num_ref_frames; 2660 2661 /* mem records */ 2662 WORD32 no_of_mem_rec; 2663 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec; 2664 2665 /* frame dimensions */ 2666 WORD32 max_wd_luma, max_ht_luma; 2667 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt; 2668 2669 /* temp var */ 2670 WORD32 i; 2671 2672 /* error status */ 2673 IV_STATUS_T status = IV_SUCCESS; 2674 2675 num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt; 2676 num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt; 2677 2678 /* mem records */ 2679 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec; 2680 no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec; 2681 2682 /* frame dimensions */ 2683 max_ht_luma = ps_ip->s_ive_ip.u4_max_ht; 2684 max_wd_luma = ps_ip->s_ive_ip.u4_max_wd; 2685 max_ht_luma = ALIGN16(max_ht_luma); 2686 max_wd_luma = ALIGN16(max_wd_luma); 2687 max_mb_rows = max_ht_luma / MB_SIZE; 2688 max_mb_cols = max_wd_luma / MB_SIZE; 2689 max_mb_cnt = max_mb_rows * max_mb_cols; 2690 2691 /* profile / level info */ 2692 level = ih264e_get_min_level(max_ht_luma, max_wd_luma); 2693 2694 /* validate params */ 2695 if ((level < MIN_LEVEL) || (level > MAX_LEVEL)) 2696 { 2697 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED; 2698 level = MAX_LEVEL; 2699 } 2700 2701 if (num_ref_frames > MAX_REF_CNT) 2702 { 2703 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED; 2704 num_ref_frames = MAX_REF_CNT; 2705 } 2706 2707 if (num_reorder_frames > MAX_REF_CNT) 2708 { 2709 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED; 2710 num_reorder_frames = MAX_REF_CNT; 2711 } 2712 2713 /* Set all memory records as persistent and alignment as 128 by default */ 2714 ps_mem_rec = ps_mem_rec_base; 2715 for (i = 0; i < no_of_mem_rec; i++) 2716 { 2717 ps_mem_rec->u4_mem_alignment = 128; 2718 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; 2719 ps_mem_rec++; 2720 } 2721 2722 /************************************************************************ 2723 * Request memory for h264 encoder handle * 2724 ***********************************************************************/ 2725 ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ]; 2726 { 2727 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t); 2728 } 2729 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size); 2730 2731 /************************************************************************ 2732 * Request memory for h264 encoder context * 2733 ***********************************************************************/ 2734 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC]; 2735 { 2736 ps_mem_rec->u4_mem_size = sizeof(codec_t); 2737 } 2738 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size); 2739 2740 /************************************************************************ 2741 * Request memory for CABAC context * 2742 ***********************************************************************/ 2743 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC]; 2744 { 2745 ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t); 2746 } 2747 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size); 2748 2749 /************************************************************************ 2750 * Request memory for CABAC MB info * 2751 ***********************************************************************/ 2752 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO]; 2753 { 2754 ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1) 2755 * sizeof(mb_info_ctxt_t); 2756 } 2757 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size); 2758 2759 2760 /************************************************************************ 2761 * Request memory for entropy context * 2762 * In multi core encoding, each row is assumed to be launched on a * 2763 * thread. The rows below can only start after its neighbors are coded * 2764 * The status of an mb coded/uncoded is signaled via entropy map. * 2765 * 1. One word32 to store skip run cnt * 2766 * 2. mb entropy map (mb status entropy coded/uncoded). The size* 2767 * of the entropy map is max mb cols. Further allocate one * 2768 * more additional row to evade checking for row -1. * 2769 * 3. size of bit stream buffer to store bit stream ctxt. * 2770 * 4. Entropy coding is dependent on nnz coefficient count for * 2771 * the neighbor blocks. It is sufficient to maintain one row * 2772 * worth of nnz as entropy for lower row waits on entropy map* 2773 ************************************************************************/ 2774 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY]; 2775 { 2776 /* total size of the mem record */ 2777 WORD32 total_size = 0; 2778 2779 /* size of skip mb run */ 2780 total_size += sizeof(WORD32); 2781 total_size = ALIGN8(total_size); 2782 2783 /* size in bytes to store entropy status of an entire frame */ 2784 total_size += (max_mb_cols * max_mb_rows); 2785 /* add an additional 1 row of bytes to evade the special case of row 0 */ 2786 total_size += max_mb_cols; 2787 total_size = ALIGN128(total_size); 2788 2789 /* size of bit stream buffer */ 2790 total_size += sizeof(bitstrm_t); 2791 total_size = ALIGN128(total_size); 2792 2793 /* top nnz luma */ 2794 total_size += (max_mb_cols * 4 * sizeof(UWORD8)); 2795 total_size = ALIGN128(total_size); 2796 2797 /* top nnz cbcr */ 2798 total_size += (max_mb_cols * 4 * sizeof(UWORD8)); 2799 total_size = ALIGN128(total_size); 2800 2801 /* total size per each proc ctxt */ 2802 total_size *= MAX_CTXT_SETS; 2803 2804 ps_mem_rec->u4_mem_size = total_size; 2805 } 2806 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size); 2807 2808 /************************************************************************ 2809 * The residue coefficients that needs to be entropy coded are packed * 2810 * at a buffer space by the proc threads. The entropy thread shall * 2811 * read from the buffer space, unpack them and encode the same. The * 2812 * buffer space required to pack a row of mbs are as follows. * 2813 * Assuming transform_8x8_flag is disabled, * 2814 * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed * 2815 * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed * 2816 * by 8 ac 4x4 chroma sub blocks. * 2817 * For the sake of simplicity we assume that all sub blocks are of * 2818 * type 4x4. The packing of each 4x4 is depicted by the structure * 2819 * tu_sblk_coeff_data_t * 2820 ************************************************************************/ 2821 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA]; 2822 { 2823 /* temp var */ 2824 WORD32 size = 0; 2825 2826 /* size of coeff data of 1 mb */ 2827 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS; 2828 2829 /* size of coeff data of 1 row of mb's */ 2830 size *= max_mb_cols; 2831 2832 /* align to avoid any false sharing across threads */ 2833 size = ALIGN64(size); 2834 2835 /* size for one full frame */ 2836 size *= max_mb_rows; 2837 2838 /* size of each proc buffer set (ping, pong) */ 2839 size *= MAX_CTXT_SETS; 2840 2841 ps_mem_rec->u4_mem_size = size; 2842 } 2843 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size); 2844 2845 /************************************************************************ 2846 * while encoding an mb, the mb header data is signaled to the entropy* 2847 * thread by writing to a buffer space. the size of header data per mb * 2848 * is assumed to be 40 bytes * 2849 * TODO: revisit this inference * 2850 ************************************************************************/ 2851 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA]; 2852 { 2853 /* temp var */ 2854 WORD32 size; 2855 2856 /* size per MB */ 2857 size = 40; 2858 2859 /* size for 1 row of mbs */ 2860 size = size * max_mb_cols; 2861 2862 /* align to avoid any false sharing across threads */ 2863 size = ALIGN64(size); 2864 2865 /* size for one full frame */ 2866 size *= max_mb_rows; 2867 2868 /* size of each proc buffer set (ping, pong) */ 2869 size *= MAX_CTXT_SETS; 2870 2871 ps_mem_rec->u4_mem_size = size; 2872 } 2873 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size); 2874 2875 /************************************************************************ 2876 * Size for holding mv_buf_t for each MV Bank. * 2877 * Note this allocation is done for BUF_MGR_MAX_CNT instead of * 2878 * MAX_DPB_SIZE or max_dpb_size for following reasons * 2879 * max_dpb_size will be based on max_wd and max_ht * 2880 * For higher max_wd and max_ht this number will be smaller than * 2881 * MAX_DPB_SIZE But during actual initialization number of buffers * 2882 * allocated can be more. * 2883 * * 2884 * One extra MV Bank is needed to hold current pics MV bank. * 2885 * Since this is only a structure allocation and not actual buffer * 2886 * allocation, it is allocated for BUF_MGR_MAX_CNT entries * 2887 ************************************************************************/ 2888 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK]; 2889 { 2890 /* max luma samples */ 2891 WORD32 max_luma_samples = 0; 2892 2893 /* determine max luma samples */ 2894 for (i = 0; i < 16; i++) 2895 if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc) 2896 max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs 2897 << (BLK_SIZE + BLK_SIZE); 2898 2899 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); 2900 2901 /************************************************************************ 2902 * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank * 2903 * Note: Number of luma samples is not max_wd * max_ht here, instead it * 2904 * is set to maximum number of luma samples allowed at the given level. * 2905 * This is done to ensure that any stream with width and height lesser * 2906 * than max_wd and max_ht is supported. Number of buffers required can * 2907 * be greater for lower width and heights at a given level and this * 2908 * increased number of buffers might require more memory than what * 2909 * max_wd and max_ht buffer would have required Also note one extra * 2910 * buffer is allocated to store current pictures MV bank. * 2911 ***********************************************************************/ 2912 2913 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t); 2914 2915 ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames 2916 + MAX_CTXT_SETS) 2917 * ih264e_get_pic_mv_bank_size(max_luma_samples); 2918 } 2919 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size); 2920 2921 /************************************************************************ 2922 * While encoding inter slices, to compute the cost of encoding an mb * 2923 * with the mv's at hand, we employ the expression cost = sad + lambda * 2924 * x mv_bits. Here mv_bits is the total number of bits taken to represe* 2925 * nt the mv in the stream. The mv bits for all the possible mv are * 2926 * stored in the look up table. The mem record for this look up table * 2927 * is given below. * 2928 ************************************************************************/ 2929 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS]; 2930 { 2931 /* max srch range x */ 2932 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x; 2933 2934 /* max srch range y */ 2935 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y; 2936 2937 /* max srch range */ 2938 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y); 2939 2940 /* due to subpel */ 2941 u4_max_srch_range <<= 2; 2942 2943 /* due to mv on either direction */ 2944 u4_max_srch_range = (u4_max_srch_range << 1); 2945 2946 /* due to pred mv + zero */ 2947 u4_max_srch_range = (u4_max_srch_range << 1) + 1; 2948 2949 u4_max_srch_range = ALIGN128(u4_max_srch_range); 2950 2951 ps_mem_rec->u4_mem_size = u4_max_srch_range; 2952 } 2953 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size); 2954 2955 /************************************************************************ 2956 * Request memory for SPS * 2957 ***********************************************************************/ 2958 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS]; 2959 { 2960 ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t); 2961 } 2962 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size); 2963 2964 /************************************************************************ 2965 * Request memory for PPS * 2966 ***********************************************************************/ 2967 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS]; 2968 { 2969 ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t); 2970 } 2971 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size); 2972 2973 /************************************************************************ 2974 * Request memory for Slice Header * 2975 ***********************************************************************/ 2976 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR]; 2977 { 2978 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT 2979 * sizeof(slice_header_t); 2980 } 2981 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size); 2982 2983 /************************************************************************ 2984 * Request memory for Adaptive Intra Refresh * 2985 ***********************************************************************/ 2986 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP]; 2987 { 2988 /* total size of the mem record */ 2989 WORD32 total_size = 0; 2990 2991 /* intra coded map */ 2992 total_size += max_mb_cnt; 2993 total_size *= MAX_CTXT_SETS; 2994 2995 /* mb refresh map */ 2996 total_size += sizeof(UWORD16) * max_mb_cnt; 2997 2998 /* alignment */ 2999 total_size = ALIGN128(total_size); 3000 3001 ps_mem_rec->u4_mem_size = total_size; 3002 } 3003 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size); 3004 3005 /************************************************************************ 3006 * In multi slice encoding, this memory record helps tracking the start* 3007 * of slice with reference to mb. * 3008 * MEM RECORD for holding * 3009 * 1. mb slice map * 3010 ************************************************************************/ 3011 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP]; 3012 { 3013 /* total size of the mem record */ 3014 WORD32 total_size = 0; 3015 3016 /* size in bytes to slice index of all mbs of a frame */ 3017 total_size = ALIGN64(max_mb_cnt); 3018 3019 /* ih264e_update_proc_ctxt can overread by 1 at the end */ 3020 total_size += 1; 3021 3022 /* total size per each proc ctxt */ 3023 total_size *= MAX_CTXT_SETS; 3024 ps_mem_rec->u4_mem_size = total_size; 3025 } 3026 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size); 3027 3028 /************************************************************************ 3029 * Request memory to hold thread handles for each processing thread * 3030 ************************************************************************/ 3031 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE]; 3032 { 3033 WORD32 handle_size = ithread_get_handle_size(); 3034 3035 ps_mem_rec->u4_mem_size = MAX_PROCESS_THREADS * handle_size; 3036 } 3037 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size); 3038 3039 /************************************************************************ 3040 * Request memory to hold mutex for control calls * 3041 ************************************************************************/ 3042 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX]; 3043 { 3044 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size(); 3045 } 3046 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size); 3047 3048 /************************************************************************ 3049 * Request memory to hold mutex for entropy calls * 3050 ************************************************************************/ 3051 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX]; 3052 { 3053 ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size(); 3054 } 3055 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size); 3056 3057 /************************************************************************ 3058 * Request memory to hold process jobs * 3059 ***********************************************************************/ 3060 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ]; 3061 { 3062 /* One process job per row of MBs */ 3063 /* Allocate for two pictures, so that wrap around can be handled easily */ 3064 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS; 3065 3066 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t)); 3067 3068 ps_mem_rec->u4_mem_size = job_queue_size; 3069 } 3070 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size); 3071 3072 /************************************************************************ 3073 * Request memory to hold entropy jobs * 3074 ***********************************************************************/ 3075 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ]; 3076 { 3077 /* One process job per row of MBs */ 3078 /* Allocate for two pictures, so that wrap around can be handled easily */ 3079 WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS; 3080 3081 WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t)); 3082 3083 ps_mem_rec->u4_mem_size = job_queue_size; 3084 } 3085 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size); 3086 3087 /************************************************************************ 3088 * In multi core encoding, each row is assumed to be launched on a * 3089 * thread. The rows below can only start after its neighbors are coded * 3090 * The status of an mb coded/uncoded is signaled via proc map. * 3091 * MEM RECORD for holding * 3092 * 1. mb proc map (mb status core coded/uncoded) * 3093 ************************************************************************/ 3094 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP]; 3095 { 3096 /* total size of the mem record */ 3097 WORD32 total_size = 0; 3098 3099 /* size in bytes to mb core coding status of an entire frame */ 3100 total_size = max_mb_cnt; 3101 3102 /* add an additional 1 row of bytes to evade the special case of row 0 */ 3103 total_size += max_mb_cols; 3104 3105 /* total size per each proc ctxt */ 3106 total_size *= MAX_CTXT_SETS; 3107 ps_mem_rec->u4_mem_size = total_size; 3108 } 3109 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size); 3110 3111 /************************************************************************ 3112 * mem record for holding a particular MB is deblocked or not * 3113 * 1. mb deblk map (mb status deblocked/not deblocked) * 3114 ************************************************************************/ 3115 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP]; 3116 { 3117 /* total size of the mem record */ 3118 WORD32 total_size = 0; 3119 3120 /* size in bytes to mb core coding status of an entire frame */ 3121 total_size = max_mb_cnt; 3122 3123 /* add an additional 1 row of bytes to evade the special case of row 0 */ 3124 total_size += max_mb_cols; 3125 3126 total_size = ALIGN64(total_size); 3127 3128 /* total size per each proc ctxt */ 3129 total_size *= MAX_CTXT_SETS; 3130 ps_mem_rec->u4_mem_size = total_size; 3131 } 3132 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size); 3133 3134 /************************************************************************ 3135 * mem record for holding a particular MB's me is done or not * 3136 * 1. mb me map * 3137 ************************************************************************/ 3138 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP]; 3139 { 3140 /* total size of the mem record */ 3141 WORD32 total_size = 0; 3142 3143 /* size in bytes to mb core coding status of an entire frame */ 3144 total_size = max_mb_cnt; 3145 3146 /* add an additional 1 row of bytes to evade the special case of row 0 */ 3147 total_size += max_mb_cols; 3148 3149 /* total size per each proc ctxt */ 3150 total_size *= MAX_CTXT_SETS; 3151 3152 ps_mem_rec->u4_mem_size = total_size; 3153 } 3154 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size); 3155 3156 /************************************************************************ 3157 * size for holding dpb manager context * 3158 ************************************************************************/ 3159 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR]; 3160 { 3161 ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t); 3162 } 3163 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size); 3164 3165 /************************************************************************ 3166 * luma or chroma core coding involves mb estimation, error computation* 3167 * between the estimated singnal and the actual signal, transform the * 3168 * error, quantize the error, then inverse transform and inverse quant * 3169 * ize the residue and add the result back to estimated signal. * 3170 * To perform all these, a set of temporary buffers are needed. * 3171 * MEM RECORD for holding scratch buffers * 3172 * 1. prediction buffer used during mb mode analysis * 3173 * 2 temp. reference buffer when intra 4x4 with rdopt on is * 3174 * enabled * 3175 * - when intra 4x4 is enabled, rdopt is on, to store the * 3176 * reconstructed values and use them later this temp. buffer * 3177 * is used. * 3178 * 3. prediction buffer used during intra mode analysis * 3179 * 4. prediction buffer used during intra 16x16 plane mode * 3180 * analysis 3181 * 5. prediction buffer used during intra chroma mode analysis * 3182 * 6. prediction buffer used during intra chroma 16x16 plane * 3183 * mode analysis 3184 * 7. forward transform output buffer * 3185 * - to store the error between estimated and the actual inp * 3186 * ut and to store the fwd transformed quantized output * 3187 * 8. forward transform output buffer * 3188 * - when intra 4x4 is enabled, rdopt is on, to store the * 3189 * fwd transform values and use them later this temp. buffer * 3190 * is used. * 3191 * 9. temporary buffer for inverse transform * 3192 * - temporary buffer used in inverse transform and inverse * 3193 * quantization * 3194 * A. Buffers for holding half_x , half_y and half_xy planes * 3195 ************************************************************************/ 3196 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH]; 3197 { 3198 WORD32 total_size = 0; 3199 WORD32 i4_tmp_size; 3200 3201 /* size to hold prediction buffer */ 3202 total_size += sizeof(UWORD8) * 16 * 16; 3203 total_size = ALIGN64(total_size); 3204 3205 /* size to hold recon for intra 4x4 buffer */ 3206 total_size += sizeof(UWORD8) * 16 * 16; 3207 total_size = ALIGN64(total_size); 3208 3209 /* prediction buffer intra 16x16 */ 3210 total_size += sizeof(UWORD8) * 16 * 16; 3211 total_size = ALIGN64(total_size); 3212 3213 /* prediction buffer intra 16x16 plane*/ 3214 total_size += sizeof(UWORD8) * 16 * 16; 3215 total_size = ALIGN64(total_size); 3216 3217 /* prediction buffer intra chroma*/ 3218 total_size += sizeof(UWORD8) * 16 * 8; 3219 total_size = ALIGN64(total_size); 3220 3221 /* prediction buffer intra chroma plane*/ 3222 total_size += sizeof(UWORD8) * 16 * 8; 3223 total_size = ALIGN64(total_size); 3224 3225 /* size to hold fwd transform output */ 3226 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF; 3227 total_size = ALIGN64(total_size); 3228 3229 /* size to hold fwd transform output */ 3230 total_size += sizeof(WORD16) * SIZE_TRANS_BUFF; 3231 total_size = ALIGN64(total_size); 3232 3233 /* size to hold temporary data during inverse transform */ 3234 total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS; 3235 total_size = ALIGN64(total_size); 3236 3237 /* Buffers for holding half_x , half_y and half_xy planes */ 3238 i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT); 3239 total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT); 3240 3241 /* Allocate for each process thread */ 3242 total_size *= MAX_PROCESS_CTXT; 3243 3244 ps_mem_rec->u4_mem_size = total_size; 3245 } 3246 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size); 3247 3248 /************************************************************************ 3249 * When transform_8x8_flag is disabled, the size of a sub block is * 3250 * 4x4 and when the transform_8x8_flag is enabled the size of the sub * 3251 * block is 8x8. The threshold matrix and the forward scaling list * 3252 * is of the size of the sub block. * 3253 * MEM RECORD for holding * 3254 * 1. quantization parameters for plane y, cb, cr * 3255 * - threshold matrix for quantization * 3256 * - forward weight matrix * 3257 * - satqd threshold matrix * 3258 ************************************************************************/ 3259 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM]; 3260 { 3261 /* total size of the mem record */ 3262 WORD32 total_size = 0; 3263 3264 /* quantization parameter list for planes y,cb and cr */ 3265 total_size += ALIGN64(sizeof(quant_params_t)) * 3; 3266 3267 /* size of threshold matrix for quantization 3268 * (assuming the transform_8x8_flag is disabled). 3269 * for all 3 planes */ 3270 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3; 3271 3272 /* size of forward weight matrix for quantization 3273 * (assuming the transform_8x8_flag is disabled). 3274 * for all 3 planes */ 3275 total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3; 3276 3277 /* Size for SATDQ threshold matrix for palnes y, cb and cr */ 3278 total_size += ALIGN64(sizeof(UWORD16) * 9) * 3; 3279 3280 /* total size per each proc thread */ 3281 total_size *= MAX_PROCESS_CTXT; 3282 3283 ps_mem_rec->u4_mem_size = total_size; 3284 } 3285 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size); 3286 3287 /************************************************************************ 3288 * While computing blocking strength for the current mb, the csbp, mb * 3289 * type for the neighboring mbs are necessary. memtab for storing top * 3290 * row mbtype and csbp is evaluated here. * 3291 * * 3292 * when encoding intra 4x4 or intra 8x8 the submb types are estimated * 3293 * and sent. The estimation is dependent on neighbor mbs. For this * 3294 * store the top row sub mb types for intra mbs * 3295 * * 3296 * During motion vector prediction, the curr mb mv is predicted from * 3297 * neigbors left, top, top right and sometimes top left depending on * 3298 * the availability. The top and top right content is accessed from * 3299 * the memtab specified below. * 3300 ************************************************************************/ 3301 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO]; 3302 { 3303 /* total size of the mem record */ 3304 WORD32 total_size = 0; 3305 3306 /* size in bytes to store 1 row of mb_info_t */ 3307 /* one additional mb, to avoid checking end of row condition */ 3308 total_size += (max_mb_cols + 1) * sizeof(mb_info_t); 3309 3310 /* size in bytes to store 1 row of intra macroblock sub modes */ 3311 total_size += max_mb_cols * sizeof(UWORD8) * 16; 3312 3313 /* size in bytes to store 1 row + 1 of enc_pu_t */ 3314 /* one additional mb, to avoid checking end of row condition */ 3315 total_size += (max_mb_cols + 1) * sizeof(enc_pu_t); 3316 3317 /* total size per proc ctxt */ 3318 total_size = ALIGN128(total_size); 3319 3320 /* total size per each proc ctxt */ 3321 total_size *= MAX_CTXT_SETS; 3322 ps_mem_rec->u4_mem_size = total_size; 3323 } 3324 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size); 3325 3326 /************************************************************************ 3327 * When transform_8x8_flag is disabled, the mb is partitioned into * 3328 * 4 sub blocks. This corresponds to 1 vertical left edge and 1 * 3329 * vertical inner edge, 1 horizontal top edge and 1 horizontal * 3330 * inner edge per mb. Further, When transform_8x8_flag is enabled, * 3331 * the mb is partitioned in to 16 sub blocks. This corresponds to * 3332 * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top * 3333 * edge and 3 horizontal inner edges per mb. * 3334 * MEM RECORD for holding * 3335 * 1. vertical edge blocking strength * 3336 * 2. horizontal edge blocking strength * 3337 * 3. mb qp * 3338 * all are frame level * 3339 ************************************************************************/ 3340 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP]; 3341 { 3342 /* total size of the mem record */ 3343 WORD32 total_size = 0; 3344 3345 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/ 3346 WORD32 vert_bs_size, horz_bs_size, qp_size; 3347 3348 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */ 3349 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0), 3350 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ 3351 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4); 3352 3353 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */ 3354 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0), 3355 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ 3356 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4); 3357 3358 /* qp of each mb requires 1 byte */ 3359 qp_size = ALIGN64(max_mb_cnt); 3360 3361 /* total size */ 3362 total_size = vert_bs_size + horz_bs_size + qp_size; 3363 3364 /* total size per each proc ctxt */ 3365 total_size *= MAX_CTXT_SETS; 3366 3367 ps_mem_rec->u4_mem_size = total_size; 3368 } 3369 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size); 3370 3371 /************************************************************************ 3372 * size for holding dpb manager context * 3373 ************************************************************************/ 3374 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC]; 3375 { 3376 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); 3377 } 3378 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size); 3379 3380 /************************************************************************ 3381 * size for holding dpb manager context * 3382 ************************************************************************/ 3383 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT]; 3384 { 3385 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); 3386 } 3387 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size); 3388 3389 /************************************************************************ 3390 * Size for color space conversion * 3391 ************************************************************************/ 3392 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC]; 3393 { 3394 /* We need a total a memory for a single frame of 420 sp, ie 3395 * (wd * ht) for luma and (wd * ht / 2) for chroma*/ 3396 ps_mem_rec->u4_mem_size = MAX_CTXT_SETS 3397 * ((3 * max_ht_luma * max_wd_luma) >> 1); 3398 /* Allocate an extra row, since inverse transform functions for 3399 * chroma access(only read, not used) few extra bytes due to 3400 * interleaved input 3401 */ 3402 ps_mem_rec->u4_mem_size += max_wd_luma; 3403 } 3404 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size); 3405 3406 /************************************************************************ 3407 * Size for holding pic_buf_t for each reference picture * 3408 * Note this allocation is done for BUF_MGR_MAX_CNT instead of * 3409 * MAX_DPB_SIZE or max_dpb_size for following reasons * 3410 * max_dpb_size will be based on max_wd and max_ht * 3411 * For higher max_wd and max_ht this number will be smaller than * 3412 * MAX_DPB_SIZE But during actual initialization number of buffers * 3413 * allocated can be more. * 3414 * * 3415 * Also to handle display depth application can allocate more than * 3416 * what codec asks for in case of non-shared mode * 3417 * Since this is only a structure allocation and not actual buffer * 3418 * allocation, it is allocated for BUF_MGR_MAX_CNT entries * 3419 ************************************************************************/ 3420 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC]; 3421 { 3422 ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); 3423 ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t); 3424 3425 /************************************************************************ 3426 * Note: Number of luma samples is not max_wd * max_ht here, instead it * 3427 * is set to maximum number of luma samples allowed at the given level. * 3428 * This is done to ensure that any stream with width and height lesser * 3429 * than max_wd and max_ht is supported. Number of buffers required can * 3430 * be greater for lower width and heights at a given level and this * 3431 * increased number of buffers might require more memory than what * 3432 * max_wd and max_ht buffer would have required. Number of buffers is * 3433 * doubled in order to return one frame at a time instead of sending * 3434 * multiple outputs during dpb full case. Also note one extra buffer is * 3435 * allocted to store current picture. * 3436 * * 3437 * Half-pel planes for each reference buffer are allocated along with * 3438 * the reference buffer. So each reference buffer is 4 times the * 3439 * required size. This way buffer management for the half-pel planes is * 3440 * easier and while using the half-pel planes in MC, an offset can be * 3441 * used from a single pointer * 3442 ***********************************************************************/ 3443 ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT 3444 * ih264e_get_total_pic_buf_size( 3445 max_wd_luma * max_ht_luma, level, 3446 PAD_WD, PAD_HT, num_ref_frames, 3447 num_reorder_frames); 3448 } 3449 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size); 3450 3451 /************************************************************************ 3452 * Request memory to hold mem recs to be returned during retrieve call * 3453 ************************************************************************/ 3454 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP]; 3455 { 3456 ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t); 3457 } 3458 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size); 3459 3460 /************************************************************************ 3461 * size for memory required by NMB info structs and buffer for storing * 3462 * half pel plane * 3463 ************************************************************************/ 3464 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB]; 3465 { 3466 ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * max_mb_cols * 3467 (sizeof(mb_info_nmb_t) + MB_SIZE * MB_SIZE 3468 * sizeof(UWORD8)); 3469 } 3470 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size); 3471 3472 /************************************************************************ 3473 * RC mem records * 3474 ************************************************************************/ 3475 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC]; 3476 { 3477 ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB); 3478 } 3479 DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size); 3480 3481 /* Each memtab size is aligned to next multiple of 128 bytes */ 3482 /* This is to ensure all the memtabs start at different cache lines */ 3483 ps_mem_rec = ps_mem_rec_base; 3484 for (i = 0; i < MEM_REC_CNT; i++) 3485 { 3486 ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size); 3487 ps_mem_rec++; 3488 } 3489 3490 ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT; 3491 3492 DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec); 3493 3494 return (status); 3495} 3496 3497/** 3498******************************************************************************* 3499* 3500* @brief 3501* Initializes from mem records passed to the codec 3502* 3503* @par Description: 3504* Initializes pointers based on mem records passed 3505* 3506* @param[in] ps_codec_obj 3507* Pointer to codec object at API level 3508* 3509* @param[in] pv_api_ip 3510* Pointer to input argument structure 3511* 3512* @param[out] pv_api_op 3513* Pointer to output argument structure 3514* 3515* @returns error status 3516* 3517* @remarks none 3518* 3519******************************************************************************* 3520*/ 3521static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj, 3522 void *pv_api_ip, 3523 void *pv_api_op) 3524{ 3525 /* api call I/O structures */ 3526 ih264e_init_ip_t *ps_ip = pv_api_ip; 3527 ih264e_init_op_t *ps_op = pv_api_op; 3528 3529 /* mem records */ 3530 iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec; 3531 3532 /* codec variables */ 3533 codec_t * ps_codec; 3534 cabac_ctxt_t *ps_cabac; 3535 mb_info_ctxt_t *ps_mb_map_ctxt_inc; 3536 3537 cfg_params_t *ps_cfg; 3538 3539 /* frame dimensions */ 3540 WORD32 max_wd_luma, max_ht_luma; 3541 WORD32 max_mb_rows, max_mb_cols, max_mb_cnt; 3542 3543 /* temp var */ 3544 WORD32 i, j; 3545 WORD32 status = IV_SUCCESS; 3546 3547 /* frame dimensions */ 3548 max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); 3549 max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); 3550 max_mb_rows = max_ht_luma / MB_SIZE; 3551 max_mb_cols = max_wd_luma / MB_SIZE; 3552 max_mb_cnt = max_mb_rows * max_mb_cols; 3553 3554 /* mem records */ 3555 ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec; 3556 3557 /* Init mem records */ 3558 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC]; 3559 { 3560 ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base; 3561 ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle); 3562 } 3563 /* Init mem records_cabac ctxt */ 3564 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC]; 3565 { 3566 ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base); 3567 } 3568 3569 /* Init mem records mb info array for CABAC */ 3570 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO]; 3571 { 3572 ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base); 3573 } 3574 3575 /* Note this memset can not be done in init() call, since init will called 3576 during reset as well. And calling this during reset will mean all pointers 3577 need to reinitialized */ 3578 memset(ps_codec, 0, sizeof(codec_t)); 3579 memset(ps_cabac, 0, sizeof(cabac_ctxt_t)); 3580 3581 /* Set default Config Params */ 3582 ps_cfg = &ps_codec->s_cfg; 3583 ih264e_set_default_params(ps_cfg); 3584 3585 /* Update config params as per input */ 3586 ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); 3587 ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); 3588 ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4; 3589 ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4; 3590 ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt; 3591 ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt; 3592 ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level; 3593 ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt; 3594 ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt; 3595 ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate; 3596 ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate; 3597 ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes; 3598 ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type; 3599 ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x; 3600 ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y; 3601 ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode; 3602 ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param; 3603 ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch; 3604 ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc; 3605 ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon; 3606 ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode; 3607 3608 /* Validate params */ 3609 if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL) 3610 || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL)) 3611 { 3612 ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED; 3613 ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL; 3614 } 3615 3616 if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT) 3617 { 3618 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED; 3619 ps_cfg->u4_max_ref_cnt = MAX_REF_CNT; 3620 } 3621 3622 if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT) 3623 { 3624 ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED; 3625 ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT; 3626 } 3627 3628 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP]; 3629 { 3630 ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base; 3631 3632 memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base, 3633 MEM_REC_CNT * sizeof(iv_mem_rec_t)); 3634 } 3635 3636 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY]; 3637 { 3638 /* temp var */ 3639 WORD32 size = 0, offset; 3640 3641 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3642 { 3643 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3644 { 3645 /* base ptr */ 3646 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3647 3648 /* reset size */ 3649 size = 0; 3650 3651 /* skip mb run */ 3652 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = 3653 (void *) (pu1_buf + size); 3654 size += sizeof(WORD32); 3655 size = ALIGN8(size); 3656 3657 /* entropy map */ 3658 ps_codec->as_process[i].s_entropy.pu1_entropy_map = 3659 (void *) (pu1_buf + size + max_mb_cols); 3660 /* size in bytes to store entropy status of an entire frame */ 3661 size += (max_mb_cols * max_mb_rows); 3662 /* add an additional 1 row of bytes to evade the special case of row 0 */ 3663 size += max_mb_cols; 3664 size = ALIGN128(size); 3665 3666 /* bit stream ptr */ 3667 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf 3668 + size); 3669 size += sizeof(bitstrm_t); 3670 size = ALIGN128(size); 3671 3672 /* nnz luma */ 3673 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma = 3674 (void *) (pu1_buf + size); 3675 size += (max_mb_cols * 4 * sizeof(UWORD8)); 3676 size = ALIGN128(size); 3677 3678 /* nnz chroma */ 3679 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = 3680 (void *) (pu1_buf + size); 3681 size += (max_mb_cols * 4 * sizeof(UWORD8)); 3682 size = ALIGN128(size); 3683 offset = size; 3684 /* cabac Context */ 3685 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac; 3686 } 3687 else 3688 { 3689 /* base ptr */ 3690 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3691 3692 /* reset size */ 3693 size = offset; 3694 3695 /* skip mb run */ 3696 ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = 3697 (void *) (pu1_buf + size); 3698 size += sizeof(WORD32); 3699 size = ALIGN8(size); 3700 3701 /* entropy map */ 3702 ps_codec->as_process[i].s_entropy.pu1_entropy_map = 3703 (void *) (pu1_buf + size + max_mb_cols); 3704 /* size in bytes to store entropy status of an entire frame */ 3705 size += (max_mb_cols * max_mb_rows); 3706 /* add an additional 1 row of bytes to evade the special case of row 0 */ 3707 size += max_mb_cols; 3708 size = ALIGN128(size); 3709 3710 /* bit stream ptr */ 3711 ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf 3712 + size); 3713 size += sizeof(bitstrm_t); 3714 size = ALIGN128(size); 3715 3716 /* nnz luma */ 3717 ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma = 3718 (void *) (pu1_buf + size); 3719 size += (max_mb_cols * 4 * sizeof(UWORD8)); 3720 size = ALIGN128(size); 3721 3722 /* nnz chroma */ 3723 ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = 3724 (void *) (pu1_buf + size); 3725 size += (max_mb_cols * 4 * sizeof(UWORD8)); 3726 size = ALIGN128(size); 3727 /* cabac Context */ 3728 ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac; 3729 } 3730 } 3731 ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base = 3732 ps_mb_map_ctxt_inc; 3733 } 3734 3735 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA]; 3736 { 3737 /* temp var */ 3738 WORD32 size = 0, size_of_row; 3739 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3740 3741 /* size of coeff data of 1 mb */ 3742 size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS; 3743 3744 /* size of coeff data of 1 row of mb's */ 3745 size *= max_mb_cols; 3746 3747 /* align to avoid false sharing */ 3748 size = ALIGN64(size); 3749 size_of_row = size; 3750 3751 /* size for one full frame */ 3752 size *= max_mb_rows; 3753 3754 ps_codec->u4_size_coeff_data = size_of_row; 3755 3756 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3757 { 3758 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3759 { 3760 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf; 3761 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = 3762 pu1_buf; 3763 } 3764 else 3765 { 3766 ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size; 3767 ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf 3768 + size; 3769 } 3770 } 3771 } 3772 3773 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA]; 3774 { 3775 /* temp var */ 3776 WORD32 size, size_of_row; 3777 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3778 3779 /* size of header data of 1 mb */ 3780 size = 40; 3781 3782 /* size for 1 row of mbs */ 3783 size = size * max_mb_cols; 3784 3785 /* align to avoid any false sharing across threads */ 3786 size = ALIGN64(size); 3787 size_of_row = size; 3788 3789 /* size for one full frame */ 3790 size *= max_mb_rows; 3791 3792 ps_codec->u4_size_header_data = size_of_row; 3793 3794 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3795 { 3796 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3797 { 3798 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf; 3799 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = 3800 pu1_buf; 3801 } 3802 else 3803 { 3804 ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size; 3805 ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = 3806 pu1_buf + size; 3807 } 3808 } 3809 } 3810 3811 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK]; 3812 { 3813 /* size of buf mgr struct */ 3814 WORD32 size = ih264_buf_mgr_size(); 3815 3816 /* temp var */ 3817 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3818 3819 /* mv buffer mgr */ 3820 ps_codec->pv_mv_buf_mgr_base = pu1_buf; 3821 3822 /* mv bank */ 3823 ps_codec->pv_mv_bank_buf_base = pu1_buf + size; 3824 ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size; 3825 } 3826 3827 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS]; 3828 { 3829 /* max srch range x */ 3830 UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x; 3831 3832 /* max srch range y */ 3833 UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y; 3834 3835 /* max srch range */ 3836 UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y); 3837 3838 /* temp var */ 3839 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3840 3841 /* due to subpel */ 3842 u4_max_srch_range <<= 2; 3843 3844// /* due to mv on either direction */ 3845// u4_max_srch_range = (u4_max_srch_range << 1); 3846 3847 /* due to pred mv + zero */ 3848 u4_max_srch_range = (u4_max_srch_range << 1) + 1; 3849 3850 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3851 { 3852 /* me ctxt */ 3853 me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt); 3854 3855 /* init at zero mv */ 3856 ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range; 3857 } 3858 } 3859 3860 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS]; 3861 { 3862 ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base; 3863 } 3864 3865 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS]; 3866 { 3867 ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base; 3868 } 3869 3870 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR]; 3871 { 3872 ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base; 3873 3874 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3875 { 3876 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3877 { 3878 ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base; 3879 } 3880 else 3881 { 3882 /* temp var */ 3883 WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t); 3884 void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size; 3885 3886 ps_codec->as_process[i].ps_slice_hdr_base = pv_buf; 3887 } 3888 } 3889 } 3890 3891 ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP]; 3892 { 3893 /* temp var */ 3894 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3895 3896 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3897 { 3898 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3899 { 3900 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf; 3901 } 3902 else 3903 { 3904 ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf 3905 + max_mb_cnt; 3906 } 3907 } 3908 3909 ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * 2); 3910 } 3911 3912 ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP]; 3913 { 3914 /* pointer to storage space */ 3915 UWORD8 *pu1_buf_ping, *pu1_buf_pong; 3916 3917 /* init pointer */ 3918 pu1_buf_ping = ps_mem_rec->pv_base; 3919 pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt); 3920 3921 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3922 { 3923 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3924 { 3925 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping; 3926 } 3927 else 3928 { 3929 ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong; 3930 } 3931 } 3932 } 3933 3934 ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE]; 3935 { 3936 WORD32 handle_size = ithread_get_handle_size(); 3937 3938 for (i = 0; i < MAX_PROCESS_THREADS; i++) 3939 { 3940 ps_codec->apv_proc_thread_handle[i] = (UWORD8 *) ps_mem_rec->pv_base 3941 + (i * handle_size); 3942 } 3943 } 3944 3945 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX]; 3946 { 3947 ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base; 3948 } 3949 3950 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX]; 3951 { 3952 ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base; 3953 } 3954 3955 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ]; 3956 { 3957 ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base; 3958 ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size; 3959 } 3960 3961 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ]; 3962 { 3963 ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base; 3964 ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size; 3965 } 3966 3967 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP]; 3968 { 3969 /* pointer to storage space */ 3970 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3971 3972 /* total size of the mem record */ 3973 WORD32 total_size = 0; 3974 3975 /* size in bytes to mb core coding status of an entire frame */ 3976 total_size = max_mb_cnt; 3977 3978 /* add an additional 1 row of bytes to evade the special case of row 0 */ 3979 total_size += max_mb_cols; 3980 3981 for (i = 0; i < MAX_PROCESS_CTXT; i++) 3982 { 3983 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 3984 { 3985 ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols; 3986 } 3987 else 3988 { 3989 ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size 3990 + max_mb_cols; 3991 } 3992 } 3993 } 3994 3995 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP]; 3996 { 3997 /* pointer to storage space */ 3998 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 3999 4000 /* total size of the mem record */ 4001 WORD32 total_size = 0; 4002 4003 /* size in bytes to mb core coding status of an entire frame */ 4004 total_size = max_mb_cnt; 4005 4006 /* add an additional 1 row of bytes to evade the special case of row 0 */ 4007 total_size += max_mb_cols; 4008 4009 /*Align the memory offsets*/ 4010 total_size = ALIGN64(total_size); 4011 4012 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4013 { 4014 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 4015 { 4016 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols; 4017 4018 } 4019 else 4020 { 4021 ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size 4022 + max_mb_cols; 4023 4024 } 4025 } 4026 } 4027 4028 ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP]; 4029 { 4030 /* pointer to storage space */ 4031 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base; 4032 4033 /* total size of the mem record */ 4034 WORD32 total_size = 0; 4035 4036 /* size in bytes to mb core coding status of an entire frame */ 4037 total_size = max_mb_cnt; 4038 4039 /* add an additional 1 row of bytes to evade the special case of row 0 */ 4040 total_size += max_mb_cols; 4041 4042 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4043 { 4044 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 4045 { 4046 ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols; 4047 } 4048 else 4049 { 4050 ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size 4051 + max_mb_cols; 4052 } 4053 } 4054 } 4055 4056 ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR]; 4057 { 4058 ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base; 4059 } 4060 4061 ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH]; 4062 { 4063 /* pointer to storage space */ 4064 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base; 4065 4066 /* size of pred buffer, fwd transform output, temp buffer for inv tra */ 4067 WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp; 4068 4069 /* temp var */ 4070 WORD32 size = 0; 4071 4072 /* size to hold intra/inter prediction buffer */ 4073 size_pred_luma = sizeof(UWORD8) * 16 * 16; 4074 size_pred_chroma = sizeof(UWORD8) * 8 * 16; 4075 4076 /* size to hold fwd transform output */ 4077 size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF; 4078 4079 /* size to hold temporary data during inverse transform */ 4080 size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS; 4081 4082 /* size to hold half pel plane buffers */ 4083 size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT); 4084 4085 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4086 { 4087 /* prediction buffer */ 4088 ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size); 4089 ps_codec->as_process[i].i4_pred_strd = 16; 4090 size += size_pred_luma; 4091 size = ALIGN64(size); 4092 4093 /* prediction buffer */ 4094 ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf 4095 + size); 4096 size += size_pred_luma; 4097 size = ALIGN64(size); 4098 4099 /* prediction buffer intra 16x16 */ 4100 ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf 4101 + size); 4102 size += size_pred_luma; 4103 size = ALIGN64(size); 4104 4105 /* prediction buffer intra 16x16 plane*/ 4106 ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane = 4107 (void *) (pu1_buf + size); 4108 size += size_pred_luma; 4109 size = ALIGN64(size); 4110 4111 /* prediction buffer intra chroma*/ 4112 ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf 4113 + size); 4114 size += size_pred_chroma; 4115 size = ALIGN64(size); 4116 4117 /* prediction buffer intra chroma plane*/ 4118 ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane = 4119 (void *) (pu1_buf + size); 4120 size += size_pred_chroma; 4121 size = ALIGN64(size); 4122 4123 /* Fwd transform output */ 4124 ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size); 4125 ps_codec->as_process[i].i4_res_strd = 16; 4126 size += size_fwd; 4127 size = ALIGN64(size); 4128 4129 /* Fwd transform output */ 4130 ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf 4131 + size); 4132 size += size_fwd; 4133 size = ALIGN64(size); 4134 4135 /* scratch buffer used during inverse transform */ 4136 ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size); 4137 size += size_inv; 4138 size = ALIGN64(size); 4139 4140 for (j = 0; j < SUBPEL_BUFF_CNT; j++) 4141 { 4142 ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size); 4143 size += ALIGN64(size_hp); 4144 } 4145 } 4146 } 4147 4148 ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM]; 4149 { 4150 /* pointer to storage space */ 4151 UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base; 4152 4153 /* size of qp, threshold matrix, fwd scaling list for one plane */ 4154 WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat, 4155 size_satqd_weight_mat; 4156 4157 /* temp var */ 4158 WORD32 total_size = 0; 4159 4160 /* size of quantization parameter list of 1 plane */ 4161 size_quant_param = ALIGN64(sizeof(quant_params_t)); 4162 4163 /* size of threshold matrix for quantization 4164 * (assuming the transform_8x8_flag is disabled). 4165 * for 1 plane */ 4166 size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4); 4167 4168 /* size of forward weight matrix for quantization 4169 * (assuming the transform_8x8_flag is disabled). 4170 * for 1 plane */ 4171 size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4); 4172 4173 /* size of SATQD matrix*/ 4174 size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9); 4175 4176 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4177 { 4178 quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params; 4179 4180 /* quantization param structure */ 4181 ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size); 4182 total_size = total_size + size_quant_param; 4183 ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size); 4184 total_size = total_size + size_quant_param; 4185 ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size); 4186 total_size = total_size + size_quant_param; 4187 4188 /* threshold matrix for quantization */ 4189 ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size); 4190 total_size = total_size + size_thres_mat; 4191 ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size); 4192 total_size = total_size + size_thres_mat; 4193 ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size); 4194 total_size = total_size + size_thres_mat; 4195 4196 /* fwd weight matrix */ 4197 ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size); 4198 total_size = total_size + size_fwd_weight_mat; 4199 ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size); 4200 total_size = total_size + size_fwd_weight_mat; 4201 ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size); 4202 total_size = total_size + size_fwd_weight_mat; 4203 4204 /* threshold matrix for SATQD */ 4205 ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size); 4206 total_size = total_size + size_satqd_weight_mat; 4207 ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size); 4208 total_size = total_size + size_satqd_weight_mat; 4209 ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size); 4210 total_size = total_size + size_satqd_weight_mat; 4211 4212 total_size = ALIGN128(total_size); 4213 } 4214 } 4215 4216 ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO]; 4217 { 4218 /* total size of the mem record */ 4219 WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv; 4220 4221 /* pointer to buffer */ 4222 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 4223 4224 /* size in bytes to store 1 row of mb_info_t */ 4225 /* one additional mb, to avoid checking end of row condition */ 4226 size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t); 4227 4228 /* size in bytes to store 1 row of intra macroblock sub modes */ 4229 size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16; 4230 4231 /* size in bytes to store 1 row + 1 of enc_pu_t */ 4232 /* one additional mb, to avoid checking end of row condition */ 4233 size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t); 4234 4235 /* total size per proc ctxt */ 4236 total_size = size_csbp + size_intra_modes + size_mv; 4237 4238 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4239 { 4240 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 4241 { 4242 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base = 4243 (mb_info_t *) pu1_buf; 4244 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf 4245 + size_csbp; 4246 ps_codec->as_process[i].ps_top_row_pu_base = 4247 (enc_pu_t *) (pu1_buf + size_csbp 4248 + size_intra_modes); 4249 } 4250 else 4251 { 4252 ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base = 4253 (mb_info_t *) (pu1_buf + total_size); 4254 ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf 4255 + total_size + size_csbp; 4256 ps_codec->as_process[i].ps_top_row_pu_base = 4257 (enc_pu_t *) (pu1_buf + total_size + size_csbp 4258 + size_intra_modes); 4259 } 4260 } 4261 } 4262 4263 ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP]; 4264 { 4265 UWORD8 *pu1_buf_ping, *pu1_buf_pong; 4266 4267 /* total size of the mem record */ 4268 WORD32 total_size = 0; 4269 4270 /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/ 4271 WORD32 vert_bs_size, horz_bs_size, qp_size; 4272 4273 /* vertical edge bs = total number of vertical edges * number of bytes per each edge */ 4274 /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0), 4275 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ 4276 vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4); 4277 4278 /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */ 4279 /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0), 4280 * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ 4281 horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4); 4282 4283 /* qp of each mb requires 1 byte */ 4284 qp_size = ALIGN64(max_mb_cnt); 4285 4286 /* total size */ 4287 total_size = vert_bs_size + horz_bs_size + qp_size; 4288 4289 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4290 { 4291 if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) 4292 { 4293 pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base; 4294 4295 /* vertical edge bs storage space */ 4296 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs = 4297 (UWORD32 *) pu1_buf_ping; 4298 pu1_buf_ping += vert_bs_size; 4299 4300 /* horizontal edge bs storage space */ 4301 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs = 4302 (UWORD32 *) pu1_buf_ping; 4303 pu1_buf_ping += horz_bs_size; 4304 4305 /* qp */ 4306 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp = 4307 (UWORD8 *) pu1_buf_ping; 4308 pu1_buf_ping += qp_size; 4309 } 4310 else 4311 { 4312 pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base; 4313 pu1_buf_pong += total_size; 4314 4315 /* vertical edge bs storage space */ 4316 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs = 4317 (UWORD32 *) pu1_buf_pong; 4318 pu1_buf_pong += vert_bs_size; 4319 4320 /* horizontal edge bs storage space */ 4321 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs = 4322 (UWORD32 *) pu1_buf_pong; 4323 pu1_buf_pong += horz_bs_size; 4324 4325 /* qp */ 4326 ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp = 4327 (UWORD8 *) pu1_buf_pong; 4328 pu1_buf_pong += qp_size; 4329 } 4330 } 4331 } 4332 4333 ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC]; 4334 { 4335 ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base; 4336 } 4337 4338 ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT]; 4339 { 4340 ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base; 4341 } 4342 4343 ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC]; 4344 { 4345 ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base; 4346 ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base 4347 + (max_ht_luma * max_wd_luma); 4348 } 4349 4350 ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC]; 4351 { 4352 /* size of buf mgr struct */ 4353 WORD32 size = ih264_buf_mgr_size(); 4354 4355 /* temp var */ 4356 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 4357 4358 /* pic buffer mgr */ 4359 ps_codec->pv_ref_buf_mgr_base = pu1_buf; 4360 4361 /* picture bank */ 4362 ps_codec->pv_pic_buf_base = pu1_buf + size; 4363 ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size; 4364 } 4365 4366 ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB]; 4367 { 4368 /* temp var */ 4369 UWORD8 *pu1_buf = ps_mem_rec->pv_base; 4370 4371 /* size of nmb ctxt */ 4372 WORD32 size = max_mb_cols * sizeof(mb_info_nmb_t); 4373 4374 WORD32 nmb_cntr, subpel_buf_size; 4375 4376 /* init nmb info structure pointer in all proc ctxts */ 4377 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4378 { 4379 ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf); 4380 4381 pu1_buf += size; 4382 } 4383 4384 subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8); 4385 4386 /* adjusting pointers for nmb halfpel buffer */ 4387 for (i = 0; i < MAX_PROCESS_CTXT; i++) 4388 { 4389 mb_info_nmb_t* ps_mb_info_nmb = 4390 &ps_codec->as_process[i].ps_nmb_info[0]; 4391 4392 for (nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++) 4393 { 4394 ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf; 4395 4396 pu1_buf = pu1_buf + subpel_buf_size; 4397 4398 ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE; 4399 } 4400 } 4401 } 4402 4403 ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC]; 4404 { 4405 ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec, 4406 USE_BASE); 4407 } 4408 4409 /* init codec ctxt */ 4410 status = ih264e_init(ps_codec); 4411 4412 return status; 4413} 4414 4415/** 4416******************************************************************************* 4417* 4418* @brief 4419* Retrieves mem records passed to the codec 4420* 4421* @par Description: 4422* Retrieves mem recs passed during init 4423* 4424* @param[in] ps_codec_obj 4425* Pointer to codec object at API level 4426* 4427* @param[in] pv_api_ip 4428* Pointer to input argument structure 4429* 4430* @param[out] pv_api_op 4431* Pointer to output argument structure 4432* 4433* @returns error status 4434* 4435* @remarks none 4436* 4437******************************************************************************* 4438*/ 4439static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj, 4440 void *pv_api_ip, 4441 void *pv_api_op) 4442{ 4443 /* codec ctxt */ 4444 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle; 4445 4446 /* ctrl call I/O structures */ 4447 ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip; 4448 ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op; 4449 4450 if (ps_codec->i4_init_done != 1) 4451 { 4452 ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR; 4453 ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE; 4454 return IV_FAIL; 4455 } 4456 4457 /* join threads upon at end of sequence */ 4458 ih264e_join_threads(ps_codec); 4459 4460 /* collect list of memory records used by the encoder library */ 4461 memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup, 4462 MEM_REC_CNT * (sizeof(iv_mem_rec_t))); 4463 ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT; 4464 4465 /* clean up mutex memory */ 4466 ih264_list_free(ps_codec->pv_entropy_jobq); 4467 ih264_list_free(ps_codec->pv_proc_jobq); 4468 ithread_mutex_destroy(ps_codec->pv_ctl_mutex); 4469 ithread_mutex_destroy(ps_codec->pv_entropy_mutex); 4470 4471 4472 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr); 4473 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr); 4474 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr); 4475 ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr); 4476 4477 return IV_SUCCESS; 4478} 4479 4480/** 4481******************************************************************************* 4482* 4483* @brief 4484* Sets the encoder in flush mode. 4485* 4486* @par Description: 4487* Sets the encoder in flush mode 4488* 4489* @param[in] ps_codec_obj 4490* Pointer to codec object at API level 4491* 4492* @param[in] pv_api_ip 4493* Pointer to input argument structure 4494* 4495* @param[out] pv_api_op 4496* Pointer to output argument structure 4497* 4498* @returns error status 4499* 4500* @remarks This call has no real effect on encoder 4501* 4502******************************************************************************* 4503*/ 4504static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj, 4505 void *pv_api_ip, 4506 void *pv_api_op) 4507{ 4508 /* codec ctxt */ 4509 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle; 4510 4511 /* ctrl call I/O structures */ 4512 ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op; 4513 4514 UNUSED(pv_api_ip); 4515 4516 ps_ctl_op->s_ive_op.u4_error_code = 0; 4517 4518 /* signal flush frame control call */ 4519 ps_codec->i4_flush_mode = 1; 4520 4521 return IV_SUCCESS; 4522} 4523 4524/** 4525******************************************************************************* 4526* 4527* @brief 4528* Gets encoder buffer requirements 4529* 4530* @par Description: 4531* Gets the encoder buffer requirements. Basing on max width and max height 4532* configuration settings, this routine, computes the sizes of necessary input, 4533* output buffers returns this info to callee. 4534* 4535* @param[in] ps_codec_obj 4536* Pointer to codec object at API level 4537* 4538* @param[in] pv_api_ip 4539* Pointer to input argument structure 4540* 4541* @param[out] pv_api_op 4542* Pointer to output argument structure 4543* 4544* @returns error status 4545* 4546* @remarks none 4547* 4548******************************************************************************* 4549*/ 4550static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj, 4551 void *pv_api_ip, 4552 void *pv_api_op) 4553{ 4554 /* ctrl call I/O structures */ 4555 ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip; 4556 ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op; 4557 4558 /* temp var */ 4559 WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); 4560 WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); 4561 WORD32 i; 4562 4563 UNUSED(ps_codec_obj); 4564 4565 ps_op->s_ive_op.u4_error_code = 0; 4566 4567 /* Number of components in input buffers required for codec & 4568 * Minimum sizes of each component in input buffer required */ 4569 if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P) 4570 { 4571 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP; 4572 4573 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht; 4574 ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1); 4575 ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1); 4576 } 4577 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE) 4578 { 4579 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP; 4580 4581 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2; 4582 ps_op->s_ive_op.au4_min_in_buf_size[1] = 4583 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; 4584 } 4585 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565) 4586 { 4587 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP; 4588 4589 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2; 4590 ps_op->s_ive_op.au4_min_in_buf_size[1] = 4591 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; 4592 } 4593 else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888) 4594 { 4595 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP; 4596 4597 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4; 4598 ps_op->s_ive_op.au4_min_in_buf_size[1] = 4599 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; 4600 } 4601 else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV) 4602 || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU)) 4603 { 4604 ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP; 4605 4606 ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht; 4607 ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1); 4608 ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; 4609 } 4610 4611 /* Number of components in output buffers required for codec & 4612 * Minimum sizes of each component in output buffer required */ 4613 ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP; 4614 4615 for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++) 4616 { 4617 ps_op->s_ive_op.au4_min_out_buf_size[i] = MAX(((wd * ht * 3) >> 1), MIN_STREAM_SIZE); 4618 } 4619 4620 ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS; 4621 ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS; 4622 4623 return IV_SUCCESS; 4624} 4625 4626/** 4627******************************************************************************* 4628* 4629* @brief 4630* Sets the picture dimensions 4631* 4632* @par Description: 4633* Sets width, height, display width, display height and strides 4634* 4635* @param[in] pv_api_ip 4636* Pointer to input argument structure 4637* 4638* @param[out] pv_api_op 4639* Pointer to output argument structure 4640* 4641* @param[out] ps_cfg 4642* Pointer to config structure to be updated 4643* 4644* @returns error status 4645* 4646* @remarks none 4647* 4648******************************************************************************* 4649*/ 4650static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip, 4651 void *pv_api_op, 4652 cfg_params_t *ps_cfg) 4653{ 4654 /* ctrl call I/O structures */ 4655 ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip; 4656 ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op; 4657 4658 ps_op->s_ive_op.u4_error_code = 0; 4659 4660 ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd); 4661 ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht); 4662 ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4; 4663 ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4; 4664 ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd; 4665 ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht; 4666 4667 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4668 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4669 4670 return IV_SUCCESS; 4671} 4672 4673/** 4674******************************************************************************* 4675* 4676* @brief 4677* Sets source and target frame rates 4678* 4679* @par Description: 4680* Sets source and target frame rates 4681* 4682* @param[in] pv_api_ip 4683* Pointer to input argument structure 4684* 4685* @param[out] pv_api_op 4686* Pointer to output argument structure 4687* 4688* @param[out] ps_cfg 4689* Pointer to config structure to be updated 4690* 4691* @returns error status 4692* 4693* @remarks none 4694* 4695******************************************************************************* 4696*/ 4697static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip, 4698 void *pv_api_op, 4699 cfg_params_t *ps_cfg) 4700{ 4701 /* ctrl call I/O structures */ 4702 ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip; 4703 ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op; 4704 4705 ps_op->s_ive_op.u4_error_code = 0; 4706 4707 ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate; 4708 ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate; 4709 4710 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4711 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4712 4713 return IV_SUCCESS; 4714} 4715 4716/** 4717******************************************************************************* 4718* 4719* @brief 4720* Sets target bit rate 4721* 4722* @par Description: 4723* Sets target bit rate 4724* 4725* @param[in] pv_api_ip 4726* Pointer to input argument structure 4727* 4728* @param[out] pv_api_op 4729* Pointer to output argument structure 4730* 4731* @param[out] ps_cfg 4732* Pointer to config structure to be updated 4733* 4734* @returns error status 4735* 4736* @remarks none 4737* 4738******************************************************************************* 4739*/ 4740static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip, 4741 void *pv_api_op, 4742 cfg_params_t *ps_cfg) 4743{ 4744 /* ctrl call I/O structures */ 4745 ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip; 4746 ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op; 4747 4748 ps_op->s_ive_op.u4_error_code = 0; 4749 4750 ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate; 4751 4752 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4753 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4754 4755 return IV_SUCCESS; 4756} 4757 4758/** 4759******************************************************************************* 4760* 4761* @brief 4762* Sets frame type 4763* 4764* @par Description: 4765* Sets frame type 4766* 4767* @param[in] pv_api_ip 4768* Pointer to input argument structure 4769* 4770* @param[out] pv_api_op 4771* Pointer to output argument structure 4772* 4773* @param[out] ps_cfg 4774* Pointer to config structure to be updated 4775* 4776* @returns error status 4777* 4778* @remarks not a sticky tag 4779* 4780******************************************************************************* 4781*/ 4782static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip, 4783 void *pv_api_op, 4784 cfg_params_t *ps_cfg) 4785{ 4786 /* ctrl call I/O structures */ 4787 ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip; 4788 ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op; 4789 4790 ps_op->s_ive_op.u4_error_code = 0; 4791 4792 ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type; 4793 4794 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4795 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4796 4797 return IV_SUCCESS; 4798} 4799 4800/** 4801******************************************************************************* 4802* 4803* @brief 4804* Sets quantization params 4805* 4806* @par Description: 4807* Sets the max, min and default qp for I frame, P frame and B frame 4808* 4809* @param[in] pv_api_ip 4810* Pointer to input argument structure 4811* 4812* @param[out] pv_api_op 4813* Pointer to output argument structure 4814* 4815* @param[out] ps_cfg 4816* Pointer to config structure to be updated 4817* 4818* @returns error status 4819* 4820* @remarks none 4821* 4822******************************************************************************* 4823*/ 4824static IV_STATUS_T ih264e_set_qp(void *pv_api_ip, 4825 void *pv_api_op, 4826 cfg_params_t *ps_cfg) 4827{ 4828 /* ctrl call I/O structures */ 4829 ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip; 4830 ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op; 4831 4832 ps_set_qp_op->s_ive_op.u4_error_code = 0; 4833 4834 ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max; 4835 ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min; 4836 ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp; 4837 ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max; 4838 ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min; 4839 ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp; 4840 ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max; 4841 ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min; 4842 ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp; 4843 4844 ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high; 4845 ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low; 4846 4847 return IV_SUCCESS; 4848} 4849 4850/** 4851******************************************************************************* 4852* 4853* @brief 4854* Sets encoding mode 4855* 4856* @par Description: 4857* Sets encoding mode 4858* 4859* @param[in] pv_api_ip 4860* Pointer to input argument structure 4861* 4862* @param[out] pv_api_op 4863* Pointer to output argument structure 4864* 4865* @param[out] ps_cfg 4866* Pointer to config structure to be updated 4867* 4868* @returns error status 4869* 4870* @remarks none 4871* 4872******************************************************************************* 4873*/ 4874static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip, 4875 void *pv_api_op, 4876 cfg_params_t *ps_cfg) 4877{ 4878 /* ctrl call I/O structures */ 4879 ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip; 4880 ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op; 4881 4882 ps_op->s_ive_op.u4_error_code = 0; 4883 4884 ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode; 4885 4886 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4887 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4888 4889 return IV_SUCCESS; 4890} 4891 4892/** 4893******************************************************************************* 4894* 4895* @brief 4896* Sets vbv parameters 4897* 4898* @par Description: 4899* Sets vbv parameters 4900* 4901* @param[in] pv_api_ip 4902* Pointer to input argument structure 4903* 4904* @param[out] pv_api_op 4905* Pointer to output argument structure 4906* 4907* @param[out] ps_cfg 4908* Pointer to config structure to be updated 4909* 4910* @returns error status 4911* 4912* @remarks none 4913* 4914******************************************************************************* 4915*/ 4916static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip, 4917 void *pv_api_op, 4918 cfg_params_t *ps_cfg) 4919{ 4920 /* ctrl call I/O structures */ 4921 ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip; 4922 ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op; 4923 4924 ps_op->s_ive_op.u4_error_code = 0; 4925 4926 ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size; 4927 ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay; 4928 4929 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4930 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4931 4932 return IV_SUCCESS; 4933} 4934 4935/** 4936******************************************************************************* 4937* 4938* @brief 4939* Sets AIR parameters 4940* 4941* @par Description: 4942* Sets AIR parameters 4943* 4944* @param[in] pv_api_ip 4945* Pointer to input argument structure 4946* 4947* @param[out] pv_api_op 4948* Pointer to output argument structure 4949* 4950* @param[out] ps_cfg 4951* Pointer to config structure to be updated 4952* 4953* @returns error status 4954* 4955* @remarks none 4956* 4957******************************************************************************* 4958*/ 4959static IV_STATUS_T ih264_set_air_params(void *pv_api_ip, 4960 void *pv_api_op, 4961 cfg_params_t *ps_cfg) 4962{ 4963 /* ctrl call I/O structures */ 4964 ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip; 4965 ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op; 4966 4967 ps_op->s_ive_op.u4_error_code = 0; 4968 4969 ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode; 4970 ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period; 4971 4972 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 4973 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 4974 4975 return IV_SUCCESS; 4976} 4977 4978/** 4979******************************************************************************* 4980* 4981* @brief 4982* Sets motion estimation parameters 4983* 4984* @par Description: 4985* Sets motion estimation parameters 4986* 4987* @param[in] pv_api_ip 4988* Pointer to input argument structure 4989* 4990* @param[out] pv_api_op 4991* Pointer to output argument structure 4992* 4993* @param[out] ps_cfg 4994* Pointer to config structure to be updated 4995* 4996* @returns error status 4997* 4998* @remarks none 4999* 5000******************************************************************************* 5001*/ 5002static IV_STATUS_T ih264_set_me_params(void *pv_api_ip, 5003 void *pv_api_op, 5004 cfg_params_t *ps_cfg) 5005{ 5006 /* ctrl call I/O structures */ 5007 ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip; 5008 ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op; 5009 5010 ps_op->s_ive_op.u4_error_code = 0; 5011 5012 ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel; 5013 ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel; 5014 ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad; 5015 ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref; 5016 ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x; 5017 ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y; 5018 ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset; 5019 5020 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 5021 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 5022 5023 return IV_SUCCESS; 5024} 5025 5026/** 5027******************************************************************************* 5028* 5029* @brief 5030* Sets Intra/Inter Prediction estimation parameters 5031* 5032* @par Description: 5033* Sets Intra/Inter Prediction estimation parameters 5034* 5035* @param[in] pv_api_ip 5036* Pointer to input argument structure 5037* 5038* @param[out] pv_api_op 5039* Pointer to output argument structure 5040* 5041* @param[out] ps_cfg 5042* Pointer to config structure to be updated 5043* 5044* @returns error status 5045* 5046* @remarks none 5047* 5048******************************************************************************* 5049*/ 5050static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip, 5051 void *pv_api_op, 5052 cfg_params_t *ps_cfg) 5053{ 5054 /* ctrl call I/O structures */ 5055 ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip; 5056 ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op; 5057 5058 ps_op->s_ive_op.u4_error_code = 0; 5059 5060 ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4; 5061 ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset; 5062 5063 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 5064 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 5065 5066 return IV_SUCCESS; 5067} 5068 5069/** 5070******************************************************************************* 5071* 5072* @brief 5073* Sets GOP parameters 5074* 5075* @par Description: 5076* Sets GOP parameters 5077* 5078* @param[in] pv_api_ip 5079* Pointer to input argument structure 5080* 5081* @param[out] pv_api_op 5082* Pointer to output argument structure 5083* 5084* @param[out] ps_cfg 5085* Pointer to config structure to be updated 5086* 5087* @returns error status 5088* 5089* @remarks none 5090* 5091******************************************************************************* 5092*/ 5093static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip, 5094 void *pv_api_op, 5095 cfg_params_t *ps_cfg) 5096{ 5097 /* ctrl call I/O structures */ 5098 ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip; 5099 ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op; 5100 5101 ps_op->s_ive_op.u4_error_code = 0; 5102 5103 ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval; 5104 ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval; 5105 5106 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 5107 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 5108 5109 return IV_SUCCESS; 5110} 5111 5112/** 5113******************************************************************************* 5114* 5115* @brief 5116* Sets profile parameters 5117* 5118* @par Description: 5119* Sets profile parameters 5120* 5121* @param[in] pv_api_ip 5122* Pointer to input argument structure 5123* 5124* @param[out] pv_api_op 5125* Pointer to output argument structure 5126* 5127* @param[out] ps_cfg 5128* Pointer to config structure to be updated 5129* 5130* @returns error status 5131* 5132* @remarks none 5133* 5134******************************************************************************* 5135*/ 5136static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip, 5137 void *pv_api_op, 5138 cfg_params_t *ps_cfg) 5139{ 5140 /* ctrl call I/O structures */ 5141 ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip; 5142 ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op; 5143 5144 ps_op->s_ive_op.u4_error_code = 0; 5145 5146 ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile; 5147 5148 ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode; 5149 5150 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 5151 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 5152 5153 return IV_SUCCESS; 5154} 5155 5156/** 5157******************************************************************************* 5158* 5159* @brief 5160* Sets disable deblock level 5161* 5162* @par Description: 5163* Sets disable deblock level. Level 0 means no disabling and level 4 means 5164* disable completely. 1, 2, 3 are intermediate levels that control amount 5165* of deblocking done. 5166* 5167* @param[in] ps_codec_obj 5168* Pointer to codec object at API level 5169* 5170* @param[in] pv_api_ip 5171* Pointer to input argument structure 5172* 5173* @param[out] pv_api_op 5174* Pointer to output argument structure 5175* 5176* @returns error status 5177* 5178* @remarks none 5179* 5180******************************************************************************* 5181*/ 5182static WORD32 ih264_set_deblock_params(void *pv_api_ip, 5183 void *pv_api_op, 5184 cfg_params_t *ps_cfg) 5185{ 5186 /* ctrl call I/O structures */ 5187 ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip; 5188 ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op; 5189 5190 ps_op->s_ive_op.u4_error_code = 0; 5191 5192 ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level; 5193 5194 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 5195 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 5196 5197 return IV_SUCCESS; 5198} 5199 5200/** 5201******************************************************************************* 5202* 5203* @brief 5204* Sets number of cores 5205* 5206* @par Description: 5207* Sets number of cores 5208* 5209* @param[in] ps_codec_obj 5210* Pointer to codec object at API level 5211* 5212* @param[in] pv_api_ip 5213* Pointer to input argument structure 5214* 5215* @param[out] pv_api_op 5216* Pointer to output argument structure 5217* 5218* @returns error status 5219* 5220* @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS 5221* 5222******************************************************************************* 5223*/ 5224static WORD32 ih264e_set_num_cores(void *pv_api_ip, 5225 void *pv_api_op, 5226 cfg_params_t *ps_cfg) 5227{ 5228 /* ctrl call I/O structures */ 5229 ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip; 5230 ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op; 5231 5232 ps_op->s_ive_op.u4_error_code = 0; 5233 5234 ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS); 5235 5236 ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; 5237 ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; 5238 5239 return IV_SUCCESS; 5240} 5241 5242/** 5243******************************************************************************* 5244* 5245* @brief 5246* Resets encoder state 5247* 5248* @par Description: 5249* Resets encoder state by calling ih264e_init() 5250* 5251* @param[in] ps_codec_obj 5252* Pointer to codec object at API level 5253* 5254* @param[in] pv_api_ip 5255* Pointer to input argument structure 5256* 5257* @param[out] pv_api_op 5258* Pointer to output argument structure 5259* 5260* @returns error status 5261* 5262* @remarks none 5263* 5264******************************************************************************* 5265*/ 5266static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj, 5267 void *pv_api_ip, 5268 void *pv_api_op) 5269{ 5270 /* codec ctxt */ 5271 codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle); 5272 5273 /* ctrl call I/O structures */ 5274 ih264e_ctl_reset_op_t *ps_op = pv_api_op; 5275 5276 UNUSED(pv_api_ip); 5277 5278 ps_op->s_ive_op.u4_error_code = 0; 5279 5280 if (ps_codec != NULL) 5281 { 5282 ih264e_init(ps_codec); 5283 } 5284 else 5285 { 5286 ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE; 5287 } 5288 5289 return IV_SUCCESS; 5290} 5291 5292/** 5293******************************************************************************* 5294* 5295* @brief 5296* Codec control call 5297* 5298* @par Description: 5299* Codec control call which in turn calls appropriate calls based on sub-command 5300* 5301* @param[in] ps_codec_obj 5302* Pointer to codec object at API level 5303* 5304* @param[in] pv_api_ip 5305* Pointer to input argument structure 5306* 5307* @param[out] pv_api_op 5308* Pointer to output argument structure 5309* 5310* @returns error status 5311* 5312* @remarks none 5313* 5314******************************************************************************* 5315*/ 5316static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj, 5317 void *pv_api_ip, 5318 void *pv_api_op) 5319{ 5320 /* codec ctxt */ 5321 codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle; 5322 5323 /* ctrl call I/O structures */ 5324 ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip; 5325 ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op; 5326 5327 /* ctrl call sub cmd */ 5328 IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd; 5329 5330 /* error status */ 5331 IV_STATUS_T ret = IV_SUCCESS; 5332 5333 /* temp var */ 5334 WORD32 i; 5335 cfg_params_t *ps_cfg = NULL; 5336 5337 /* control call is for configuring encoding params, this is not to be called 5338 * before a successful init call */ 5339 if (ps_codec->i4_init_done != 1) 5340 { 5341 ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR; 5342 ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE; 5343 return IV_FAIL; 5344 } 5345 5346 /* make it thread safe */ 5347 ithread_mutex_lock(ps_codec->pv_ctl_mutex); 5348 5349 /* find a free config param set to hold current parameters */ 5350 for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++) 5351 { 5352 if (0 == ps_codec->as_cfg[i].u4_is_valid) 5353 { 5354 ps_cfg = &ps_codec->as_cfg[i]; 5355 break; 5356 } 5357 } 5358 5359 /* If all are invalid, then start overwriting from the head config params */ 5360 if (NULL == ps_cfg) 5361 { 5362 ps_cfg = &ps_codec->as_cfg[0]; 5363 } 5364 5365 ps_cfg->u4_is_valid = 1; 5366 5367 ps_cfg->e_cmd = sub_cmd; 5368 5369 switch (sub_cmd) 5370 { 5371 case IVE_CMD_CTL_SET_DIMENSIONS: 5372 ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg); 5373 break; 5374 5375 case IVE_CMD_CTL_SET_FRAMERATE: 5376 ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg); 5377 break; 5378 5379 case IVE_CMD_CTL_SET_BITRATE: 5380 ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg); 5381 break; 5382 5383 case IVE_CMD_CTL_SET_FRAMETYPE: 5384 ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg); 5385 break; 5386 5387 case IVE_CMD_CTL_SET_QP: 5388 ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg); 5389 break; 5390 5391 case IVE_CMD_CTL_SET_ENC_MODE: 5392 ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg); 5393 break; 5394 5395 case IVE_CMD_CTL_SET_VBV_PARAMS: 5396 ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg); 5397 break; 5398 5399 case IVE_CMD_CTL_SET_AIR_PARAMS: 5400 ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg); 5401 break; 5402 5403 case IVE_CMD_CTL_SET_ME_PARAMS: 5404 ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg); 5405 break; 5406 5407 case IVE_CMD_CTL_SET_IPE_PARAMS: 5408 ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg); 5409 break; 5410 5411 case IVE_CMD_CTL_SET_GOP_PARAMS: 5412 ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg); 5413 break; 5414 5415 case IVE_CMD_CTL_SET_PROFILE_PARAMS: 5416 ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg); 5417 break; 5418 5419 case IVE_CMD_CTL_SET_DEBLOCK_PARAMS: 5420 ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg); 5421 break; 5422 5423 case IVE_CMD_CTL_RESET: 5424 5425 /* invalidate config param struct as it is being served right away */ 5426 ps_codec->as_cfg[i].u4_is_valid = 0; 5427 5428 ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op); 5429 break; 5430 5431 case IVE_CMD_CTL_SETDEFAULT: 5432 { 5433 /* ctrl call I/O structures */ 5434 ih264e_ctl_setdefault_op_t *ps_op = pv_api_op; 5435 5436 /* invalidate config param struct as it is being served right away */ 5437 ps_codec->as_cfg[i].u4_is_valid = 0; 5438 5439 /* error status */ 5440 ret = ih264e_set_default_params(ps_cfg); 5441 5442 ps_op->s_ive_op.u4_error_code = ret; 5443 5444 break; 5445 } 5446 5447 case IVE_CMD_CTL_FLUSH: 5448 5449 /* invalidate config param struct as it is being served right away */ 5450 ps_codec->as_cfg[i].u4_is_valid = 0; 5451 5452 ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op); 5453 break; 5454 5455 case IVE_CMD_CTL_GETBUFINFO: 5456 5457 /* invalidate config param struct as it is being served right away */ 5458 ps_codec->as_cfg[i].u4_is_valid = 0; 5459 5460 ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op); 5461 break; 5462 5463 case IVE_CMD_CTL_GETVERSION: 5464 { 5465 /* ctrl call I/O structures */ 5466 ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip; 5467 ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op; 5468 5469 /* invalidate config param struct as it is being served right away */ 5470 ps_codec->as_cfg[i].u4_is_valid = 0; 5471 5472 /* error status */ 5473 ps_op->s_ive_op.u4_error_code = IV_SUCCESS; 5474 5475 if (ps_ip->s_ive_ip.u4_version_bufsize <= 0) 5476 { 5477 ps_op->s_ive_op.u4_error_code = 5478 IH264E_CXA_VERS_BUF_INSUFFICIENT; 5479 ret = IV_FAIL; 5480 } 5481 else 5482 { 5483 ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version, 5484 ps_ip->s_ive_ip.u4_version_bufsize); 5485 5486 if (ret != IV_SUCCESS) 5487 { 5488 ps_op->s_ive_op.u4_error_code = 5489 IH264E_CXA_VERS_BUF_INSUFFICIENT; 5490 ret = IV_FAIL; 5491 } 5492 } 5493 break; 5494 } 5495 5496 case IVE_CMD_CTL_SET_NUM_CORES: 5497 ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg); 5498 break; 5499 5500 default: 5501 /* invalidate config param struct as it is being served right away */ 5502 ps_codec->as_cfg[i].u4_is_valid = 0; 5503 5504 DEBUG("Warning !! unrecognized control api command \n"); 5505 break; 5506 } 5507 5508 ithread_mutex_unlock(ps_codec->pv_ctl_mutex); 5509 5510 return ret; 5511} 5512 5513/** 5514******************************************************************************* 5515* 5516* @brief 5517* Codec entry point function. All the function calls to the codec are done 5518* using this function with different values specified in command 5519* 5520* @par Description: 5521* Arguments are tested for validity and then based on the command 5522* appropriate function is called 5523* 5524* @param[in] ps_handle 5525* API level handle for codec 5526* 5527* @param[in] pv_api_ip 5528* Input argument structure 5529* 5530* @param[out] pv_api_op 5531* Output argument structure 5532* 5533* @returns error_status 5534* 5535* @remarks 5536* 5537******************************************************************************* 5538*/ 5539IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle, 5540 void *pv_api_ip, 5541 void *pv_api_op) 5542{ 5543 /* api command */ 5544 WORD32 command = IV_CMD_NA; 5545 5546 /* error status */ 5547 IV_STATUS_T e_status; 5548 WORD32 ret; 5549 5550 /* tmp var */ 5551 WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip; 5552 5553 /* validate input / output structures */ 5554 e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op); 5555 5556 if (e_status != IV_SUCCESS) 5557 { 5558 DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1)); 5559 return IV_FAIL; 5560 } 5561 5562 pu4_ptr_cmd++; 5563 5564 command = *pu4_ptr_cmd; 5565 5566 switch (command) 5567 { 5568 case IV_CMD_GET_NUM_MEM_REC: 5569 ret = ih264e_get_num_rec(pv_api_ip, pv_api_op); 5570 break; 5571 5572 case IV_CMD_FILL_NUM_MEM_REC: 5573 ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op); 5574 break; 5575 5576 case IV_CMD_INIT: 5577 ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op); 5578 break; 5579 5580 case IV_CMD_RETRIEVE_MEMREC: 5581 ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op); 5582 break; 5583 5584 case IVE_CMD_VIDEO_CTL: 5585 ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op); 5586 break; 5587 5588 case IVE_CMD_VIDEO_ENCODE: 5589 ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op); 5590 break; 5591 5592 default: 5593 ret = IV_FAIL; 5594 break; 5595 } 5596 5597 return (IV_STATUS_T) ret; 5598} 5599