drm_mode.h revision 7b228e900f59cda3cafb60692be9dd7aced6ad96 
1/*
2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4 * Copyright (c) 2008 Red Hat Inc.
5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6 * Copyright (c) 2007-2008 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H
29
30#define DRM_DISPLAY_INFO_LEN	32
31#define DRM_CONNECTOR_NAME_LEN	32
32#define DRM_DISPLAY_MODE_LEN	32
33#define DRM_PROP_NAME_LEN	32
34
35#define DRM_MODE_TYPE_BUILTIN	(1<<0)
36#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
37#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
38#define DRM_MODE_TYPE_PREFERRED	(1<<3)
39#define DRM_MODE_TYPE_DEFAULT	(1<<4)
40#define DRM_MODE_TYPE_USERDEF	(1<<5)
41#define DRM_MODE_TYPE_DRIVER	(1<<6)
42
43/* Video mode flags */
44/* bit compatible with the xorg definitions. */
45#define DRM_MODE_FLAG_PHSYNC	(1<<0)
46#define DRM_MODE_FLAG_NHSYNC	(1<<1)
47#define DRM_MODE_FLAG_PVSYNC	(1<<2)
48#define DRM_MODE_FLAG_NVSYNC	(1<<3)
49#define DRM_MODE_FLAG_INTERLACE	(1<<4)
50#define DRM_MODE_FLAG_DBLSCAN	(1<<5)
51#define DRM_MODE_FLAG_CSYNC	(1<<6)
52#define DRM_MODE_FLAG_PCSYNC	(1<<7)
53#define DRM_MODE_FLAG_NCSYNC	(1<<8)
54#define DRM_MODE_FLAG_HSKEW	(1<<9) /* hskew provided */
55#define DRM_MODE_FLAG_BCAST	(1<<10)
56#define DRM_MODE_FLAG_PIXMUX	(1<<11)
57#define DRM_MODE_FLAG_DBLCLK	(1<<12)
58#define DRM_MODE_FLAG_CLKDIV2	(1<<13)
59
60/* DPMS flags */
61/* bit compatible with the xorg definitions. */
62#define DRM_MODE_DPMS_ON	0
63#define DRM_MODE_DPMS_STANDBY	1
64#define DRM_MODE_DPMS_SUSPEND	2
65#define DRM_MODE_DPMS_OFF	3
66
67/* Scaling mode options */
68#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
69					     software can still scale) */
70#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
71#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
72#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */
73
74/* Dithering mode options */
75#define DRM_MODE_DITHERING_OFF	0
76#define DRM_MODE_DITHERING_ON	1
77#define DRM_MODE_DITHERING_AUTO 2
78
79/* Dirty info options */
80#define DRM_MODE_DIRTY_OFF      0
81#define DRM_MODE_DIRTY_ON       1
82#define DRM_MODE_DIRTY_ANNOTATE 2
83
84struct drm_mode_modeinfo {
85	__u32 clock;
86	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
87	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
88
89	__u32 vrefresh;
90
91	__u32 flags;
92	__u32 type;
93	char name[DRM_DISPLAY_MODE_LEN];
94};
95
96struct drm_mode_card_res {
97	__u64 fb_id_ptr;
98	__u64 crtc_id_ptr;
99	__u64 connector_id_ptr;
100	__u64 encoder_id_ptr;
101	__u32 count_fbs;
102	__u32 count_crtcs;
103	__u32 count_connectors;
104	__u32 count_encoders;
105	__u32 min_width, max_width;
106	__u32 min_height, max_height;
107};
108
109struct drm_mode_crtc {
110	__u64 set_connectors_ptr;
111	__u32 count_connectors;
112
113	__u32 crtc_id; /**< Id */
114	__u32 fb_id; /**< Id of framebuffer */
115
116	__u32 x, y; /**< Position on the frameuffer */
117
118	__u32 gamma_size;
119	__u32 mode_valid;
120	struct drm_mode_modeinfo mode;
121};
122
123#define DRM_MODE_PRESENT_TOP_FIELD     (1<<0)
124#define DRM_MODE_PRESENT_BOTTOM_FIELD  (1<<1)
125
126/* Planes blend with or override other bits on the CRTC */
127struct drm_mode_set_plane {
128	__u32 plane_id;
129	__u32 crtc_id;
130	__u32 fb_id; /* fb object contains surface format type */
131	__u32 flags;
132
133	/* Signed dest location allows it to be partially off screen */
134	__s32 crtc_x, crtc_y;
135	__u32 crtc_w, crtc_h;
136
137	/* Source values are 16.16 fixed point */
138	__u32 src_x, src_y;
139	__u32 src_h, src_w;
140};
141
142struct drm_mode_get_plane {
143	__u32 plane_id;
144
145	__u32 crtc_id;
146	__u32 fb_id;
147
148	__u32 possible_crtcs;
149	__u32 gamma_size;
150
151	__u32 count_format_types;
152	__u64 format_type_ptr;
153};
154
155struct drm_mode_get_plane_res {
156	__u64 plane_id_ptr;
157	__u32 count_planes;
158};
159
160#define DRM_MODE_ENCODER_NONE	0
161#define DRM_MODE_ENCODER_DAC	1
162#define DRM_MODE_ENCODER_TMDS	2
163#define DRM_MODE_ENCODER_LVDS	3
164#define DRM_MODE_ENCODER_TVDAC	4
165
166struct drm_mode_get_encoder {
167	__u32 encoder_id;
168	__u32 encoder_type;
169
170	__u32 crtc_id; /**< Id of crtc */
171
172	__u32 possible_crtcs;
173	__u32 possible_clones;
174};
175
176/* This is for connectors with multiple signal types. */
177/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
178#define DRM_MODE_SUBCONNECTOR_Automatic	0
179#define DRM_MODE_SUBCONNECTOR_Unknown	0
180#define DRM_MODE_SUBCONNECTOR_DVID	3
181#define DRM_MODE_SUBCONNECTOR_DVIA	4
182#define DRM_MODE_SUBCONNECTOR_Composite	5
183#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
184#define DRM_MODE_SUBCONNECTOR_Component	8
185#define DRM_MODE_SUBCONNECTOR_SCART	9
186
187#define DRM_MODE_CONNECTOR_Unknown	0
188#define DRM_MODE_CONNECTOR_VGA		1
189#define DRM_MODE_CONNECTOR_DVII		2
190#define DRM_MODE_CONNECTOR_DVID		3
191#define DRM_MODE_CONNECTOR_DVIA		4
192#define DRM_MODE_CONNECTOR_Composite	5
193#define DRM_MODE_CONNECTOR_SVIDEO	6
194#define DRM_MODE_CONNECTOR_LVDS		7
195#define DRM_MODE_CONNECTOR_Component	8
196#define DRM_MODE_CONNECTOR_9PinDIN	9
197#define DRM_MODE_CONNECTOR_DisplayPort	10
198#define DRM_MODE_CONNECTOR_HDMIA	11
199#define DRM_MODE_CONNECTOR_HDMIB	12
200#define DRM_MODE_CONNECTOR_TV		13
201#define DRM_MODE_CONNECTOR_eDP		14
202
203struct drm_mode_get_connector {
204
205	__u64 encoders_ptr;
206	__u64 modes_ptr;
207	__u64 props_ptr;
208	__u64 prop_values_ptr;
209
210	__u32 count_modes;
211	__u32 count_props;
212	__u32 count_encoders;
213
214	__u32 encoder_id; /**< Current Encoder */
215	__u32 connector_id; /**< Id */
216	__u32 connector_type;
217	__u32 connector_type_id;
218
219	__u32 connection;
220	__u32 mm_width, mm_height; /**< HxW in millimeters */
221	__u32 subpixel;
222};
223
224#define DRM_MODE_PROP_PENDING	(1<<0)
225#define DRM_MODE_PROP_RANGE	(1<<1)
226#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
227#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
228#define DRM_MODE_PROP_BLOB	(1<<4)
229#define DRM_MODE_PROP_BITMASK	(1<<5) /* bitmask of enumerated types */
230
231struct drm_mode_property_enum {
232	__u64 value;
233	char name[DRM_PROP_NAME_LEN];
234};
235
236struct drm_mode_get_property {
237	__u64 values_ptr; /* values and blob lengths */
238	__u64 enum_blob_ptr; /* enum and blob id ptrs */
239
240	__u32 prop_id;
241	__u32 flags;
242	char name[DRM_PROP_NAME_LEN];
243
244	__u32 count_values;
245	__u32 count_enum_blobs;
246};
247
248struct drm_mode_connector_set_property {
249	__u64 value;
250	__u32 prop_id;
251	__u32 connector_id;
252};
253
254#define DRM_MODE_OBJECT_CRTC 0xcccccccc
255#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
256#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
257#define DRM_MODE_OBJECT_MODE 0xdededede
258#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
259#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
260#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
261#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
262
263struct drm_mode_obj_get_properties {
264	__u64 props_ptr;
265	__u64 prop_values_ptr;
266	__u32 count_props;
267	__u32 obj_id;
268	__u32 obj_type;
269};
270
271struct drm_mode_obj_set_property {
272	__u64 value;
273	__u32 prop_id;
274	__u32 obj_id;
275	__u32 obj_type;
276};
277
278struct drm_mode_get_blob {
279	__u32 blob_id;
280	__u32 length;
281	__u64 data;
282};
283
284struct drm_mode_fb_cmd {
285	__u32 fb_id;
286	__u32 width, height;
287	__u32 pitch;
288	__u32 bpp;
289	__u32 depth;
290	/* driver specific handle */
291	__u32 handle;
292};
293
294#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
295
296struct drm_mode_fb_cmd2 {
297	__u32 fb_id;
298	__u32 width, height;
299	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
300	__u32 flags;
301
302	/*
303	 * In case of planar formats, this ioctl allows up to 4
304	 * buffer objects with offsets and pitches per plane.
305	 * The pitch and offset order is dictated by the fourcc,
306	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
307	 *
308	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
309	 *   followed by an interleaved U/V plane containing
310	 *   8 bit 2x2 subsampled colour difference samples.
311	 *
312	 * So it would consist of Y as offset[0] and UV as
313	 * offset[1].  Note that offset[0] will generally
314	 * be 0.
315	 */
316	__u32 handles[4];
317	__u32 pitches[4]; /* pitch for each plane */
318	__u32 offsets[4]; /* offset of each plane */
319};
320
321#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
322#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
323#define DRM_MODE_FB_DIRTY_FLAGS         0x03
324
325/*
326 * Mark a region of a framebuffer as dirty.
327 *
328 * Some hardware does not automatically update display contents
329 * as a hardware or software draw to a framebuffer. This ioctl
330 * allows userspace to tell the kernel and the hardware what
331 * regions of the framebuffer have changed.
332 *
333 * The kernel or hardware is free to update more then just the
334 * region specified by the clip rects. The kernel or hardware
335 * may also delay and/or coalesce several calls to dirty into a
336 * single update.
337 *
338 * Userspace may annotate the updates, the annotates are a
339 * promise made by the caller that the change is either a copy
340 * of pixels or a fill of a single color in the region specified.
341 *
342 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
343 * the number of updated regions are half of num_clips given,
344 * where the clip rects are paired in src and dst. The width and
345 * height of each one of the pairs must match.
346 *
347 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
348 * promises that the region specified of the clip rects is filled
349 * completely with a single color as given in the color argument.
350 */
351
352struct drm_mode_fb_dirty_cmd {
353	__u32 fb_id;
354	__u32 flags;
355	__u32 color;
356	__u32 num_clips;
357	__u64 clips_ptr;
358};
359
360struct drm_mode_mode_cmd {
361	__u32 connector_id;
362	struct drm_mode_modeinfo mode;
363};
364
365#define DRM_MODE_CURSOR_BO	(1<<0)
366#define DRM_MODE_CURSOR_MOVE	(1<<1)
367
368/*
369 * depending on the value in flags diffrent members are used.
370 *
371 * CURSOR_BO uses
372 *    crtc
373 *    width
374 *    height
375 *    handle - if 0 turns the cursor of
376 *
377 * CURSOR_MOVE uses
378 *    crtc
379 *    x
380 *    y
381 */
382struct drm_mode_cursor {
383	__u32 flags;
384	__u32 crtc_id;
385	__s32 x;
386	__s32 y;
387	__u32 width;
388	__u32 height;
389	/* driver specific handle */
390	__u32 handle;
391};
392
393struct drm_mode_crtc_lut {
394	__u32 crtc_id;
395	__u32 gamma_size;
396
397	/* pointers to arrays */
398	__u64 red;
399	__u64 green;
400	__u64 blue;
401};
402
403#define DRM_MODE_PAGE_FLIP_EVENT 0x01
404#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT
405
406/*
407 * Request a page flip on the specified crtc.
408 *
409 * This ioctl will ask KMS to schedule a page flip for the specified
410 * crtc.  Once any pending rendering targeting the specified fb (as of
411 * ioctl time) has completed, the crtc will be reprogrammed to display
412 * that fb after the next vertical refresh.  The ioctl returns
413 * immediately, but subsequent rendering to the current fb will block
414 * in the execbuffer ioctl until the page flip happens.  If a page
415 * flip is already pending as the ioctl is called, EBUSY will be
416 * returned.
417 *
418 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will
419 * request that drm sends back a vblank event (see drm.h: struct
420 * drm_event_vblank) when the page flip is done.  The user_data field
421 * passed in with this ioctl will be returned as the user_data field
422 * in the vblank event struct.
423 *
424 * The reserved field must be zero until we figure out something
425 * clever to use it for.
426 */
427
428struct drm_mode_crtc_page_flip {
429	__u32 crtc_id;
430	__u32 fb_id;
431	__u32 flags;
432	__u32 reserved;
433	__u64 user_data;
434};
435
436/* create a dumb scanout buffer */
437struct drm_mode_create_dumb {
438        __u32 height;
439        __u32 width;
440        __u32 bpp;
441        __u32 flags;
442        /* handle, pitch, size will be returned */
443        __u32 handle;
444        __u32 pitch;
445        __u64 size;
446};
447
448/* set up for mmap of a dumb scanout buffer */
449struct drm_mode_map_dumb {
450        /** Handle for the object being mapped. */
451        __u32 handle;
452        __u32 pad;
453        /**
454         * Fake offset to use for subsequent mmap call
455         *
456         * This is a fixed-size type for 32/64 compatibility.
457         */
458        __u64 offset;
459};
460
461struct drm_mode_destroy_dumb {
462	__u32 handle;
463};
464
465#endif
466