1//==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This implements the Emit routines for the SelectionDAG class, which creates 11// MachineInstrs based on the decisions of the SelectionDAG instruction 12// selection. 13// 14//===----------------------------------------------------------------------===// 15 16#include "InstrEmitter.h" 17#include "SDNodeDbgValue.h" 18#include "llvm/ADT/Statistic.h" 19#include "llvm/CodeGen/MachineConstantPool.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineRegisterInfo.h" 23#include "llvm/CodeGen/StackMaps.h" 24#include "llvm/IR/DataLayout.h" 25#include "llvm/Support/Debug.h" 26#include "llvm/Support/ErrorHandling.h" 27#include "llvm/Support/MathExtras.h" 28#include "llvm/Target/TargetInstrInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetSubtargetInfo.h" 31using namespace llvm; 32 33#define DEBUG_TYPE "instr-emitter" 34 35/// MinRCSize - Smallest register class we allow when constraining virtual 36/// registers. If satisfying all register class constraints would require 37/// using a smaller register class, emit a COPY to a new virtual register 38/// instead. 39const unsigned MinRCSize = 4; 40 41/// CountResults - The results of target nodes have register or immediate 42/// operands first, then an optional chain, and optional glue operands (which do 43/// not go into the resulting MachineInstr). 44unsigned InstrEmitter::CountResults(SDNode *Node) { 45 unsigned N = Node->getNumValues(); 46 while (N && Node->getValueType(N - 1) == MVT::Glue) 47 --N; 48 if (N && Node->getValueType(N - 1) == MVT::Other) 49 --N; // Skip over chain result. 50 return N; 51} 52 53/// countOperands - The inputs to target nodes have any actual inputs first, 54/// followed by an optional chain operand, then an optional glue operand. 55/// Compute the number of actual operands that will go into the resulting 56/// MachineInstr. 57/// 58/// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding 59/// the chain and glue. These operands may be implicit on the machine instr. 60static unsigned countOperands(SDNode *Node, unsigned NumExpUses, 61 unsigned &NumImpUses) { 62 unsigned N = Node->getNumOperands(); 63 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 64 --N; 65 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) 66 --N; // Ignore chain if it exists. 67 68 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses. 69 NumImpUses = N - NumExpUses; 70 for (unsigned I = N; I > NumExpUses; --I) { 71 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1))) 72 continue; 73 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1))) 74 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg())) 75 continue; 76 NumImpUses = N - I; 77 break; 78 } 79 80 return N; 81} 82 83/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 84/// implicit physical register output. 85void InstrEmitter:: 86EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, 87 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 88 unsigned VRBase = 0; 89 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 90 // Just use the input register directly! 91 SDValue Op(Node, ResNo); 92 if (IsClone) 93 VRBaseMap.erase(Op); 94 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 95 (void)isNew; // Silence compiler warning. 96 assert(isNew && "Node emitted out of order - early"); 97 return; 98 } 99 100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 101 // the CopyToReg'd destination register instead of creating a new vreg. 102 bool MatchReg = true; 103 const TargetRegisterClass *UseRC = nullptr; 104 MVT VT = Node->getSimpleValueType(ResNo); 105 106 // Stick to the preferred register classes for legal types. 107 if (TLI->isTypeLegal(VT)) 108 UseRC = TLI->getRegClassFor(VT); 109 110 if (!IsClone && !IsCloned) 111 for (SDNode *User : Node->uses()) { 112 bool Match = true; 113 if (User->getOpcode() == ISD::CopyToReg && 114 User->getOperand(2).getNode() == Node && 115 User->getOperand(2).getResNo() == ResNo) { 116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 118 VRBase = DestReg; 119 Match = false; 120 } else if (DestReg != SrcReg) 121 Match = false; 122 } else { 123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 124 SDValue Op = User->getOperand(i); 125 if (Op.getNode() != Node || Op.getResNo() != ResNo) 126 continue; 127 MVT VT = Node->getSimpleValueType(Op.getResNo()); 128 if (VT == MVT::Other || VT == MVT::Glue) 129 continue; 130 Match = false; 131 if (User->isMachineOpcode()) { 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 133 const TargetRegisterClass *RC = nullptr; 134 if (i+II.getNumDefs() < II.getNumOperands()) { 135 RC = TRI->getAllocatableClass( 136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 137 } 138 if (!UseRC) 139 UseRC = RC; 140 else if (RC) { 141 const TargetRegisterClass *ComRC = 142 TRI->getCommonSubClass(UseRC, RC); 143 // If multiple uses expect disjoint register classes, we emit 144 // copies in AddRegisterOperand. 145 if (ComRC) 146 UseRC = ComRC; 147 } 148 } 149 } 150 } 151 MatchReg &= Match; 152 if (VRBase) 153 break; 154 } 155 156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 158 159 // Figure out the register class to create for the destreg. 160 if (VRBase) { 161 DstRC = MRI->getRegClass(VRBase); 162 } else if (UseRC) { 163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!"); 164 DstRC = UseRC; 165 } else { 166 DstRC = TLI->getRegClassFor(VT); 167 } 168 169 // If all uses are reading from the src physical register and copying the 170 // register is either impossible or very expensive, then don't create a copy. 171 if (MatchReg && SrcRC->getCopyCost() < 0) { 172 VRBase = SrcReg; 173 } else { 174 // Create the reg, emit the copy. 175 VRBase = MRI->createVirtualRegister(DstRC); 176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 177 VRBase).addReg(SrcReg); 178 } 179 180 SDValue Op(Node, ResNo); 181 if (IsClone) 182 VRBaseMap.erase(Op); 183 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 184 (void)isNew; // Silence compiler warning. 185 assert(isNew && "Node emitted out of order - early"); 186} 187 188/// getDstOfCopyToRegUse - If the only use of the specified result number of 189/// node is a CopyToReg, return its destination register. Return 0 otherwise. 190unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node, 191 unsigned ResNo) const { 192 if (!Node->hasOneUse()) 193 return 0; 194 195 SDNode *User = *Node->use_begin(); 196 if (User->getOpcode() == ISD::CopyToReg && 197 User->getOperand(2).getNode() == Node && 198 User->getOperand(2).getResNo() == ResNo) { 199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 200 if (TargetRegisterInfo::isVirtualRegister(Reg)) 201 return Reg; 202 } 203 return 0; 204} 205 206void InstrEmitter::CreateVirtualRegisters(SDNode *Node, 207 MachineInstrBuilder &MIB, 208 const MCInstrDesc &II, 209 bool IsClone, bool IsCloned, 210 DenseMap<SDValue, unsigned> &VRBaseMap) { 211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && 212 "IMPLICIT_DEF should have been handled as a special case elsewhere!"); 213 214 unsigned NumResults = CountResults(Node); 215 for (unsigned i = 0; i < II.getNumDefs(); ++i) { 216 // If the specific node value is only used by a CopyToReg and the dest reg 217 // is a vreg in the same register class, use the CopyToReg'd destination 218 // register instead of creating a new vreg. 219 unsigned VRBase = 0; 220 const TargetRegisterClass *RC = 221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 222 // Always let the value type influence the used register class. The 223 // constraints on the instruction may be too lax to represent the value 224 // type correctly. For example, a 64-bit float (X86::FR64) can't live in 225 // the 32-bit float super-class (X86::FR32). 226 if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { 227 const TargetRegisterClass *VTRC = 228 TLI->getRegClassFor(Node->getSimpleValueType(i)); 229 if (RC) 230 VTRC = TRI->getCommonSubClass(RC, VTRC); 231 if (VTRC) 232 RC = VTRC; 233 } 234 235 if (II.OpInfo[i].isOptionalDef()) { 236 // Optional def must be a physical register. 237 unsigned NumResults = CountResults(Node); 238 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg(); 239 assert(TargetRegisterInfo::isPhysicalRegister(VRBase)); 240 MIB.addReg(VRBase, RegState::Define); 241 } 242 243 if (!VRBase && !IsClone && !IsCloned) 244 for (SDNode *User : Node->uses()) { 245 if (User->getOpcode() == ISD::CopyToReg && 246 User->getOperand(2).getNode() == Node && 247 User->getOperand(2).getResNo() == i) { 248 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 249 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); 251 if (RegRC == RC) { 252 VRBase = Reg; 253 MIB.addReg(VRBase, RegState::Define); 254 break; 255 } 256 } 257 } 258 } 259 260 // Create the result registers for this node and add the result regs to 261 // the machine instruction. 262 if (VRBase == 0) { 263 assert(RC && "Isn't a register operand!"); 264 VRBase = MRI->createVirtualRegister(RC); 265 MIB.addReg(VRBase, RegState::Define); 266 } 267 268 // If this def corresponds to a result of the SDNode insert the VRBase into 269 // the lookup map. 270 if (i < NumResults) { 271 SDValue Op(Node, i); 272 if (IsClone) 273 VRBaseMap.erase(Op); 274 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 275 (void)isNew; // Silence compiler warning. 276 assert(isNew && "Node emitted out of order - early"); 277 } 278 } 279} 280 281/// getVR - Return the virtual register corresponding to the specified result 282/// of the specified node. 283unsigned InstrEmitter::getVR(SDValue Op, 284 DenseMap<SDValue, unsigned> &VRBaseMap) { 285 if (Op.isMachineOpcode() && 286 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { 287 // Add an IMPLICIT_DEF instruction before every use. 288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); 289 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc 290 // does not include operand register class info. 291 if (!VReg) { 292 const TargetRegisterClass *RC = 293 TLI->getRegClassFor(Op.getSimpleValueType()); 294 VReg = MRI->createVirtualRegister(RC); 295 } 296 BuildMI(*MBB, InsertPos, Op.getDebugLoc(), 297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 298 return VReg; 299 } 300 301 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 302 assert(I != VRBaseMap.end() && "Node emitted out of order - late"); 303 return I->second; 304} 305 306 307/// AddRegisterOperand - Add the specified register as an operand to the 308/// specified machine instr. Insert register copies if the register is 309/// not in the required register class. 310void 311InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 312 SDValue Op, 313 unsigned IIOpNum, 314 const MCInstrDesc *II, 315 DenseMap<SDValue, unsigned> &VRBaseMap, 316 bool IsDebug, bool IsClone, bool IsCloned) { 317 assert(Op.getValueType() != MVT::Other && 318 Op.getValueType() != MVT::Glue && 319 "Chain and glue operands should occur at end of operand list!"); 320 // Get/emit the operand. 321 unsigned VReg = getVR(Op, VRBaseMap); 322 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); 323 324 const MCInstrDesc &MCID = MIB->getDesc(); 325 bool isOptDef = IIOpNum < MCID.getNumOperands() && 326 MCID.OpInfo[IIOpNum].isOptionalDef(); 327 328 // If the instruction requires a register in a different class, create 329 // a new virtual register and copy the value into it, but first attempt to 330 // shrink VReg's register class within reason. For example, if VReg == GR32 331 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. 332 if (II) { 333 const TargetRegisterClass *DstRC = nullptr; 334 if (IIOpNum < II->getNumOperands()) 335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); 336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { 337 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 338 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), 339 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 340 VReg = NewVReg; 341 } 342 } 343 344 // If this value has only one use, that use is a kill. This is a 345 // conservative approximation. InstrEmitter does trivial coalescing 346 // with CopyFromReg nodes, so don't emit kill flags for them. 347 // Avoid kill flags on Schedule cloned nodes, since there will be 348 // multiple uses. 349 // Tied operands are never killed, so we need to check that. And that 350 // means we need to determine the index of the operand. 351 bool isKill = Op.hasOneUse() && 352 Op.getNode()->getOpcode() != ISD::CopyFromReg && 353 !IsDebug && 354 !(IsClone || IsCloned); 355 if (isKill) { 356 unsigned Idx = MIB->getNumOperands(); 357 while (Idx > 0 && 358 MIB->getOperand(Idx-1).isReg() && 359 MIB->getOperand(Idx-1).isImplicit()) 360 --Idx; 361 bool isTied = MCID.getOperandConstraint(Idx, MCOI::TIED_TO) != -1; 362 if (isTied) 363 isKill = false; 364 } 365 366 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | 367 getDebugRegState(IsDebug)); 368} 369 370/// AddOperand - Add the specified operand to the specified machine instr. II 371/// specifies the instruction information for the node, and IIOpNum is the 372/// operand number (in the II) that we are adding. 373void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 374 SDValue Op, 375 unsigned IIOpNum, 376 const MCInstrDesc *II, 377 DenseMap<SDValue, unsigned> &VRBaseMap, 378 bool IsDebug, bool IsClone, bool IsCloned) { 379 if (Op.isMachineOpcode()) { 380 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 381 IsDebug, IsClone, IsCloned); 382 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 383 MIB.addImm(C->getSExtValue()); 384 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) { 385 MIB.addFPImm(F->getConstantFPValue()); 386 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) { 387 // Turn additional physreg operands into implicit uses on non-variadic 388 // instructions. This is used by call and return instructions passing 389 // arguments in registers. 390 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic()); 391 MIB.addReg(R->getReg(), getImplRegState(Imp)); 392 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) { 393 MIB.addRegMask(RM->getRegMask()); 394 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) { 395 MIB.addGlobalAddress(TGA->getGlobal(), TGA->getOffset(), 396 TGA->getTargetFlags()); 397 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) { 398 MIB.addMBB(BBNode->getBasicBlock()); 399 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) { 400 MIB.addFrameIndex(FI->getIndex()); 401 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) { 402 MIB.addJumpTableIndex(JT->getIndex(), JT->getTargetFlags()); 403 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) { 404 int Offset = CP->getOffset(); 405 unsigned Align = CP->getAlignment(); 406 Type *Type = CP->getType(); 407 // MachineConstantPool wants an explicit alignment. 408 if (Align == 0) { 409 Align = MF->getTarget().getDataLayout()->getPrefTypeAlignment(Type); 410 if (Align == 0) { 411 // Alignment of vector types. FIXME! 412 Align = MF->getTarget().getDataLayout()->getTypeAllocSize(Type); 413 } 414 } 415 416 unsigned Idx; 417 MachineConstantPool *MCP = MF->getConstantPool(); 418 if (CP->isMachineConstantPoolEntry()) 419 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align); 420 else 421 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align); 422 MIB.addConstantPoolIndex(Idx, Offset, CP->getTargetFlags()); 423 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) { 424 MIB.addExternalSymbol(ES->getSymbol(), ES->getTargetFlags()); 425 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) { 426 MIB.addBlockAddress(BA->getBlockAddress(), 427 BA->getOffset(), 428 BA->getTargetFlags()); 429 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) { 430 MIB.addTargetIndex(TI->getIndex(), TI->getOffset(), TI->getTargetFlags()); 431 } else { 432 assert(Op.getValueType() != MVT::Other && 433 Op.getValueType() != MVT::Glue && 434 "Chain and glue operands should occur at end of operand list!"); 435 AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap, 436 IsDebug, IsClone, IsCloned); 437 } 438} 439 440unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 441 MVT VT, DebugLoc DL) { 442 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); 443 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 444 445 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 446 // within reason. 447 if (RC && RC != VRC) 448 RC = MRI->constrainRegClass(VReg, RC, MinRCSize); 449 450 // VReg has been adjusted. It can be used with SubIdx operands now. 451 if (RC) 452 return VReg; 453 454 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual 455 // register instead. 456 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 457 assert(RC && "No legal register class for VT supports that SubIdx"); 458 unsigned NewReg = MRI->createVirtualRegister(RC); 459 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) 460 .addReg(VReg); 461 return NewReg; 462} 463 464/// EmitSubregNode - Generate machine code for subreg nodes. 465/// 466void InstrEmitter::EmitSubregNode(SDNode *Node, 467 DenseMap<SDValue, unsigned> &VRBaseMap, 468 bool IsClone, bool IsCloned) { 469 unsigned VRBase = 0; 470 unsigned Opc = Node->getMachineOpcode(); 471 472 // If the node is only used by a CopyToReg and the dest reg is a vreg, use 473 // the CopyToReg'd destination register instead of creating a new vreg. 474 for (SDNode *User : Node->uses()) { 475 if (User->getOpcode() == ISD::CopyToReg && 476 User->getOperand(2).getNode() == Node) { 477 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg(); 478 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { 479 VRBase = DestReg; 480 break; 481 } 482 } 483 } 484 485 if (Opc == TargetOpcode::EXTRACT_SUBREG) { 486 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no 487 // constraints on the %dst register, COPY can target all legal register 488 // classes. 489 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 490 const TargetRegisterClass *TRC = 491 TLI->getRegClassFor(Node->getSimpleValueType(0)); 492 493 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 494 MachineInstr *DefMI = MRI->getVRegDef(VReg); 495 unsigned SrcReg, DstReg, DefSubIdx; 496 if (DefMI && 497 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 498 SubIdx == DefSubIdx && 499 TRC == MRI->getRegClass(SrcReg)) { 500 // Optimize these: 501 // r1025 = s/zext r1024, 4 502 // r1026 = extract_subreg r1025, 4 503 // to a copy 504 // r1026 = copy r1024 505 VRBase = MRI->createVirtualRegister(TRC); 506 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 507 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); 508 MRI->clearKillFlags(SrcReg); 509 } else { 510 // VReg may not support a SubIdx sub-register, and we may need to 511 // constrain its register class or issue a COPY to a compatible register 512 // class. 513 VReg = ConstrainForSubReg(VReg, SubIdx, 514 Node->getOperand(0).getSimpleValueType(), 515 Node->getDebugLoc()); 516 517 // Create the destreg if it is missing. 518 if (VRBase == 0) 519 VRBase = MRI->createVirtualRegister(TRC); 520 521 // Create the extract_subreg machine instruction. 522 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 523 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); 524 } 525 } else if (Opc == TargetOpcode::INSERT_SUBREG || 526 Opc == TargetOpcode::SUBREG_TO_REG) { 527 SDValue N0 = Node->getOperand(0); 528 SDValue N1 = Node->getOperand(1); 529 SDValue N2 = Node->getOperand(2); 530 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); 531 532 // Figure out the register class to create for the destreg. It should be 533 // the largest legal register class supporting SubIdx sub-registers. 534 // RegisterCoalescer will constrain it further if it decides to eliminate 535 // the INSERT_SUBREG instruction. 536 // 537 // %dst = INSERT_SUBREG %src, %sub, SubIdx 538 // 539 // is lowered by TwoAddressInstructionPass to: 540 // 541 // %dst = COPY %src 542 // %dst:SubIdx = COPY %sub 543 // 544 // There is no constraint on the %src register class. 545 // 546 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); 547 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); 548 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG"); 549 550 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase))) 551 VRBase = MRI->createVirtualRegister(SRC); 552 553 // Create the insert_subreg or subreg_to_reg machine instruction. 554 MachineInstrBuilder MIB = 555 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase); 556 557 // If creating a subreg_to_reg, then the first input operand 558 // is an implicit value immediate, otherwise it's a register 559 if (Opc == TargetOpcode::SUBREG_TO_REG) { 560 const ConstantSDNode *SD = cast<ConstantSDNode>(N0); 561 MIB.addImm(SD->getZExtValue()); 562 } else 563 AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 564 IsClone, IsCloned); 565 // Add the subregster being inserted 566 AddOperand(MIB, N1, 0, nullptr, VRBaseMap, /*IsDebug=*/false, 567 IsClone, IsCloned); 568 MIB.addImm(SubIdx); 569 MBB->insert(InsertPos, MIB); 570 } else 571 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg"); 572 573 SDValue Op(Node, 0); 574 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second; 575 (void)isNew; // Silence compiler warning. 576 assert(isNew && "Node emitted out of order - early"); 577} 578 579/// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 580/// COPY_TO_REGCLASS is just a normal copy, except that the destination 581/// register is constrained to be in a particular register class. 582/// 583void 584InstrEmitter::EmitCopyToRegClassNode(SDNode *Node, 585 DenseMap<SDValue, unsigned> &VRBaseMap) { 586 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); 587 588 // Create the new VReg in the destination class and emit a copy. 589 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 590 const TargetRegisterClass *DstRC = 591 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx)); 592 unsigned NewVReg = MRI->createVirtualRegister(DstRC); 593 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 594 NewVReg).addReg(VReg); 595 596 SDValue Op(Node, 0); 597 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 598 (void)isNew; // Silence compiler warning. 599 assert(isNew && "Node emitted out of order - early"); 600} 601 602/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 603/// 604void InstrEmitter::EmitRegSequence(SDNode *Node, 605 DenseMap<SDValue, unsigned> &VRBaseMap, 606 bool IsClone, bool IsCloned) { 607 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue(); 608 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx); 609 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); 610 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); 611 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 612 unsigned NumOps = Node->getNumOperands(); 613 assert((NumOps & 1) == 1 && 614 "REG_SEQUENCE must have an odd number of operands!"); 615 for (unsigned i = 1; i != NumOps; ++i) { 616 SDValue Op = Node->getOperand(i); 617 if ((i & 1) == 0) { 618 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1)); 619 // Skip physical registers as they don't have a vreg to get and we'll 620 // insert copies for them in TwoAddressInstructionPass anyway. 621 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) { 622 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); 623 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap); 624 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); 625 const TargetRegisterClass *SRC = 626 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); 627 if (SRC && SRC != RC) { 628 MRI->setRegClass(NewVReg, SRC); 629 RC = SRC; 630 } 631 } 632 } 633 AddOperand(MIB, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false, 634 IsClone, IsCloned); 635 } 636 637 MBB->insert(InsertPos, MIB); 638 SDValue Op(Node, 0); 639 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second; 640 (void)isNew; // Silence compiler warning. 641 assert(isNew && "Node emitted out of order - early"); 642} 643 644/// EmitDbgValue - Generate machine instruction for a dbg_value node. 645/// 646MachineInstr * 647InstrEmitter::EmitDbgValue(SDDbgValue *SD, 648 DenseMap<SDValue, unsigned> &VRBaseMap) { 649 uint64_t Offset = SD->getOffset(); 650 MDNode *Var = SD->getVariable(); 651 MDNode *Expr = SD->getExpression(); 652 DebugLoc DL = SD->getDebugLoc(); 653 assert(cast<MDLocalVariable>(Var)->isValidLocationForIntrinsic(DL) && 654 "Expected inlined-at fields to agree"); 655 656 if (SD->getKind() == SDDbgValue::FRAMEIX) { 657 // Stack address; this needs to be lowered in target-dependent fashion. 658 // EmitTargetCodeForFrameDebugValue is responsible for allocation. 659 return BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE)) 660 .addFrameIndex(SD->getFrameIx()) 661 .addImm(Offset) 662 .addMetadata(Var) 663 .addMetadata(Expr); 664 } 665 // Otherwise, we're going to create an instruction here. 666 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); 667 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 668 if (SD->getKind() == SDDbgValue::SDNODE) { 669 SDNode *Node = SD->getSDNode(); 670 SDValue Op = SDValue(Node, SD->getResNo()); 671 // It's possible we replaced this SDNode with other(s) and therefore 672 // didn't generate code for it. It's better to catch these cases where 673 // they happen and transfer the debug info, but trying to guarantee that 674 // in all cases would be very fragile; this is a safeguard for any 675 // that were missed. 676 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op); 677 if (I==VRBaseMap.end()) 678 MIB.addReg(0U); // undef 679 else 680 AddOperand(MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap, 681 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false); 682 } else if (SD->getKind() == SDDbgValue::CONST) { 683 const Value *V = SD->getConst(); 684 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) { 685 if (CI->getBitWidth() > 64) 686 MIB.addCImm(CI); 687 else 688 MIB.addImm(CI->getSExtValue()); 689 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) { 690 MIB.addFPImm(CF); 691 } else { 692 // Could be an Undef. In any case insert an Undef so we can see what we 693 // dropped. 694 MIB.addReg(0U); 695 } 696 } else { 697 // Insert an Undef so we can see what we dropped. 698 MIB.addReg(0U); 699 } 700 701 // Indirect addressing is indicated by an Imm as the second parameter. 702 if (SD->isIndirect()) 703 MIB.addImm(Offset); 704 else { 705 assert(Offset == 0 && "direct value cannot have an offset"); 706 MIB.addReg(0U, RegState::Debug); 707 } 708 709 MIB.addMetadata(Var); 710 MIB.addMetadata(Expr); 711 712 return &*MIB; 713} 714 715/// EmitMachineNode - Generate machine code for a target-specific node and 716/// needed dependencies. 717/// 718void InstrEmitter:: 719EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 720 DenseMap<SDValue, unsigned> &VRBaseMap) { 721 unsigned Opc = Node->getMachineOpcode(); 722 723 // Handle subreg insert/extract specially 724 if (Opc == TargetOpcode::EXTRACT_SUBREG || 725 Opc == TargetOpcode::INSERT_SUBREG || 726 Opc == TargetOpcode::SUBREG_TO_REG) { 727 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned); 728 return; 729 } 730 731 // Handle COPY_TO_REGCLASS specially. 732 if (Opc == TargetOpcode::COPY_TO_REGCLASS) { 733 EmitCopyToRegClassNode(Node, VRBaseMap); 734 return; 735 } 736 737 // Handle REG_SEQUENCE specially. 738 if (Opc == TargetOpcode::REG_SEQUENCE) { 739 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned); 740 return; 741 } 742 743 if (Opc == TargetOpcode::IMPLICIT_DEF) 744 // We want a unique VR for each IMPLICIT_DEF use. 745 return; 746 747 const MCInstrDesc &II = TII->get(Opc); 748 unsigned NumResults = CountResults(Node); 749 unsigned NumDefs = II.getNumDefs(); 750 const MCPhysReg *ScratchRegs = nullptr; 751 752 // Handle STACKMAP and PATCHPOINT specially and then use the generic code. 753 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) { 754 // Stackmaps do not have arguments and do not preserve their calling 755 // convention. However, to simplify runtime support, they clobber the same 756 // scratch registers as AnyRegCC. 757 unsigned CC = CallingConv::AnyReg; 758 if (Opc == TargetOpcode::PATCHPOINT) { 759 CC = Node->getConstantOperandVal(PatchPointOpers::CCPos); 760 NumDefs = NumResults; 761 } 762 ScratchRegs = TLI->getScratchRegisters((CallingConv::ID) CC); 763 } 764 765 unsigned NumImpUses = 0; 766 unsigned NodeOperands = 767 countOperands(Node, II.getNumOperands() - NumDefs, NumImpUses); 768 bool HasPhysRegOuts = NumResults > NumDefs && II.getImplicitDefs()!=nullptr; 769#ifndef NDEBUG 770 unsigned NumMIOperands = NodeOperands + NumResults; 771 if (II.isVariadic()) 772 assert(NumMIOperands >= II.getNumOperands() && 773 "Too few operands for a variadic node!"); 774 else 775 assert(NumMIOperands >= II.getNumOperands() && 776 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() + 777 NumImpUses && 778 "#operands for dag node doesn't match .td file!"); 779#endif 780 781 // Create the new machine instruction. 782 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); 783 784 // Add result register values for things that are defined by this 785 // instruction. 786 if (NumResults) 787 CreateVirtualRegisters(Node, MIB, II, IsClone, IsCloned, VRBaseMap); 788 789 // Emit all of the actual operands of this instruction, adding them to the 790 // instruction as appropriate. 791 bool HasOptPRefs = NumDefs > NumResults; 792 assert((!HasOptPRefs || !HasPhysRegOuts) && 793 "Unable to cope with optional defs and phys regs defs!"); 794 unsigned NumSkip = HasOptPRefs ? NumDefs - NumResults : 0; 795 for (unsigned i = NumSkip; i != NodeOperands; ++i) 796 AddOperand(MIB, Node->getOperand(i), i-NumSkip+NumDefs, &II, 797 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned); 798 799 // Add scratch registers as implicit def and early clobber 800 if (ScratchRegs) 801 for (unsigned i = 0; ScratchRegs[i]; ++i) 802 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | 803 RegState::EarlyClobber); 804 805 // Transfer all of the memory reference descriptions of this instruction. 806 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), 807 cast<MachineSDNode>(Node)->memoperands_end()); 808 809 // Insert the instruction into position in the block. This needs to 810 // happen before any custom inserter hook is called so that the 811 // hook knows where in the block to insert the replacement code. 812 MBB->insert(InsertPos, MIB); 813 814 // The MachineInstr may also define physregs instead of virtregs. These 815 // physreg values can reach other instructions in different ways: 816 // 817 // 1. When there is a use of a Node value beyond the explicitly defined 818 // virtual registers, we emit a CopyFromReg for one of the implicitly 819 // defined physregs. This only happens when HasPhysRegOuts is true. 820 // 821 // 2. A CopyFromReg reading a physreg may be glued to this instruction. 822 // 823 // 3. A glued instruction may implicitly use a physreg. 824 // 825 // 4. A glued instruction may use a RegisterSDNode operand. 826 // 827 // Collect all the used physreg defs, and make sure that any unused physreg 828 // defs are marked as dead. 829 SmallVector<unsigned, 8> UsedRegs; 830 831 // Additional results must be physical register defs. 832 if (HasPhysRegOuts) { 833 for (unsigned i = NumDefs; i < NumResults; ++i) { 834 unsigned Reg = II.getImplicitDefs()[i - NumDefs]; 835 if (!Node->hasAnyUseOfValue(i)) 836 continue; 837 // This implicitly defined physreg has a use. 838 UsedRegs.push_back(Reg); 839 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap); 840 } 841 } 842 843 // Scan the glue chain for any used physregs. 844 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) { 845 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) { 846 if (F->getOpcode() == ISD::CopyFromReg) { 847 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg()); 848 continue; 849 } else if (F->getOpcode() == ISD::CopyToReg) { 850 // Skip CopyToReg nodes that are internal to the glue chain. 851 continue; 852 } 853 // Collect declared implicit uses. 854 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); 855 UsedRegs.append(MCID.getImplicitUses(), 856 MCID.getImplicitUses() + MCID.getNumImplicitUses()); 857 // In addition to declared implicit uses, we must also check for 858 // direct RegisterSDNode operands. 859 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) 860 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) { 861 unsigned Reg = R->getReg(); 862 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 863 UsedRegs.push_back(Reg); 864 } 865 } 866 } 867 868 // Finally mark unused registers as dead. 869 if (!UsedRegs.empty() || II.getImplicitDefs()) 870 MIB->setPhysRegsDeadExcept(UsedRegs, *TRI); 871 872 // Run post-isel target hook to adjust this instruction if needed. 873 if (II.hasPostISelHook()) 874 TLI->AdjustInstrPostInstrSelection(MIB, Node); 875} 876 877/// EmitSpecialNode - Generate machine code for a target-independent node and 878/// needed dependencies. 879void InstrEmitter:: 880EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 881 DenseMap<SDValue, unsigned> &VRBaseMap) { 882 switch (Node->getOpcode()) { 883 default: 884#ifndef NDEBUG 885 Node->dump(); 886#endif 887 llvm_unreachable("This target-independent node should have been selected!"); 888 case ISD::EntryToken: 889 llvm_unreachable("EntryToken should have been excluded from the schedule!"); 890 case ISD::MERGE_VALUES: 891 case ISD::TokenFactor: // fall thru 892 break; 893 case ISD::CopyToReg: { 894 unsigned SrcReg; 895 SDValue SrcVal = Node->getOperand(2); 896 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal)) 897 SrcReg = R->getReg(); 898 else 899 SrcReg = getVR(SrcVal, VRBaseMap); 900 901 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 902 if (SrcReg == DestReg) // Coalesced away the copy? Ignore. 903 break; 904 905 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 906 DestReg).addReg(SrcReg); 907 break; 908 } 909 case ISD::CopyFromReg: { 910 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg(); 911 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap); 912 break; 913 } 914 case ISD::EH_LABEL: { 915 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel(); 916 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), 917 TII->get(TargetOpcode::EH_LABEL)).addSym(S); 918 break; 919 } 920 921 case ISD::LIFETIME_START: 922 case ISD::LIFETIME_END: { 923 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ? 924 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END; 925 926 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1)); 927 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp)) 928 .addFrameIndex(FI->getIndex()); 929 break; 930 } 931 932 case ISD::INLINEASM: { 933 unsigned NumOps = Node->getNumOperands(); 934 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 935 --NumOps; // Ignore the glue operand. 936 937 // Create the inline asm machine instruction. 938 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), 939 TII->get(TargetOpcode::INLINEASM)); 940 941 // Add the asm string as an external symbol operand. 942 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString); 943 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol(); 944 MIB.addExternalSymbol(AsmStr); 945 946 // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore 947 // bits. 948 int64_t ExtraInfo = 949 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))-> 950 getZExtValue(); 951 MIB.addImm(ExtraInfo); 952 953 // Remember to operand index of the group flags. 954 SmallVector<unsigned, 8> GroupIdx; 955 956 // Add all of the operand registers to the instruction. 957 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 958 unsigned Flags = 959 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 960 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 961 962 GroupIdx.push_back(MIB->getNumOperands()); 963 MIB.addImm(Flags); 964 ++i; // Skip the ID value. 965 966 switch (InlineAsm::getKind(Flags)) { 967 default: llvm_unreachable("Bad flags!"); 968 case InlineAsm::Kind_RegDef: 969 for (unsigned j = 0; j != NumVals; ++j, ++i) { 970 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 971 // FIXME: Add dead flags for physical and virtual registers defined. 972 // For now, mark physical register defs as implicit to help fast 973 // regalloc. This makes inline asm look a lot like calls. 974 MIB.addReg(Reg, RegState::Define | 975 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 976 } 977 break; 978 case InlineAsm::Kind_RegDefEarlyClobber: 979 case InlineAsm::Kind_Clobber: 980 for (unsigned j = 0; j != NumVals; ++j, ++i) { 981 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 982 MIB.addReg(Reg, RegState::Define | RegState::EarlyClobber | 983 getImplRegState(TargetRegisterInfo::isPhysicalRegister(Reg))); 984 } 985 break; 986 case InlineAsm::Kind_RegUse: // Use of register. 987 case InlineAsm::Kind_Imm: // Immediate. 988 case InlineAsm::Kind_Mem: // Addressing mode. 989 // The addressing mode has been selected, just add all of the 990 // operands to the machine instruction. 991 for (unsigned j = 0; j != NumVals; ++j, ++i) 992 AddOperand(MIB, Node->getOperand(i), 0, nullptr, VRBaseMap, 993 /*IsDebug=*/false, IsClone, IsCloned); 994 995 // Manually set isTied bits. 996 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) { 997 unsigned DefGroup = 0; 998 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) { 999 unsigned DefIdx = GroupIdx[DefGroup] + 1; 1000 unsigned UseIdx = GroupIdx.back() + 1; 1001 for (unsigned j = 0; j != NumVals; ++j) 1002 MIB->tieOperands(DefIdx + j, UseIdx + j); 1003 } 1004 } 1005 break; 1006 } 1007 } 1008 1009 // Get the mdnode from the asm if it exists and add it to the instruction. 1010 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode); 1011 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD(); 1012 if (MD) 1013 MIB.addMetadata(MD); 1014 1015 MBB->insert(InsertPos, MIB); 1016 break; 1017 } 1018 } 1019} 1020 1021/// InstrEmitter - Construct an InstrEmitter and set it to start inserting 1022/// at the given position in the given block. 1023InstrEmitter::InstrEmitter(MachineBasicBlock *mbb, 1024 MachineBasicBlock::iterator insertpos) 1025 : MF(mbb->getParent()), MRI(&MF->getRegInfo()), 1026 TII(MF->getSubtarget().getInstrInfo()), 1027 TRI(MF->getSubtarget().getRegisterInfo()), 1028 TLI(MF->getSubtarget().getTargetLowering()), MBB(mbb), 1029 InsertPos(insertpos) {} 1030