1dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines//==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==// 2dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// 3dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// The LLVM Compiler Infrastructure 4dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// 5dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// This file is distributed under the University of Illinois Open Source 6dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// License. See LICENSE.TXT for details. 7dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// 8dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines//===----------------------------------------------------------------------===// 9dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// When allowed by the instruction, replace a dead definition of a GPR with 10dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// the zero register. This makes the code a bit friendlier towards the 11dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// hardware's register renamer. 12dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines//===----------------------------------------------------------------------===// 13dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 14dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "AArch64.h" 15dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "AArch64RegisterInfo.h" 16dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/ADT/Statistic.h" 17dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/CodeGen/MachineFunction.h" 1837ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#include "llvm/CodeGen/MachineFunctionPass.h" 19dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/CodeGen/MachineInstr.h" 20dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/Support/Debug.h" 21dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/Support/raw_ostream.h" 2237ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#include "llvm/Target/TargetSubtargetInfo.h" 23dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesusing namespace llvm; 24dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 25dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "aarch64-dead-defs" 26dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 27dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesSTATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced"); 28dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 29dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesnamespace { 30dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesclass AArch64DeadRegisterDefinitions : public MachineFunctionPass { 31dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesprivate: 32dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const TargetRegisterInfo *TRI; 33dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI); 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool processMachineBasicBlock(MachineBasicBlock &MBB); 35dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool usesFrameIndex(const MachineInstr &MI); 36dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinespublic: 37dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines static char ID; // Pass identification, replacement for typeid. 38dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {} 39dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 4037ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines bool runOnMachineFunction(MachineFunction &F) override; 41dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 42dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const char *getPassName() const override { return "Dead register definitions"; } 43dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 4437ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines void getAnalysisUsage(AnalysisUsage &AU) const override { 45dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines AU.setPreservesCFG(); 46dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineFunctionPass::getAnalysisUsage(AU); 47dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 48dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines}; 49dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hineschar AArch64DeadRegisterDefinitions::ID = 0; 50dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} // end anonymous namespace 51dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 52dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesbool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg( 53dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned Reg, const MachineInstr &MI) { 54dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (const MachineOperand &MO : MI.implicit_operands()) 55dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (MO.isReg() && MO.isDef()) 56dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (TRI->regsOverlap(Reg, MO.getReg())) 57dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 58dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 59dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 60dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 61dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesbool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) { 62dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (const MachineOperand &Op : MI.uses()) 63dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (Op.isFI()) 64dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 65dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 66dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 67dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 68dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesbool AArch64DeadRegisterDefinitions::processMachineBasicBlock( 69dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineBasicBlock &MBB) { 70dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool Changed = false; 71dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (MachineInstr &MI : MBB) { 72dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (usesFrameIndex(MI)) { 73dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // We need to skip this instruction because while it appears to have a 74dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // dead def it uses a frame index which might expand into a multi 75dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // instruction sequence during EPI. 76dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Ignoring, operand is frame index\n"); 77dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines continue; 78dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 79dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { 80dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MachineOperand &MO = MI.getOperand(i); 81dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (MO.isReg() && MO.isDead() && MO.isDef()) { 82dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines assert(!MO.isImplicit() && "Unexpected implicit def!"); 83dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Dead def operand #" << i << " in:\n "; 84dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MI.print(dbgs())); 85dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Be careful not to change the register if it's a tied operand. 86dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (MI.isRegTiedToUseOperand(i)) { 87dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Ignoring, def is tied operand.\n"); 88dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines continue; 89dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 90dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Don't change the register if there's an implicit def of a subreg or 91dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // supperreg. 92dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) { 93dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n"); 94dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines continue; 95dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 96dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // Make sure the instruction take a register class that contains 97dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // the zero register and replace it if so. 98dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned NewReg; 99dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines switch (MI.getDesc().OpInfo[i].RegClass) { 100dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines default: 101dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Ignoring, register is not a GPR.\n"); 102dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines continue; 103dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case AArch64::GPR32RegClassID: 104dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NewReg = AArch64::WZR; 105dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 106dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case AArch64::GPR64RegClassID: 107dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines NewReg = AArch64::XZR; 108dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 109dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 110dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << " Replacing with zero register. New:\n "); 111dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines MO.setReg(NewReg); 112dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(MI.print(dbgs())); 113dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines ++NumDeadDefsReplaced; 114dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 115dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 116dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 117dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return Changed; 118dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 119dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 120dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// Scan the function for instructions that have a dead definition of a 121dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines// register. Replace that register with the zero register when possible. 122dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesbool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { 12337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines TRI = MF.getSubtarget().getRegisterInfo(); 124dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool Changed = false; 125dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); 126dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 127dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines for (auto &MBB : MF) 128dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (processMachineBasicBlock(MBB)) 129dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines Changed = true; 130dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return Changed; 131dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 132dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 133dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen HinesFunctionPass *llvm::createAArch64DeadRegisterDefinitions() { 134dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return new AArch64DeadRegisterDefinitions(); 135dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 136