1//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AArch64 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
15#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
16
17#include "AArch64.h"
18#include "AArch64RegisterInfo.h"
19#include "llvm/CodeGen/MachineCombinerPattern.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22#define GET_INSTRINFO_HEADER
23#include "AArch64GenInstrInfo.inc"
24
25namespace llvm {
26
27class AArch64Subtarget;
28class AArch64TargetMachine;
29
30class AArch64InstrInfo : public AArch64GenInstrInfo {
31  // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
32  // They will be shifted into MOTargetHintStart when accessed.
33  enum TargetMemOperandFlags {
34    MOSuppressPair = 1
35  };
36
37  const AArch64RegisterInfo RI;
38  const AArch64Subtarget &Subtarget;
39
40public:
41  explicit AArch64InstrInfo(const AArch64Subtarget &STI);
42
43  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
44  /// such, whenever a client has an instance of instruction info, it should
45  /// always be able to get register info as well (through this method).
46  const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
47
48  unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
49
50  bool isAsCheapAsAMove(const MachineInstr *MI) const override;
51
52  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
53                             unsigned &DstReg, unsigned &SubIdx) const override;
54
55  bool
56  areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
57                                  AliasAnalysis *AA = nullptr) const override;
58
59  unsigned isLoadFromStackSlot(const MachineInstr *MI,
60                               int &FrameIndex) const override;
61  unsigned isStoreToStackSlot(const MachineInstr *MI,
62                              int &FrameIndex) const override;
63
64  /// Returns true if there is a shiftable register and that the shift value
65  /// is non-zero.
66  bool hasShiftedReg(const MachineInstr *MI) const;
67
68  /// Returns true if there is an extendable register and that the extending
69  /// value is non-zero.
70  bool hasExtendedReg(const MachineInstr *MI) const;
71
72  /// \brief Does this instruction set its full destination register to zero?
73  bool isGPRZero(const MachineInstr *MI) const;
74
75  /// \brief Does this instruction rename a GPR without modifying bits?
76  bool isGPRCopy(const MachineInstr *MI) const;
77
78  /// \brief Does this instruction rename an FPR without modifying bits?
79  bool isFPRCopy(const MachineInstr *MI) const;
80
81  /// Return true if this is load/store scales or extends its register offset.
82  /// This refers to scaling a dynamic index as opposed to scaled immediates.
83  /// MI should be a memory op that allows scaled addressing.
84  bool isScaledAddr(const MachineInstr *MI) const;
85
86  /// Return true if pairing the given load or store is hinted to be
87  /// unprofitable.
88  bool isLdStPairSuppressed(const MachineInstr *MI) const;
89
90  /// Hint that pairing the given load or store is unprofitable.
91  void suppressLdStPair(MachineInstr *MI) const;
92
93  bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
94                            unsigned &Offset,
95                            const TargetRegisterInfo *TRI) const override;
96
97  bool getLdStBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
98                                 int &Offset, int &Width,
99                                 const TargetRegisterInfo *TRI) const;
100
101  bool enableClusterLoads() const override { return true; }
102
103  bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
104                          unsigned NumLoads) const override;
105
106  bool shouldScheduleAdjacent(MachineInstr *First,
107                              MachineInstr *Second) const override;
108
109  MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
110                                         uint64_t Offset, const MDNode *Var,
111                                         const MDNode *Expr, DebugLoc DL) const;
112  void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
113                        DebugLoc DL, unsigned DestReg, unsigned SrcReg,
114                        bool KillSrc, unsigned Opcode,
115                        llvm::ArrayRef<unsigned> Indices) const;
116  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
117                   DebugLoc DL, unsigned DestReg, unsigned SrcReg,
118                   bool KillSrc) const override;
119
120  void storeRegToStackSlot(MachineBasicBlock &MBB,
121                           MachineBasicBlock::iterator MBBI, unsigned SrcReg,
122                           bool isKill, int FrameIndex,
123                           const TargetRegisterClass *RC,
124                           const TargetRegisterInfo *TRI) const override;
125
126  void loadRegFromStackSlot(MachineBasicBlock &MBB,
127                            MachineBasicBlock::iterator MBBI, unsigned DestReg,
128                            int FrameIndex, const TargetRegisterClass *RC,
129                            const TargetRegisterInfo *TRI) const override;
130
131  using TargetInstrInfo::foldMemoryOperandImpl;
132  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
133                                      ArrayRef<unsigned> Ops,
134                                      int FrameIndex) const override;
135
136  bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
137                     MachineBasicBlock *&FBB,
138                     SmallVectorImpl<MachineOperand> &Cond,
139                     bool AllowModify = false) const override;
140  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
141  unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
142                        MachineBasicBlock *FBB,
143                        const SmallVectorImpl<MachineOperand> &Cond,
144                        DebugLoc DL) const override;
145  bool
146  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
147  bool canInsertSelect(const MachineBasicBlock &,
148                       const SmallVectorImpl<MachineOperand> &Cond, unsigned,
149                       unsigned, int &, int &, int &) const override;
150  void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
151                    DebugLoc DL, unsigned DstReg,
152                    const SmallVectorImpl<MachineOperand> &Cond,
153                    unsigned TrueReg, unsigned FalseReg) const override;
154  void getNoopForMachoTarget(MCInst &NopInst) const override;
155
156  /// analyzeCompare - For a comparison instruction, return the source registers
157  /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
158  /// Return true if the comparison instruction can be analyzed.
159  bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
160                      unsigned &SrcReg2, int &CmpMask,
161                      int &CmpValue) const override;
162  /// optimizeCompareInstr - Convert the instruction supplying the argument to
163  /// the comparison into one that sets the zero bit in the flags register.
164  bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
165                            unsigned SrcReg2, int CmpMask, int CmpValue,
166                            const MachineRegisterInfo *MRI) const override;
167  bool optimizeCondBranch(MachineInstr *MI) const override;
168  /// hasPattern - return true when there is potentially a faster code sequence
169  /// for an instruction chain ending in <Root>. All potential patterns are
170  /// listed
171  /// in the <Pattern> array.
172  bool hasPattern(MachineInstr &Root,
173                  SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern)
174      const override;
175
176  /// genAlternativeCodeSequence - when hasPattern() finds a pattern
177  /// this function generates the instructions that could replace the
178  /// original code sequence
179  void genAlternativeCodeSequence(
180      MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
181      SmallVectorImpl<MachineInstr *> &InsInstrs,
182      SmallVectorImpl<MachineInstr *> &DelInstrs,
183      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
184  /// useMachineCombiner - AArch64 supports MachineCombiner
185  bool useMachineCombiner() const override;
186
187  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
188private:
189  void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
190                             MachineBasicBlock *TBB,
191                             const SmallVectorImpl<MachineOperand> &Cond) const;
192};
193
194/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
195/// plus Offset.  This is intended to be used from within the prolog/epilog
196/// insertion (PEI) pass, where a virtual scratch register may be allocated
197/// if necessary, to be replaced by the scavenger at the end of PEI.
198void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
199                     DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
200                     const TargetInstrInfo *TII,
201                     MachineInstr::MIFlag = MachineInstr::NoFlags,
202                     bool SetNZCV = false);
203
204/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
205/// FP. Return false if the offset could not be handled directly in MI, and
206/// return the left-over portion by reference.
207bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
208                            unsigned FrameReg, int &Offset,
209                            const AArch64InstrInfo *TII);
210
211/// \brief Use to report the frame offset status in isAArch64FrameOffsetLegal.
212enum AArch64FrameOffsetStatus {
213  AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
214  AArch64FrameOffsetIsLegal = 0x1,      ///< Offset is legal.
215  AArch64FrameOffsetCanUpdate = 0x2     ///< Offset can apply, at least partly.
216};
217
218/// \brief Check if the @p Offset is a valid frame offset for @p MI.
219/// The returned value reports the validity of the frame offset for @p MI.
220/// It uses the values defined by AArch64FrameOffsetStatus for that.
221/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
222/// use an offset.eq
223/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
224/// rewriten in @p MI.
225/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
226/// amount that is off the limit of the legal offset.
227/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
228/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
229/// If set, @p EmittableOffset contains the amount that can be set in @p MI
230/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
231/// is a legal offset.
232int isAArch64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
233                            bool *OutUseUnscaledOp = nullptr,
234                            unsigned *OutUnscaledOp = nullptr,
235                            int *EmittableOffset = nullptr);
236
237static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
238
239static inline bool isCondBranchOpcode(int Opc) {
240  switch (Opc) {
241  case AArch64::Bcc:
242  case AArch64::CBZW:
243  case AArch64::CBZX:
244  case AArch64::CBNZW:
245  case AArch64::CBNZX:
246  case AArch64::TBZW:
247  case AArch64::TBZX:
248  case AArch64::TBNZW:
249  case AArch64::TBNZX:
250    return true;
251  default:
252    return false;
253  }
254}
255
256static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; }
257
258} // end namespace llvm
259
260#endif
261