1//===-- HexagonDisassembler.cpp - Disassembler for Hexagon ISA ------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/HexagonBaseInfo.h" 11#include "MCTargetDesc/HexagonMCInstrInfo.h" 12#include "MCTargetDesc/HexagonMCTargetDesc.h" 13#include "llvm/MC/MCContext.h" 14#include "llvm/MC/MCDisassembler.h" 15#include "llvm/MC/MCExpr.h" 16#include "llvm/MC/MCFixedLenDisassembler.h" 17#include "llvm/MC/MCInst.h" 18#include "llvm/MC/MCInstrDesc.h" 19#include "llvm/MC/MCSubtargetInfo.h" 20#include "llvm/Support/Debug.h" 21#include "llvm/Support/Endian.h" 22#include "llvm/Support/ErrorHandling.h" 23#include "llvm/Support/LEB128.h" 24#include "llvm/Support/TargetRegistry.h" 25#include "llvm/Support/raw_ostream.h" 26#include <array> 27#include <vector> 28 29using namespace llvm; 30 31#define DEBUG_TYPE "hexagon-disassembler" 32 33// Pull DecodeStatus and its enum values into the global namespace. 34typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 35 36namespace { 37/// \brief Hexagon disassembler for all Hexagon platforms. 38class HexagonDisassembler : public MCDisassembler { 39public: 40 HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx) 41 : MCDisassembler(STI, Ctx) {} 42 43 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 44 ArrayRef<uint8_t> Bytes, uint64_t Address, 45 raw_ostream &VStream, 46 raw_ostream &CStream) const override; 47}; 48} 49 50static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 51 uint64_t Address, const void *Decoder); 52static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 53 uint64_t Address, const void *Decoder); 54static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 55 uint64_t Address, void const *Decoder); 56 57static const uint16_t IntRegDecoderTable[] = { 58 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 59 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9, 60 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14, 61 Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, 62 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, 63 Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29, 64 Hexagon::R30, Hexagon::R31 }; 65 66static const uint16_t PredRegDecoderTable[] = { Hexagon::P0, Hexagon::P1, 67Hexagon::P2, Hexagon::P3 }; 68 69static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo, 70 const uint16_t Table[], size_t Size) { 71 if (RegNo < Size) { 72 Inst.addOperand(MCOperand::CreateReg(Table[RegNo])); 73 return MCDisassembler::Success; 74 } 75 else 76 return MCDisassembler::Fail; 77} 78 79static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 80 uint64_t /*Address*/, 81 void const *Decoder) { 82 if (RegNo > 31) 83 return MCDisassembler::Fail; 84 85 unsigned Register = IntRegDecoderTable[RegNo]; 86 Inst.addOperand(MCOperand::CreateReg(Register)); 87 return MCDisassembler::Success; 88} 89 90static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 91 uint64_t /*Address*/, const void *Decoder) { 92 static const uint16_t CtrlRegDecoderTable[] = { 93 Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1, 94 Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7, 95 Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP, 96 Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH 97 }; 98 99 if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0])) 100 return MCDisassembler::Fail; 101 102 if (CtrlRegDecoderTable[RegNo] == Hexagon::NoRegister) 103 return MCDisassembler::Fail; 104 105 unsigned Register = CtrlRegDecoderTable[RegNo]; 106 Inst.addOperand(MCOperand::CreateReg(Register)); 107 return MCDisassembler::Success; 108} 109 110static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo, 111 uint64_t /*Address*/, void const *Decoder) { 112 static const uint16_t CtrlReg64DecoderTable[] = { 113 Hexagon::C1_0, Hexagon::NoRegister, 114 Hexagon::C3_2, Hexagon::NoRegister, 115 Hexagon::NoRegister, Hexagon::NoRegister, 116 Hexagon::C7_6, Hexagon::NoRegister, 117 Hexagon::C9_8, Hexagon::NoRegister, 118 Hexagon::C11_10, Hexagon::NoRegister, 119 Hexagon::CS, Hexagon::NoRegister, 120 Hexagon::UPC, Hexagon::NoRegister 121 }; 122 123 if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0])) 124 return MCDisassembler::Fail; 125 126 if (CtrlReg64DecoderTable[RegNo] == Hexagon::NoRegister) 127 return MCDisassembler::Fail; 128 129 unsigned Register = CtrlReg64DecoderTable[RegNo]; 130 Inst.addOperand(MCOperand::CreateReg(Register)); 131 return MCDisassembler::Success; 132} 133 134static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo, 135 uint64_t /*Address*/, const void *Decoder) { 136 unsigned Register = 0; 137 switch (RegNo) { 138 case 0: 139 Register = Hexagon::M0; 140 break; 141 case 1: 142 Register = Hexagon::M1; 143 break; 144 default: 145 return MCDisassembler::Fail; 146 } 147 Inst.addOperand(MCOperand::CreateReg(Register)); 148 return MCDisassembler::Success; 149} 150 151static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t /*Address*/, const void *Decoder) { 153 static const uint16_t DoubleRegDecoderTable[] = { 154 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 155 Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7, 156 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11, 157 Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15 158 }; 159 160 return (DecodeRegisterClass(Inst, RegNo >> 1, 161 DoubleRegDecoderTable, 162 sizeof (DoubleRegDecoderTable))); 163} 164 165static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 166 uint64_t /*Address*/, 167 void const *Decoder) { 168 if (RegNo > 3) 169 return MCDisassembler::Fail; 170 171 unsigned Register = PredRegDecoderTable[RegNo]; 172 Inst.addOperand(MCOperand::CreateReg(Register)); 173 return MCDisassembler::Success; 174} 175 176#include "HexagonGenDisassemblerTables.inc" 177 178static MCDisassembler *createHexagonDisassembler(Target const &T, 179 MCSubtargetInfo const &STI, 180 MCContext &Ctx) { 181 return new HexagonDisassembler(STI, Ctx); 182} 183 184extern "C" void LLVMInitializeHexagonDisassembler() { 185 TargetRegistry::RegisterMCDisassembler(TheHexagonTarget, 186 createHexagonDisassembler); 187} 188 189DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 190 ArrayRef<uint8_t> Bytes, 191 uint64_t Address, 192 raw_ostream &os, 193 raw_ostream &cs) const { 194 Size = 4; 195 if (Bytes.size() < 4) 196 return MCDisassembler::Fail; 197 198 uint32_t insn = 199 llvm::support::endian::read<uint32_t, llvm::support::little, 200 llvm::support::unaligned>(Bytes.data()); 201 202 // Remove parse bits. 203 insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK); 204 DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI); 205 HexagonMCInstrInfo::AppendImplicitOperands(MI); 206 return Result; 207} 208