PPCAsmParser.cpp revision 96fb3a25cb0007f06d22d28c0b9c3503798324f6
1//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/PPCMCTargetDesc.h" 11#include "MCTargetDesc/PPCMCExpr.h" 12#include "llvm/MC/MCTargetAsmParser.h" 13#include "llvm/MC/MCStreamer.h" 14#include "llvm/MC/MCExpr.h" 15#include "llvm/MC/MCInst.h" 16#include "llvm/MC/MCRegisterInfo.h" 17#include "llvm/MC/MCSubtargetInfo.h" 18#include "llvm/MC/MCParser/MCAsmLexer.h" 19#include "llvm/MC/MCParser/MCAsmParser.h" 20#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 21#include "llvm/ADT/SmallString.h" 22#include "llvm/ADT/SmallVector.h" 23#include "llvm/ADT/StringSwitch.h" 24#include "llvm/ADT/Twine.h" 25#include "llvm/Support/SourceMgr.h" 26#include "llvm/Support/TargetRegistry.h" 27#include "llvm/Support/raw_ostream.h" 28 29using namespace llvm; 30 31namespace { 32 33static unsigned RRegs[32] = { 34 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 35 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 36 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 37 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 38 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 39 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 40 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 41 PPC::R28, PPC::R29, PPC::R30, PPC::R31 42}; 43static unsigned RRegsNoR0[32] = { 44 PPC::ZERO, 45 PPC::R1, PPC::R2, PPC::R3, 46 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 47 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 48 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 49 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 50 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 51 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 52 PPC::R28, PPC::R29, PPC::R30, PPC::R31 53}; 54static unsigned XRegs[32] = { 55 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 56 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 57 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 58 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 59 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 60 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 61 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 62 PPC::X28, PPC::X29, PPC::X30, PPC::X31 63}; 64static unsigned XRegsNoX0[32] = { 65 PPC::ZERO8, 66 PPC::X1, PPC::X2, PPC::X3, 67 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 68 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 69 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 70 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 71 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 72 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 73 PPC::X28, PPC::X29, PPC::X30, PPC::X31 74}; 75static unsigned FRegs[32] = { 76 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 77 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 78 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 79 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 80 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 81 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 82 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 83 PPC::F28, PPC::F29, PPC::F30, PPC::F31 84}; 85static unsigned VRegs[32] = { 86 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 87 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 88 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 89 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 90 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 91 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 92 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 93 PPC::V28, PPC::V29, PPC::V30, PPC::V31 94}; 95static unsigned CRBITRegs[32] = { 96 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 97 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 98 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 99 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 100 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 101 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 102 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 103 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 104}; 105static unsigned CRRegs[8] = { 106 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 107 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 108}; 109 110struct PPCOperand; 111 112class PPCAsmParser : public MCTargetAsmParser { 113 MCSubtargetInfo &STI; 114 MCAsmParser &Parser; 115 bool IsPPC64; 116 117 MCAsmParser &getParser() const { return Parser; } 118 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 119 120 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 121 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 122 123 bool isPPC64() const { return IsPPC64; } 124 125 bool MatchRegisterName(const AsmToken &Tok, 126 unsigned &RegNo, int64_t &IntVal); 127 128 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 129 130 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 131 PPCMCExpr::VariantKind &Variant); 132 bool ParseExpression(const MCExpr *&EVal); 133 134 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 135 136 bool ParseDirectiveWord(unsigned Size, SMLoc L); 137 bool ParseDirectiveTC(unsigned Size, SMLoc L); 138 139 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 140 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 141 MCStreamer &Out, unsigned &ErrorInfo, 142 bool MatchingInlineAsm); 143 144 void ProcessInstruction(MCInst &Inst, 145 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 146 147 /// @name Auto-generated Match Functions 148 /// { 149 150#define GET_ASSEMBLER_HEADER 151#include "PPCGenAsmMatcher.inc" 152 153 /// } 154 155 156public: 157 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 158 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 159 // Check for 64-bit vs. 32-bit pointer mode. 160 Triple TheTriple(STI.getTargetTriple()); 161 IsPPC64 = TheTriple.getArch() == Triple::ppc64; 162 // Initialize the set of available features. 163 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 164 } 165 166 virtual bool ParseInstruction(ParseInstructionInfo &Info, 167 StringRef Name, SMLoc NameLoc, 168 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 169 170 virtual bool ParseDirective(AsmToken DirectiveID); 171}; 172 173/// PPCOperand - Instances of this class represent a parsed PowerPC machine 174/// instruction. 175struct PPCOperand : public MCParsedAsmOperand { 176 enum KindTy { 177 Token, 178 Immediate, 179 Expression 180 } Kind; 181 182 SMLoc StartLoc, EndLoc; 183 bool IsPPC64; 184 185 struct TokOp { 186 const char *Data; 187 unsigned Length; 188 }; 189 190 struct ImmOp { 191 int64_t Val; 192 }; 193 194 struct ExprOp { 195 const MCExpr *Val; 196 }; 197 198 union { 199 struct TokOp Tok; 200 struct ImmOp Imm; 201 struct ExprOp Expr; 202 }; 203 204 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 205public: 206 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 207 Kind = o.Kind; 208 StartLoc = o.StartLoc; 209 EndLoc = o.EndLoc; 210 IsPPC64 = o.IsPPC64; 211 switch (Kind) { 212 case Token: 213 Tok = o.Tok; 214 break; 215 case Immediate: 216 Imm = o.Imm; 217 break; 218 case Expression: 219 Expr = o.Expr; 220 break; 221 } 222 } 223 224 /// getStartLoc - Get the location of the first token of this operand. 225 SMLoc getStartLoc() const { return StartLoc; } 226 227 /// getEndLoc - Get the location of the last token of this operand. 228 SMLoc getEndLoc() const { return EndLoc; } 229 230 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 231 bool isPPC64() const { return IsPPC64; } 232 233 int64_t getImm() const { 234 assert(Kind == Immediate && "Invalid access!"); 235 return Imm.Val; 236 } 237 238 const MCExpr *getExpr() const { 239 assert(Kind == Expression && "Invalid access!"); 240 return Expr.Val; 241 } 242 243 unsigned getReg() const { 244 assert(isRegNumber() && "Invalid access!"); 245 return (unsigned) Imm.Val; 246 } 247 248 unsigned getCCReg() const { 249 assert(isCCRegNumber() && "Invalid access!"); 250 return (unsigned) Imm.Val; 251 } 252 253 unsigned getCRBitMask() const { 254 assert(isCRBitMask() && "Invalid access!"); 255 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 256 } 257 258 bool isToken() const { return Kind == Token; } 259 bool isImm() const { return Kind == Immediate || Kind == Expression; } 260 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 261 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 262 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 263 bool isU16Imm() const { return Kind == Expression || 264 (Kind == Immediate && isUInt<16>(getImm())); } 265 bool isS16Imm() const { return Kind == Expression || 266 (Kind == Immediate && isInt<16>(getImm())); } 267 bool isS16ImmX4() const { return Kind == Expression || 268 (Kind == Immediate && isInt<16>(getImm()) && 269 (getImm() & 3) == 0); } 270 bool isDirectBr() const { return Kind == Expression || 271 (Kind == Immediate && isInt<26>(getImm()) && 272 (getImm() & 3) == 0); } 273 bool isCondBr() const { return Kind == Expression || 274 (Kind == Immediate && isInt<16>(getImm()) && 275 (getImm() & 3) == 0); } 276 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 277 bool isCCRegNumber() const { return Kind == Immediate && 278 isUInt<3>(getImm()); } 279 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 280 isPowerOf2_32(getImm()); } 281 bool isMem() const { return false; } 282 bool isReg() const { return false; } 283 284 void addRegOperands(MCInst &Inst, unsigned N) const { 285 llvm_unreachable("addRegOperands"); 286 } 287 288 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 289 assert(N == 1 && "Invalid number of operands!"); 290 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); 291 } 292 293 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 294 assert(N == 1 && "Invalid number of operands!"); 295 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); 296 } 297 298 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 299 assert(N == 1 && "Invalid number of operands!"); 300 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); 301 } 302 303 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 304 assert(N == 1 && "Invalid number of operands!"); 305 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); 306 } 307 308 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 309 if (isPPC64()) 310 addRegG8RCOperands(Inst, N); 311 else 312 addRegGPRCOperands(Inst, N); 313 } 314 315 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 316 if (isPPC64()) 317 addRegG8RCNoX0Operands(Inst, N); 318 else 319 addRegGPRCNoR0Operands(Inst, N); 320 } 321 322 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 323 assert(N == 1 && "Invalid number of operands!"); 324 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 325 } 326 327 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 328 assert(N == 1 && "Invalid number of operands!"); 329 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 330 } 331 332 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 333 assert(N == 1 && "Invalid number of operands!"); 334 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); 335 } 336 337 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 338 assert(N == 1 && "Invalid number of operands!"); 339 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getReg()])); 340 } 341 342 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 343 assert(N == 1 && "Invalid number of operands!"); 344 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()])); 345 } 346 347 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 348 assert(N == 1 && "Invalid number of operands!"); 349 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()])); 350 } 351 352 void addImmOperands(MCInst &Inst, unsigned N) const { 353 assert(N == 1 && "Invalid number of operands!"); 354 if (Kind == Immediate) 355 Inst.addOperand(MCOperand::CreateImm(getImm())); 356 else 357 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 358 } 359 360 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 361 assert(N == 1 && "Invalid number of operands!"); 362 if (Kind == Immediate) 363 Inst.addOperand(MCOperand::CreateImm(getImm() / 4)); 364 else 365 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 366 } 367 368 StringRef getToken() const { 369 assert(Kind == Token && "Invalid access!"); 370 return StringRef(Tok.Data, Tok.Length); 371 } 372 373 virtual void print(raw_ostream &OS) const; 374 375 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) { 376 PPCOperand *Op = new PPCOperand(Token); 377 Op->Tok.Data = Str.data(); 378 Op->Tok.Length = Str.size(); 379 Op->StartLoc = S; 380 Op->EndLoc = S; 381 Op->IsPPC64 = IsPPC64; 382 return Op; 383 } 384 385 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 386 PPCOperand *Op = new PPCOperand(Immediate); 387 Op->Imm.Val = Val; 388 Op->StartLoc = S; 389 Op->EndLoc = E; 390 Op->IsPPC64 = IsPPC64; 391 return Op; 392 } 393 394 static PPCOperand *CreateExpr(const MCExpr *Val, 395 SMLoc S, SMLoc E, bool IsPPC64) { 396 PPCOperand *Op = new PPCOperand(Expression); 397 Op->Expr.Val = Val; 398 Op->StartLoc = S; 399 Op->EndLoc = E; 400 Op->IsPPC64 = IsPPC64; 401 return Op; 402 } 403}; 404 405} // end anonymous namespace. 406 407void PPCOperand::print(raw_ostream &OS) const { 408 switch (Kind) { 409 case Token: 410 OS << "'" << getToken() << "'"; 411 break; 412 case Immediate: 413 OS << getImm(); 414 break; 415 case Expression: 416 getExpr()->print(OS); 417 break; 418 } 419} 420 421 422void PPCAsmParser:: 423ProcessInstruction(MCInst &Inst, 424 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 425 switch (Inst.getOpcode()) { 426 case PPC::LAx: { 427 MCInst TmpInst; 428 TmpInst.setOpcode(PPC::LA); 429 TmpInst.addOperand(Inst.getOperand(0)); 430 TmpInst.addOperand(Inst.getOperand(2)); 431 TmpInst.addOperand(Inst.getOperand(1)); 432 Inst = TmpInst; 433 break; 434 } 435 case PPC::SLWI: { 436 MCInst TmpInst; 437 int64_t N = Inst.getOperand(2).getImm(); 438 TmpInst.setOpcode(PPC::RLWINM); 439 TmpInst.addOperand(Inst.getOperand(0)); 440 TmpInst.addOperand(Inst.getOperand(1)); 441 TmpInst.addOperand(MCOperand::CreateImm(N)); 442 TmpInst.addOperand(MCOperand::CreateImm(0)); 443 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 444 Inst = TmpInst; 445 break; 446 } 447 case PPC::SRWI: { 448 MCInst TmpInst; 449 int64_t N = Inst.getOperand(2).getImm(); 450 TmpInst.setOpcode(PPC::RLWINM); 451 TmpInst.addOperand(Inst.getOperand(0)); 452 TmpInst.addOperand(Inst.getOperand(1)); 453 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 454 TmpInst.addOperand(MCOperand::CreateImm(N)); 455 TmpInst.addOperand(MCOperand::CreateImm(31)); 456 Inst = TmpInst; 457 break; 458 } 459 case PPC::SLDI: { 460 MCInst TmpInst; 461 int64_t N = Inst.getOperand(2).getImm(); 462 TmpInst.setOpcode(PPC::RLDICR); 463 TmpInst.addOperand(Inst.getOperand(0)); 464 TmpInst.addOperand(Inst.getOperand(1)); 465 TmpInst.addOperand(MCOperand::CreateImm(N)); 466 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 467 Inst = TmpInst; 468 break; 469 } 470 case PPC::SRDI: { 471 MCInst TmpInst; 472 int64_t N = Inst.getOperand(2).getImm(); 473 TmpInst.setOpcode(PPC::RLDICL); 474 TmpInst.addOperand(Inst.getOperand(0)); 475 TmpInst.addOperand(Inst.getOperand(1)); 476 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 477 TmpInst.addOperand(MCOperand::CreateImm(N)); 478 Inst = TmpInst; 479 break; 480 } 481 } 482} 483 484bool PPCAsmParser:: 485MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 486 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 487 MCStreamer &Out, unsigned &ErrorInfo, 488 bool MatchingInlineAsm) { 489 MCInst Inst; 490 491 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 492 default: break; 493 case Match_Success: 494 // Post-process instructions (typically extended mnemonics) 495 ProcessInstruction(Inst, Operands); 496 Inst.setLoc(IDLoc); 497 Out.EmitInstruction(Inst); 498 return false; 499 case Match_MissingFeature: 500 return Error(IDLoc, "instruction use requires an option to be enabled"); 501 case Match_MnemonicFail: 502 return Error(IDLoc, "unrecognized instruction mnemonic"); 503 case Match_InvalidOperand: { 504 SMLoc ErrorLoc = IDLoc; 505 if (ErrorInfo != ~0U) { 506 if (ErrorInfo >= Operands.size()) 507 return Error(IDLoc, "too few operands for instruction"); 508 509 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc(); 510 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 511 } 512 513 return Error(ErrorLoc, "invalid operand for instruction"); 514 } 515 } 516 517 llvm_unreachable("Implement any new match types added!"); 518} 519 520bool PPCAsmParser:: 521MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { 522 if (Tok.is(AsmToken::Identifier)) { 523 StringRef Name = Tok.getString(); 524 525 if (Name.equals_lower("lr")) { 526 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 527 IntVal = 8; 528 return false; 529 } else if (Name.equals_lower("ctr")) { 530 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 531 IntVal = 9; 532 return false; 533 } else if (Name.substr(0, 1).equals_lower("r") && 534 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 535 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 536 return false; 537 } else if (Name.substr(0, 1).equals_lower("f") && 538 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 539 RegNo = FRegs[IntVal]; 540 return false; 541 } else if (Name.substr(0, 1).equals_lower("v") && 542 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 543 RegNo = VRegs[IntVal]; 544 return false; 545 } else if (Name.substr(0, 2).equals_lower("cr") && 546 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 547 RegNo = CRRegs[IntVal]; 548 return false; 549 } 550 } 551 552 return true; 553} 554 555bool PPCAsmParser:: 556ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 557 const AsmToken &Tok = Parser.getTok(); 558 StartLoc = Tok.getLoc(); 559 EndLoc = Tok.getEndLoc(); 560 RegNo = 0; 561 int64_t IntVal; 562 563 if (!MatchRegisterName(Tok, RegNo, IntVal)) { 564 Parser.Lex(); // Eat identifier token. 565 return false; 566 } 567 568 return Error(StartLoc, "invalid register name"); 569} 570 571/// Extract @l/@ha modifier from expression. Recursively scan 572/// the expression and check for VK_PPC_LO/HI/HA 573/// symbol variants. If all symbols with modifier use the same 574/// variant, return the corresponding PPCMCExpr::VariantKind, 575/// and a modified expression using the default symbol variant. 576/// Otherwise, return NULL. 577const MCExpr *PPCAsmParser:: 578ExtractModifierFromExpr(const MCExpr *E, 579 PPCMCExpr::VariantKind &Variant) { 580 MCContext &Context = getParser().getContext(); 581 Variant = PPCMCExpr::VK_PPC_None; 582 583 switch (E->getKind()) { 584 case MCExpr::Target: 585 case MCExpr::Constant: 586 return 0; 587 588 case MCExpr::SymbolRef: { 589 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 590 591 switch (SRE->getKind()) { 592 case MCSymbolRefExpr::VK_PPC_LO: 593 Variant = PPCMCExpr::VK_PPC_LO; 594 break; 595 case MCSymbolRefExpr::VK_PPC_HI: 596 Variant = PPCMCExpr::VK_PPC_HI; 597 break; 598 case MCSymbolRefExpr::VK_PPC_HA: 599 Variant = PPCMCExpr::VK_PPC_HA; 600 break; 601 case MCSymbolRefExpr::VK_PPC_HIGHER: 602 Variant = PPCMCExpr::VK_PPC_HIGHER; 603 break; 604 case MCSymbolRefExpr::VK_PPC_HIGHERA: 605 Variant = PPCMCExpr::VK_PPC_HIGHERA; 606 break; 607 case MCSymbolRefExpr::VK_PPC_HIGHEST: 608 Variant = PPCMCExpr::VK_PPC_HIGHEST; 609 break; 610 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 611 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 612 break; 613 default: 614 return 0; 615 } 616 617 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context); 618 } 619 620 case MCExpr::Unary: { 621 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 622 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 623 if (!Sub) 624 return 0; 625 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); 626 } 627 628 case MCExpr::Binary: { 629 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 630 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 631 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 632 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 633 634 if (!LHS && !RHS) 635 return 0; 636 637 if (!LHS) LHS = BE->getLHS(); 638 if (!RHS) RHS = BE->getRHS(); 639 640 if (LHSVariant == PPCMCExpr::VK_PPC_None) 641 Variant = RHSVariant; 642 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 643 Variant = LHSVariant; 644 else if (LHSVariant == RHSVariant) 645 Variant = LHSVariant; 646 else 647 return 0; 648 649 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); 650 } 651 } 652 653 llvm_unreachable("Invalid expression kind!"); 654} 655 656/// Parse an expression. This differs from the default "parseExpression" 657/// in that it handles complex @l/@ha modifiers. 658bool PPCAsmParser:: 659ParseExpression(const MCExpr *&EVal) { 660 if (getParser().parseExpression(EVal)) 661 return true; 662 663 PPCMCExpr::VariantKind Variant; 664 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 665 if (E) 666 EVal = PPCMCExpr::Create(Variant, E, getParser().getContext()); 667 668 return false; 669} 670 671bool PPCAsmParser:: 672ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 673 SMLoc S = Parser.getTok().getLoc(); 674 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 675 const MCExpr *EVal; 676 PPCOperand *Op; 677 678 // Attempt to parse the next token as an immediate 679 switch (getLexer().getKind()) { 680 // Special handling for register names. These are interpreted 681 // as immediates corresponding to the register number. 682 case AsmToken::Percent: 683 Parser.Lex(); // Eat the '%'. 684 unsigned RegNo; 685 int64_t IntVal; 686 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 687 Parser.Lex(); // Eat the identifier token. 688 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 689 Operands.push_back(Op); 690 return false; 691 } 692 return Error(S, "invalid register name"); 693 694 // All other expressions 695 case AsmToken::LParen: 696 case AsmToken::Plus: 697 case AsmToken::Minus: 698 case AsmToken::Integer: 699 case AsmToken::Identifier: 700 case AsmToken::Dot: 701 case AsmToken::Dollar: 702 if (!ParseExpression(EVal)) 703 break; 704 /* fall through */ 705 default: 706 return Error(S, "unknown operand"); 707 } 708 709 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(EVal)) 710 Op = PPCOperand::CreateImm(CE->getValue(), S, E, isPPC64()); 711 else 712 Op = PPCOperand::CreateExpr(EVal, S, E, isPPC64()); 713 714 // Push the parsed operand into the list of operands 715 Operands.push_back(Op); 716 717 // Check for D-form memory operands 718 if (getLexer().is(AsmToken::LParen)) { 719 Parser.Lex(); // Eat the '('. 720 S = Parser.getTok().getLoc(); 721 722 int64_t IntVal; 723 switch (getLexer().getKind()) { 724 case AsmToken::Percent: 725 Parser.Lex(); // Eat the '%'. 726 unsigned RegNo; 727 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal)) 728 return Error(S, "invalid register name"); 729 Parser.Lex(); // Eat the identifier token. 730 break; 731 732 case AsmToken::Integer: 733 if (getParser().parseAbsoluteExpression(IntVal) || 734 IntVal < 0 || IntVal > 31) 735 return Error(S, "invalid register number"); 736 break; 737 738 default: 739 return Error(S, "invalid memory operand"); 740 } 741 742 if (getLexer().isNot(AsmToken::RParen)) 743 return Error(Parser.getTok().getLoc(), "missing ')'"); 744 E = Parser.getTok().getLoc(); 745 Parser.Lex(); // Eat the ')'. 746 747 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 748 Operands.push_back(Op); 749 } 750 751 return false; 752} 753 754/// Parse an instruction mnemonic followed by its operands. 755bool PPCAsmParser:: 756ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, 757 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 758 // The first operand is the token for the instruction name. 759 // If the next character is a '+' or '-', we need to add it to the 760 // instruction name, to match what TableGen is doing. 761 if (getLexer().is(AsmToken::Plus)) { 762 getLexer().Lex(); 763 char *NewOpcode = new char[Name.size() + 1]; 764 memcpy(NewOpcode, Name.data(), Name.size()); 765 NewOpcode[Name.size()] = '+'; 766 Name = StringRef(NewOpcode, Name.size() + 1); 767 } 768 if (getLexer().is(AsmToken::Minus)) { 769 getLexer().Lex(); 770 char *NewOpcode = new char[Name.size() + 1]; 771 memcpy(NewOpcode, Name.data(), Name.size()); 772 NewOpcode[Name.size()] = '-'; 773 Name = StringRef(NewOpcode, Name.size() + 1); 774 } 775 // If the instruction ends in a '.', we need to create a separate 776 // token for it, to match what TableGen is doing. 777 size_t Dot = Name.find('.'); 778 StringRef Mnemonic = Name.slice(0, Dot); 779 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 780 if (Dot != StringRef::npos) { 781 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 782 StringRef DotStr = Name.slice(Dot, StringRef::npos); 783 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 784 } 785 786 // If there are no more operands then finish 787 if (getLexer().is(AsmToken::EndOfStatement)) 788 return false; 789 790 // Parse the first operand 791 if (ParseOperand(Operands)) 792 return true; 793 794 while (getLexer().isNot(AsmToken::EndOfStatement) && 795 getLexer().is(AsmToken::Comma)) { 796 // Consume the comma token 797 getLexer().Lex(); 798 799 // Parse the next operand 800 if (ParseOperand(Operands)) 801 return true; 802 } 803 804 return false; 805} 806 807/// ParseDirective parses the PPC specific directives 808bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 809 StringRef IDVal = DirectiveID.getIdentifier(); 810 if (IDVal == ".word") 811 return ParseDirectiveWord(4, DirectiveID.getLoc()); 812 if (IDVal == ".tc") 813 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); 814 return true; 815} 816 817/// ParseDirectiveWord 818/// ::= .word [ expression (, expression)* ] 819bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 820 if (getLexer().isNot(AsmToken::EndOfStatement)) { 821 for (;;) { 822 const MCExpr *Value; 823 if (getParser().parseExpression(Value)) 824 return true; 825 826 getParser().getStreamer().EmitValue(Value, Size); 827 828 if (getLexer().is(AsmToken::EndOfStatement)) 829 break; 830 831 if (getLexer().isNot(AsmToken::Comma)) 832 return Error(L, "unexpected token in directive"); 833 Parser.Lex(); 834 } 835 } 836 837 Parser.Lex(); 838 return false; 839} 840 841/// ParseDirectiveTC 842/// ::= .tc [ symbol (, expression)* ] 843bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) { 844 // Skip TC symbol, which is only used with XCOFF. 845 while (getLexer().isNot(AsmToken::EndOfStatement) 846 && getLexer().isNot(AsmToken::Comma)) 847 Parser.Lex(); 848 if (getLexer().isNot(AsmToken::Comma)) 849 return Error(L, "unexpected token in directive"); 850 Parser.Lex(); 851 852 // Align to word size. 853 getParser().getStreamer().EmitValueToAlignment(Size); 854 855 // Emit expressions. 856 return ParseDirectiveWord(Size, L); 857} 858 859/// Force static initialization. 860extern "C" void LLVMInitializePowerPCAsmParser() { 861 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); 862 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); 863} 864 865#define GET_REGISTER_MATCHER 866#define GET_MATCHER_IMPLEMENTATION 867#include "PPCGenAsmMatcher.inc" 868