PPCAsmParser.cpp revision 9e5bbeab1f6f79375c24bfab87c28f5f4c5afea1 
1//===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/PPCMCTargetDesc.h"
11#include "MCTargetDesc/PPCMCExpr.h"
12#include "llvm/MC/MCTargetAsmParser.h"
13#include "llvm/MC/MCStreamer.h"
14#include "llvm/MC/MCExpr.h"
15#include "llvm/MC/MCInst.h"
16#include "llvm/MC/MCRegisterInfo.h"
17#include "llvm/MC/MCSubtargetInfo.h"
18#include "llvm/MC/MCParser/MCAsmLexer.h"
19#include "llvm/MC/MCParser/MCAsmParser.h"
20#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21#include "llvm/ADT/SmallString.h"
22#include "llvm/ADT/SmallVector.h"
23#include "llvm/ADT/StringSwitch.h"
24#include "llvm/ADT/Twine.h"
25#include "llvm/Support/SourceMgr.h"
26#include "llvm/Support/TargetRegistry.h"
27#include "llvm/Support/raw_ostream.h"
28
29using namespace llvm;
30
31namespace {
32
33static unsigned RRegs[32] = {
34  PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
35  PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
36  PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
37  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
38  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
39  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
40  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
41  PPC::R28, PPC::R29, PPC::R30, PPC::R31
42};
43static unsigned RRegsNoR0[32] = {
44  PPC::ZERO,
45            PPC::R1,  PPC::R2,  PPC::R3,
46  PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
47  PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
48  PPC::R12, PPC::R13, PPC::R14, PPC::R15,
49  PPC::R16, PPC::R17, PPC::R18, PPC::R19,
50  PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51  PPC::R24, PPC::R25, PPC::R26, PPC::R27,
52  PPC::R28, PPC::R29, PPC::R30, PPC::R31
53};
54static unsigned XRegs[32] = {
55  PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
56  PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
57  PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
58  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
59  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
60  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
61  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
62  PPC::X28, PPC::X29, PPC::X30, PPC::X31
63};
64static unsigned XRegsNoX0[32] = {
65  PPC::ZERO8,
66            PPC::X1,  PPC::X2,  PPC::X3,
67  PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
68  PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
69  PPC::X12, PPC::X13, PPC::X14, PPC::X15,
70  PPC::X16, PPC::X17, PPC::X18, PPC::X19,
71  PPC::X20, PPC::X21, PPC::X22, PPC::X23,
72  PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73  PPC::X28, PPC::X29, PPC::X30, PPC::X31
74};
75static unsigned FRegs[32] = {
76  PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
77  PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
78  PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
79  PPC::F12, PPC::F13, PPC::F14, PPC::F15,
80  PPC::F16, PPC::F17, PPC::F18, PPC::F19,
81  PPC::F20, PPC::F21, PPC::F22, PPC::F23,
82  PPC::F24, PPC::F25, PPC::F26, PPC::F27,
83  PPC::F28, PPC::F29, PPC::F30, PPC::F31
84};
85static unsigned VRegs[32] = {
86  PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
87  PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
88  PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
89  PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90  PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91  PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92  PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93  PPC::V28, PPC::V29, PPC::V30, PPC::V31
94};
95static unsigned CRBITRegs[32] = {
96  PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
97  PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
98  PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
99  PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
100  PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
101  PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
102  PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
103  PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
104};
105static unsigned CRRegs[8] = {
106  PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
107  PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
108};
109
110// Evaluate an expression containing condition register
111// or condition register field symbols.  Returns positive
112// value on success, or -1 on error.
113static int64_t
114EvaluateCRExpr(const MCExpr *E) {
115  switch (E->getKind()) {
116  case MCExpr::Target:
117    return -1;
118
119  case MCExpr::Constant: {
120    int64_t Res = cast<MCConstantExpr>(E)->getValue();
121    return Res < 0 ? -1 : Res;
122  }
123
124  case MCExpr::SymbolRef: {
125    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
126    StringRef Name = SRE->getSymbol().getName();
127
128    if (Name == "lt") return 0;
129    if (Name == "gt") return 1;
130    if (Name == "eq") return 2;
131    if (Name == "so") return 3;
132    if (Name == "un") return 3;
133
134    if (Name == "cr0") return 0;
135    if (Name == "cr1") return 1;
136    if (Name == "cr2") return 2;
137    if (Name == "cr3") return 3;
138    if (Name == "cr4") return 4;
139    if (Name == "cr5") return 5;
140    if (Name == "cr6") return 6;
141    if (Name == "cr7") return 7;
142
143    return -1;
144  }
145
146  case MCExpr::Unary:
147    return -1;
148
149  case MCExpr::Binary: {
150    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
151    int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
152    int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
153    int64_t Res;
154
155    if (LHSVal < 0 || RHSVal < 0)
156      return -1;
157
158    switch (BE->getOpcode()) {
159    default: return -1;
160    case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
161    case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
162    }
163
164    return Res < 0 ? -1 : Res;
165  }
166  }
167
168  llvm_unreachable("Invalid expression kind!");
169}
170
171struct PPCOperand;
172
173class PPCAsmParser : public MCTargetAsmParser {
174  MCSubtargetInfo &STI;
175  MCAsmParser &Parser;
176  bool IsPPC64;
177
178  MCAsmParser &getParser() const { return Parser; }
179  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
180
181  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
182  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
183
184  bool isPPC64() const { return IsPPC64; }
185
186  bool MatchRegisterName(const AsmToken &Tok,
187                         unsigned &RegNo, int64_t &IntVal);
188
189  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
190
191  const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
192                                        PPCMCExpr::VariantKind &Variant);
193  bool ParseExpression(const MCExpr *&EVal);
194
195  bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
196
197  bool ParseDirectiveWord(unsigned Size, SMLoc L);
198  bool ParseDirectiveTC(unsigned Size, SMLoc L);
199
200  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
201                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
202                               MCStreamer &Out, unsigned &ErrorInfo,
203                               bool MatchingInlineAsm);
204
205  void ProcessInstruction(MCInst &Inst,
206                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
207
208  /// @name Auto-generated Match Functions
209  /// {
210
211#define GET_ASSEMBLER_HEADER
212#include "PPCGenAsmMatcher.inc"
213
214  /// }
215
216
217public:
218  PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
219    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
220    // Check for 64-bit vs. 32-bit pointer mode.
221    Triple TheTriple(STI.getTargetTriple());
222    IsPPC64 = TheTriple.getArch() == Triple::ppc64;
223    // Initialize the set of available features.
224    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
225  }
226
227  virtual bool ParseInstruction(ParseInstructionInfo &Info,
228                                StringRef Name, SMLoc NameLoc,
229                                SmallVectorImpl<MCParsedAsmOperand*> &Operands);
230
231  virtual bool ParseDirective(AsmToken DirectiveID);
232
233  unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
234};
235
236/// PPCOperand - Instances of this class represent a parsed PowerPC machine
237/// instruction.
238struct PPCOperand : public MCParsedAsmOperand {
239  enum KindTy {
240    Token,
241    Immediate,
242    Expression,
243    TLSRegister
244  } Kind;
245
246  SMLoc StartLoc, EndLoc;
247  bool IsPPC64;
248
249  struct TokOp {
250    const char *Data;
251    unsigned Length;
252  };
253
254  struct ImmOp {
255    int64_t Val;
256  };
257
258  struct ExprOp {
259    const MCExpr *Val;
260    int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
261  };
262
263  struct TLSRegOp {
264    const MCSymbolRefExpr *Sym;
265  };
266
267  union {
268    struct TokOp Tok;
269    struct ImmOp Imm;
270    struct ExprOp Expr;
271    struct TLSRegOp TLSReg;
272  };
273
274  PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
275public:
276  PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
277    Kind = o.Kind;
278    StartLoc = o.StartLoc;
279    EndLoc = o.EndLoc;
280    IsPPC64 = o.IsPPC64;
281    switch (Kind) {
282    case Token:
283      Tok = o.Tok;
284      break;
285    case Immediate:
286      Imm = o.Imm;
287      break;
288    case Expression:
289      Expr = o.Expr;
290      break;
291    case TLSRegister:
292      TLSReg = o.TLSReg;
293      break;
294    }
295  }
296
297  /// getStartLoc - Get the location of the first token of this operand.
298  SMLoc getStartLoc() const { return StartLoc; }
299
300  /// getEndLoc - Get the location of the last token of this operand.
301  SMLoc getEndLoc() const { return EndLoc; }
302
303  /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
304  bool isPPC64() const { return IsPPC64; }
305
306  int64_t getImm() const {
307    assert(Kind == Immediate && "Invalid access!");
308    return Imm.Val;
309  }
310
311  const MCExpr *getExpr() const {
312    assert(Kind == Expression && "Invalid access!");
313    return Expr.Val;
314  }
315
316  int64_t getExprCRVal() const {
317    assert(Kind == Expression && "Invalid access!");
318    return Expr.CRVal;
319  }
320
321  const MCExpr *getTLSReg() const {
322    assert(Kind == TLSRegister && "Invalid access!");
323    return TLSReg.Sym;
324  }
325
326  unsigned getReg() const {
327    assert(isRegNumber() && "Invalid access!");
328    return (unsigned) Imm.Val;
329  }
330
331  unsigned getCCReg() const {
332    assert(isCCRegNumber() && "Invalid access!");
333    return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
334  }
335
336  unsigned getCRBit() const {
337    assert(isCRBitNumber() && "Invalid access!");
338    return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
339  }
340
341  unsigned getCRBitMask() const {
342    assert(isCRBitMask() && "Invalid access!");
343    return 7 - countTrailingZeros<uint64_t>(Imm.Val);
344  }
345
346  bool isToken() const { return Kind == Token; }
347  bool isImm() const { return Kind == Immediate || Kind == Expression; }
348  bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
349  bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
350  bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
351  bool isU16Imm() const { return Kind == Expression ||
352                                 (Kind == Immediate && isUInt<16>(getImm())); }
353  bool isS16Imm() const { return Kind == Expression ||
354                                 (Kind == Immediate && isInt<16>(getImm())); }
355  bool isS16ImmX4() const { return Kind == Expression ||
356                                   (Kind == Immediate && isInt<16>(getImm()) &&
357                                    (getImm() & 3) == 0); }
358  bool isS17Imm() const { return Kind == Expression ||
359                                 (Kind == Immediate && isInt<17>(getImm())); }
360  bool isTLSReg() const { return Kind == TLSRegister; }
361  bool isDirectBr() const { return Kind == Expression ||
362                                   (Kind == Immediate && isInt<26>(getImm()) &&
363                                    (getImm() & 3) == 0); }
364  bool isCondBr() const { return Kind == Expression ||
365                                 (Kind == Immediate && isInt<16>(getImm()) &&
366                                  (getImm() & 3) == 0); }
367  bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
368  bool isCCRegNumber() const { return (Kind == Expression
369                                       && isUInt<3>(getExprCRVal())) ||
370                                      (Kind == Immediate
371                                       && isUInt<3>(getImm())); }
372  bool isCRBitNumber() const { return (Kind == Expression
373                                       && isUInt<5>(getExprCRVal())) ||
374                                      (Kind == Immediate
375                                       && isUInt<5>(getImm())); }
376  bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
377                                    isPowerOf2_32(getImm()); }
378  bool isMem() const { return false; }
379  bool isReg() const { return false; }
380
381  void addRegOperands(MCInst &Inst, unsigned N) const {
382    llvm_unreachable("addRegOperands");
383  }
384
385  void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
386    assert(N == 1 && "Invalid number of operands!");
387    Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
388  }
389
390  void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
391    assert(N == 1 && "Invalid number of operands!");
392    Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
393  }
394
395  void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
396    assert(N == 1 && "Invalid number of operands!");
397    Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
398  }
399
400  void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
401    assert(N == 1 && "Invalid number of operands!");
402    Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
403  }
404
405  void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
406    if (isPPC64())
407      addRegG8RCOperands(Inst, N);
408    else
409      addRegGPRCOperands(Inst, N);
410  }
411
412  void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
413    if (isPPC64())
414      addRegG8RCNoX0Operands(Inst, N);
415    else
416      addRegGPRCNoR0Operands(Inst, N);
417  }
418
419  void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
420    assert(N == 1 && "Invalid number of operands!");
421    Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
422  }
423
424  void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
425    assert(N == 1 && "Invalid number of operands!");
426    Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
427  }
428
429  void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
430    assert(N == 1 && "Invalid number of operands!");
431    Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
432  }
433
434  void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
435    assert(N == 1 && "Invalid number of operands!");
436    Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
437  }
438
439  void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
440    assert(N == 1 && "Invalid number of operands!");
441    Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
442  }
443
444  void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
445    assert(N == 1 && "Invalid number of operands!");
446    Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
447  }
448
449  void addImmOperands(MCInst &Inst, unsigned N) const {
450    assert(N == 1 && "Invalid number of operands!");
451    if (Kind == Immediate)
452      Inst.addOperand(MCOperand::CreateImm(getImm()));
453    else
454      Inst.addOperand(MCOperand::CreateExpr(getExpr()));
455  }
456
457  void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
458    assert(N == 1 && "Invalid number of operands!");
459    if (Kind == Immediate)
460      Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
461    else
462      Inst.addOperand(MCOperand::CreateExpr(getExpr()));
463  }
464
465  void addTLSRegOperands(MCInst &Inst, unsigned N) const {
466    assert(N == 1 && "Invalid number of operands!");
467    Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
468  }
469
470  StringRef getToken() const {
471    assert(Kind == Token && "Invalid access!");
472    return StringRef(Tok.Data, Tok.Length);
473  }
474
475  virtual void print(raw_ostream &OS) const;
476
477  static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
478    PPCOperand *Op = new PPCOperand(Token);
479    Op->Tok.Data = Str.data();
480    Op->Tok.Length = Str.size();
481    Op->StartLoc = S;
482    Op->EndLoc = S;
483    Op->IsPPC64 = IsPPC64;
484    return Op;
485  }
486
487  static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
488    PPCOperand *Op = new PPCOperand(Immediate);
489    Op->Imm.Val = Val;
490    Op->StartLoc = S;
491    Op->EndLoc = E;
492    Op->IsPPC64 = IsPPC64;
493    return Op;
494  }
495
496  static PPCOperand *CreateExpr(const MCExpr *Val,
497                                SMLoc S, SMLoc E, bool IsPPC64) {
498    PPCOperand *Op = new PPCOperand(Expression);
499    Op->Expr.Val = Val;
500    Op->Expr.CRVal = EvaluateCRExpr(Val);
501    Op->StartLoc = S;
502    Op->EndLoc = E;
503    Op->IsPPC64 = IsPPC64;
504    return Op;
505  }
506
507  static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
508                                  SMLoc S, SMLoc E, bool IsPPC64) {
509    PPCOperand *Op = new PPCOperand(TLSRegister);
510    Op->TLSReg.Sym = Sym;
511    Op->StartLoc = S;
512    Op->EndLoc = E;
513    Op->IsPPC64 = IsPPC64;
514    return Op;
515  }
516
517  static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
518                                      SMLoc S, SMLoc E, bool IsPPC64) {
519    if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
520      return CreateImm(CE->getValue(), S, E, IsPPC64);
521
522    if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
523      if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
524        return CreateTLSReg(SRE, S, E, IsPPC64);
525
526    return CreateExpr(Val, S, E, IsPPC64);
527  }
528};
529
530} // end anonymous namespace.
531
532void PPCOperand::print(raw_ostream &OS) const {
533  switch (Kind) {
534  case Token:
535    OS << "'" << getToken() << "'";
536    break;
537  case Immediate:
538    OS << getImm();
539    break;
540  case Expression:
541    getExpr()->print(OS);
542    break;
543  case TLSRegister:
544    getTLSReg()->print(OS);
545    break;
546  }
547}
548
549
550void PPCAsmParser::
551ProcessInstruction(MCInst &Inst,
552                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
553  int Opcode = Inst.getOpcode();
554  switch (Opcode) {
555  case PPC::LAx: {
556    MCInst TmpInst;
557    TmpInst.setOpcode(PPC::LA);
558    TmpInst.addOperand(Inst.getOperand(0));
559    TmpInst.addOperand(Inst.getOperand(2));
560    TmpInst.addOperand(Inst.getOperand(1));
561    Inst = TmpInst;
562    break;
563  }
564  case PPC::SUBI: {
565    MCInst TmpInst;
566    int64_t N = Inst.getOperand(2).getImm();
567    TmpInst.setOpcode(PPC::ADDI);
568    TmpInst.addOperand(Inst.getOperand(0));
569    TmpInst.addOperand(Inst.getOperand(1));
570    TmpInst.addOperand(MCOperand::CreateImm(-N));
571    Inst = TmpInst;
572    break;
573  }
574  case PPC::SUBIS: {
575    MCInst TmpInst;
576    int64_t N = Inst.getOperand(2).getImm();
577    TmpInst.setOpcode(PPC::ADDIS);
578    TmpInst.addOperand(Inst.getOperand(0));
579    TmpInst.addOperand(Inst.getOperand(1));
580    TmpInst.addOperand(MCOperand::CreateImm(-N));
581    Inst = TmpInst;
582    break;
583  }
584  case PPC::SUBIC: {
585    MCInst TmpInst;
586    int64_t N = Inst.getOperand(2).getImm();
587    TmpInst.setOpcode(PPC::ADDIC);
588    TmpInst.addOperand(Inst.getOperand(0));
589    TmpInst.addOperand(Inst.getOperand(1));
590    TmpInst.addOperand(MCOperand::CreateImm(-N));
591    Inst = TmpInst;
592    break;
593  }
594  case PPC::SUBICo: {
595    MCInst TmpInst;
596    int64_t N = Inst.getOperand(2).getImm();
597    TmpInst.setOpcode(PPC::ADDICo);
598    TmpInst.addOperand(Inst.getOperand(0));
599    TmpInst.addOperand(Inst.getOperand(1));
600    TmpInst.addOperand(MCOperand::CreateImm(-N));
601    Inst = TmpInst;
602    break;
603  }
604  case PPC::EXTLWI:
605  case PPC::EXTLWIo: {
606    MCInst TmpInst;
607    int64_t N = Inst.getOperand(2).getImm();
608    int64_t B = Inst.getOperand(3).getImm();
609    TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
610    TmpInst.addOperand(Inst.getOperand(0));
611    TmpInst.addOperand(Inst.getOperand(1));
612    TmpInst.addOperand(MCOperand::CreateImm(B));
613    TmpInst.addOperand(MCOperand::CreateImm(0));
614    TmpInst.addOperand(MCOperand::CreateImm(N - 1));
615    Inst = TmpInst;
616    break;
617  }
618  case PPC::EXTRWI:
619  case PPC::EXTRWIo: {
620    MCInst TmpInst;
621    int64_t N = Inst.getOperand(2).getImm();
622    int64_t B = Inst.getOperand(3).getImm();
623    TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
624    TmpInst.addOperand(Inst.getOperand(0));
625    TmpInst.addOperand(Inst.getOperand(1));
626    TmpInst.addOperand(MCOperand::CreateImm(B + N));
627    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
628    TmpInst.addOperand(MCOperand::CreateImm(31));
629    Inst = TmpInst;
630    break;
631  }
632  case PPC::INSLWI:
633  case PPC::INSLWIo: {
634    MCInst TmpInst;
635    int64_t N = Inst.getOperand(2).getImm();
636    int64_t B = Inst.getOperand(3).getImm();
637    TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
638    TmpInst.addOperand(Inst.getOperand(0));
639    TmpInst.addOperand(Inst.getOperand(0));
640    TmpInst.addOperand(Inst.getOperand(1));
641    TmpInst.addOperand(MCOperand::CreateImm(32 - B));
642    TmpInst.addOperand(MCOperand::CreateImm(B));
643    TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
644    Inst = TmpInst;
645    break;
646  }
647  case PPC::INSRWI:
648  case PPC::INSRWIo: {
649    MCInst TmpInst;
650    int64_t N = Inst.getOperand(2).getImm();
651    int64_t B = Inst.getOperand(3).getImm();
652    TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
653    TmpInst.addOperand(Inst.getOperand(0));
654    TmpInst.addOperand(Inst.getOperand(0));
655    TmpInst.addOperand(Inst.getOperand(1));
656    TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
657    TmpInst.addOperand(MCOperand::CreateImm(B));
658    TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
659    Inst = TmpInst;
660    break;
661  }
662  case PPC::ROTRWI:
663  case PPC::ROTRWIo: {
664    MCInst TmpInst;
665    int64_t N = Inst.getOperand(2).getImm();
666    TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
667    TmpInst.addOperand(Inst.getOperand(0));
668    TmpInst.addOperand(Inst.getOperand(1));
669    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
670    TmpInst.addOperand(MCOperand::CreateImm(0));
671    TmpInst.addOperand(MCOperand::CreateImm(31));
672    Inst = TmpInst;
673    break;
674  }
675  case PPC::SLWI:
676  case PPC::SLWIo: {
677    MCInst TmpInst;
678    int64_t N = Inst.getOperand(2).getImm();
679    TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
680    TmpInst.addOperand(Inst.getOperand(0));
681    TmpInst.addOperand(Inst.getOperand(1));
682    TmpInst.addOperand(MCOperand::CreateImm(N));
683    TmpInst.addOperand(MCOperand::CreateImm(0));
684    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
685    Inst = TmpInst;
686    break;
687  }
688  case PPC::SRWI:
689  case PPC::SRWIo: {
690    MCInst TmpInst;
691    int64_t N = Inst.getOperand(2).getImm();
692    TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
693    TmpInst.addOperand(Inst.getOperand(0));
694    TmpInst.addOperand(Inst.getOperand(1));
695    TmpInst.addOperand(MCOperand::CreateImm(32 - N));
696    TmpInst.addOperand(MCOperand::CreateImm(N));
697    TmpInst.addOperand(MCOperand::CreateImm(31));
698    Inst = TmpInst;
699    break;
700  }
701  case PPC::CLRRWI:
702  case PPC::CLRRWIo: {
703    MCInst TmpInst;
704    int64_t N = Inst.getOperand(2).getImm();
705    TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
706    TmpInst.addOperand(Inst.getOperand(0));
707    TmpInst.addOperand(Inst.getOperand(1));
708    TmpInst.addOperand(MCOperand::CreateImm(0));
709    TmpInst.addOperand(MCOperand::CreateImm(0));
710    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
711    Inst = TmpInst;
712    break;
713  }
714  case PPC::CLRLSLWI:
715  case PPC::CLRLSLWIo: {
716    MCInst TmpInst;
717    int64_t B = Inst.getOperand(2).getImm();
718    int64_t N = Inst.getOperand(3).getImm();
719    TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
720    TmpInst.addOperand(Inst.getOperand(0));
721    TmpInst.addOperand(Inst.getOperand(1));
722    TmpInst.addOperand(MCOperand::CreateImm(N));
723    TmpInst.addOperand(MCOperand::CreateImm(B - N));
724    TmpInst.addOperand(MCOperand::CreateImm(31 - N));
725    Inst = TmpInst;
726    break;
727  }
728  case PPC::EXTLDI:
729  case PPC::EXTLDIo: {
730    MCInst TmpInst;
731    int64_t N = Inst.getOperand(2).getImm();
732    int64_t B = Inst.getOperand(3).getImm();
733    TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
734    TmpInst.addOperand(Inst.getOperand(0));
735    TmpInst.addOperand(Inst.getOperand(1));
736    TmpInst.addOperand(MCOperand::CreateImm(B));
737    TmpInst.addOperand(MCOperand::CreateImm(N - 1));
738    Inst = TmpInst;
739    break;
740  }
741  case PPC::EXTRDI:
742  case PPC::EXTRDIo: {
743    MCInst TmpInst;
744    int64_t N = Inst.getOperand(2).getImm();
745    int64_t B = Inst.getOperand(3).getImm();
746    TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
747    TmpInst.addOperand(Inst.getOperand(0));
748    TmpInst.addOperand(Inst.getOperand(1));
749    TmpInst.addOperand(MCOperand::CreateImm(B + N));
750    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
751    Inst = TmpInst;
752    break;
753  }
754  case PPC::INSRDI:
755  case PPC::INSRDIo: {
756    MCInst TmpInst;
757    int64_t N = Inst.getOperand(2).getImm();
758    int64_t B = Inst.getOperand(3).getImm();
759    TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
760    TmpInst.addOperand(Inst.getOperand(0));
761    TmpInst.addOperand(Inst.getOperand(0));
762    TmpInst.addOperand(Inst.getOperand(1));
763    TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
764    TmpInst.addOperand(MCOperand::CreateImm(B));
765    Inst = TmpInst;
766    break;
767  }
768  case PPC::ROTRDI:
769  case PPC::ROTRDIo: {
770    MCInst TmpInst;
771    int64_t N = Inst.getOperand(2).getImm();
772    TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
773    TmpInst.addOperand(Inst.getOperand(0));
774    TmpInst.addOperand(Inst.getOperand(1));
775    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
776    TmpInst.addOperand(MCOperand::CreateImm(0));
777    Inst = TmpInst;
778    break;
779  }
780  case PPC::SLDI:
781  case PPC::SLDIo: {
782    MCInst TmpInst;
783    int64_t N = Inst.getOperand(2).getImm();
784    TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
785    TmpInst.addOperand(Inst.getOperand(0));
786    TmpInst.addOperand(Inst.getOperand(1));
787    TmpInst.addOperand(MCOperand::CreateImm(N));
788    TmpInst.addOperand(MCOperand::CreateImm(63 - N));
789    Inst = TmpInst;
790    break;
791  }
792  case PPC::SRDI:
793  case PPC::SRDIo: {
794    MCInst TmpInst;
795    int64_t N = Inst.getOperand(2).getImm();
796    TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
797    TmpInst.addOperand(Inst.getOperand(0));
798    TmpInst.addOperand(Inst.getOperand(1));
799    TmpInst.addOperand(MCOperand::CreateImm(64 - N));
800    TmpInst.addOperand(MCOperand::CreateImm(N));
801    Inst = TmpInst;
802    break;
803  }
804  case PPC::CLRRDI:
805  case PPC::CLRRDIo: {
806    MCInst TmpInst;
807    int64_t N = Inst.getOperand(2).getImm();
808    TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
809    TmpInst.addOperand(Inst.getOperand(0));
810    TmpInst.addOperand(Inst.getOperand(1));
811    TmpInst.addOperand(MCOperand::CreateImm(0));
812    TmpInst.addOperand(MCOperand::CreateImm(63 - N));
813    Inst = TmpInst;
814    break;
815  }
816  case PPC::CLRLSLDI:
817  case PPC::CLRLSLDIo: {
818    MCInst TmpInst;
819    int64_t B = Inst.getOperand(2).getImm();
820    int64_t N = Inst.getOperand(3).getImm();
821    TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
822    TmpInst.addOperand(Inst.getOperand(0));
823    TmpInst.addOperand(Inst.getOperand(1));
824    TmpInst.addOperand(MCOperand::CreateImm(N));
825    TmpInst.addOperand(MCOperand::CreateImm(B - N));
826    Inst = TmpInst;
827    break;
828  }
829  }
830}
831
832bool PPCAsmParser::
833MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
834                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
835                        MCStreamer &Out, unsigned &ErrorInfo,
836                        bool MatchingInlineAsm) {
837  MCInst Inst;
838
839  switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
840  default: break;
841  case Match_Success:
842    // Post-process instructions (typically extended mnemonics)
843    ProcessInstruction(Inst, Operands);
844    Inst.setLoc(IDLoc);
845    Out.EmitInstruction(Inst);
846    return false;
847  case Match_MissingFeature:
848    return Error(IDLoc, "instruction use requires an option to be enabled");
849  case Match_MnemonicFail:
850      return Error(IDLoc, "unrecognized instruction mnemonic");
851  case Match_InvalidOperand: {
852    SMLoc ErrorLoc = IDLoc;
853    if (ErrorInfo != ~0U) {
854      if (ErrorInfo >= Operands.size())
855        return Error(IDLoc, "too few operands for instruction");
856
857      ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
858      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
859    }
860
861    return Error(ErrorLoc, "invalid operand for instruction");
862  }
863  }
864
865  llvm_unreachable("Implement any new match types added!");
866}
867
868bool PPCAsmParser::
869MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
870  if (Tok.is(AsmToken::Identifier)) {
871    StringRef Name = Tok.getString();
872
873    if (Name.equals_lower("lr")) {
874      RegNo = isPPC64()? PPC::LR8 : PPC::LR;
875      IntVal = 8;
876      return false;
877    } else if (Name.equals_lower("ctr")) {
878      RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
879      IntVal = 9;
880      return false;
881    } else if (Name.equals_lower("vrsave")) {
882      RegNo = PPC::VRSAVE;
883      IntVal = 256;
884      return false;
885    } else if (Name.substr(0, 1).equals_lower("r") &&
886               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
887      RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
888      return false;
889    } else if (Name.substr(0, 1).equals_lower("f") &&
890               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
891      RegNo = FRegs[IntVal];
892      return false;
893    } else if (Name.substr(0, 1).equals_lower("v") &&
894               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
895      RegNo = VRegs[IntVal];
896      return false;
897    } else if (Name.substr(0, 2).equals_lower("cr") &&
898               !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
899      RegNo = CRRegs[IntVal];
900      return false;
901    }
902  }
903
904  return true;
905}
906
907bool PPCAsmParser::
908ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
909  const AsmToken &Tok = Parser.getTok();
910  StartLoc = Tok.getLoc();
911  EndLoc = Tok.getEndLoc();
912  RegNo = 0;
913  int64_t IntVal;
914
915  if (!MatchRegisterName(Tok, RegNo, IntVal)) {
916    Parser.Lex(); // Eat identifier token.
917    return false;
918  }
919
920  return Error(StartLoc, "invalid register name");
921}
922
923/// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
924/// the expression and check for VK_PPC_LO/HI/HA
925/// symbol variants.  If all symbols with modifier use the same
926/// variant, return the corresponding PPCMCExpr::VariantKind,
927/// and a modified expression using the default symbol variant.
928/// Otherwise, return NULL.
929const MCExpr *PPCAsmParser::
930ExtractModifierFromExpr(const MCExpr *E,
931                        PPCMCExpr::VariantKind &Variant) {
932  MCContext &Context = getParser().getContext();
933  Variant = PPCMCExpr::VK_PPC_None;
934
935  switch (E->getKind()) {
936  case MCExpr::Target:
937  case MCExpr::Constant:
938    return 0;
939
940  case MCExpr::SymbolRef: {
941    const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
942
943    switch (SRE->getKind()) {
944    case MCSymbolRefExpr::VK_PPC_LO:
945      Variant = PPCMCExpr::VK_PPC_LO;
946      break;
947    case MCSymbolRefExpr::VK_PPC_HI:
948      Variant = PPCMCExpr::VK_PPC_HI;
949      break;
950    case MCSymbolRefExpr::VK_PPC_HA:
951      Variant = PPCMCExpr::VK_PPC_HA;
952      break;
953    case MCSymbolRefExpr::VK_PPC_HIGHER:
954      Variant = PPCMCExpr::VK_PPC_HIGHER;
955      break;
956    case MCSymbolRefExpr::VK_PPC_HIGHERA:
957      Variant = PPCMCExpr::VK_PPC_HIGHERA;
958      break;
959    case MCSymbolRefExpr::VK_PPC_HIGHEST:
960      Variant = PPCMCExpr::VK_PPC_HIGHEST;
961      break;
962    case MCSymbolRefExpr::VK_PPC_HIGHESTA:
963      Variant = PPCMCExpr::VK_PPC_HIGHESTA;
964      break;
965    default:
966      return 0;
967    }
968
969    return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
970  }
971
972  case MCExpr::Unary: {
973    const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
974    const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
975    if (!Sub)
976      return 0;
977    return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
978  }
979
980  case MCExpr::Binary: {
981    const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
982    PPCMCExpr::VariantKind LHSVariant, RHSVariant;
983    const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
984    const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
985
986    if (!LHS && !RHS)
987      return 0;
988
989    if (!LHS) LHS = BE->getLHS();
990    if (!RHS) RHS = BE->getRHS();
991
992    if (LHSVariant == PPCMCExpr::VK_PPC_None)
993      Variant = RHSVariant;
994    else if (RHSVariant == PPCMCExpr::VK_PPC_None)
995      Variant = LHSVariant;
996    else if (LHSVariant == RHSVariant)
997      Variant = LHSVariant;
998    else
999      return 0;
1000
1001    return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1002  }
1003  }
1004
1005  llvm_unreachable("Invalid expression kind!");
1006}
1007
1008/// Parse an expression.  This differs from the default "parseExpression"
1009/// in that it handles complex \code @l/@ha \endcode modifiers.
1010bool PPCAsmParser::
1011ParseExpression(const MCExpr *&EVal) {
1012  if (getParser().parseExpression(EVal))
1013    return true;
1014
1015  PPCMCExpr::VariantKind Variant;
1016  const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1017  if (E)
1018    EVal = PPCMCExpr::Create(Variant, E, getParser().getContext());
1019
1020  return false;
1021}
1022
1023bool PPCAsmParser::
1024ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1025  SMLoc S = Parser.getTok().getLoc();
1026  SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1027  const MCExpr *EVal;
1028  PPCOperand *Op;
1029
1030  // Attempt to parse the next token as an immediate
1031  switch (getLexer().getKind()) {
1032  // Special handling for register names.  These are interpreted
1033  // as immediates corresponding to the register number.
1034  case AsmToken::Percent:
1035    Parser.Lex(); // Eat the '%'.
1036    unsigned RegNo;
1037    int64_t IntVal;
1038    if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1039      Parser.Lex(); // Eat the identifier token.
1040      Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1041      Operands.push_back(Op);
1042      return false;
1043    }
1044    return Error(S, "invalid register name");
1045
1046  // All other expressions
1047  case AsmToken::LParen:
1048  case AsmToken::Plus:
1049  case AsmToken::Minus:
1050  case AsmToken::Integer:
1051  case AsmToken::Identifier:
1052  case AsmToken::Dot:
1053  case AsmToken::Dollar:
1054    if (!ParseExpression(EVal))
1055      break;
1056    /* fall through */
1057  default:
1058    return Error(S, "unknown operand");
1059  }
1060
1061  // Push the parsed operand into the list of operands
1062  Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1063  Operands.push_back(Op);
1064
1065  // Check whether this is a TLS call expression
1066  bool TLSCall = false;
1067  if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1068    TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1069
1070  if (TLSCall && getLexer().is(AsmToken::LParen)) {
1071    const MCExpr *TLSSym;
1072
1073    Parser.Lex(); // Eat the '('.
1074    S = Parser.getTok().getLoc();
1075    if (ParseExpression(TLSSym))
1076      return Error(S, "invalid TLS call expression");
1077    if (getLexer().isNot(AsmToken::RParen))
1078      return Error(Parser.getTok().getLoc(), "missing ')'");
1079    E = Parser.getTok().getLoc();
1080    Parser.Lex(); // Eat the ')'.
1081
1082    Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1083    Operands.push_back(Op);
1084  }
1085
1086  // Otherwise, check for D-form memory operands
1087  if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1088    Parser.Lex(); // Eat the '('.
1089    S = Parser.getTok().getLoc();
1090
1091    int64_t IntVal;
1092    switch (getLexer().getKind()) {
1093    case AsmToken::Percent:
1094      Parser.Lex(); // Eat the '%'.
1095      unsigned RegNo;
1096      if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1097        return Error(S, "invalid register name");
1098      Parser.Lex(); // Eat the identifier token.
1099      break;
1100
1101    case AsmToken::Integer:
1102      if (getParser().parseAbsoluteExpression(IntVal) ||
1103          IntVal < 0 || IntVal > 31)
1104        return Error(S, "invalid register number");
1105      break;
1106
1107    default:
1108      return Error(S, "invalid memory operand");
1109    }
1110
1111    if (getLexer().isNot(AsmToken::RParen))
1112      return Error(Parser.getTok().getLoc(), "missing ')'");
1113    E = Parser.getTok().getLoc();
1114    Parser.Lex(); // Eat the ')'.
1115
1116    Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1117    Operands.push_back(Op);
1118  }
1119
1120  return false;
1121}
1122
1123/// Parse an instruction mnemonic followed by its operands.
1124bool PPCAsmParser::
1125ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1126                 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1127  // The first operand is the token for the instruction name.
1128  // If the next character is a '+' or '-', we need to add it to the
1129  // instruction name, to match what TableGen is doing.
1130  if (getLexer().is(AsmToken::Plus)) {
1131    getLexer().Lex();
1132    char *NewOpcode = new char[Name.size() + 1];
1133    memcpy(NewOpcode, Name.data(), Name.size());
1134    NewOpcode[Name.size()] = '+';
1135    Name = StringRef(NewOpcode, Name.size() + 1);
1136  }
1137  if (getLexer().is(AsmToken::Minus)) {
1138    getLexer().Lex();
1139    char *NewOpcode = new char[Name.size() + 1];
1140    memcpy(NewOpcode, Name.data(), Name.size());
1141    NewOpcode[Name.size()] = '-';
1142    Name = StringRef(NewOpcode, Name.size() + 1);
1143  }
1144  // If the instruction ends in a '.', we need to create a separate
1145  // token for it, to match what TableGen is doing.
1146  size_t Dot = Name.find('.');
1147  StringRef Mnemonic = Name.slice(0, Dot);
1148  Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1149  if (Dot != StringRef::npos) {
1150    SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1151    StringRef DotStr = Name.slice(Dot, StringRef::npos);
1152    Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1153  }
1154
1155  // If there are no more operands then finish
1156  if (getLexer().is(AsmToken::EndOfStatement))
1157    return false;
1158
1159  // Parse the first operand
1160  if (ParseOperand(Operands))
1161    return true;
1162
1163  while (getLexer().isNot(AsmToken::EndOfStatement) &&
1164         getLexer().is(AsmToken::Comma)) {
1165    // Consume the comma token
1166    getLexer().Lex();
1167
1168    // Parse the next operand
1169    if (ParseOperand(Operands))
1170      return true;
1171  }
1172
1173  return false;
1174}
1175
1176/// ParseDirective parses the PPC specific directives
1177bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1178  StringRef IDVal = DirectiveID.getIdentifier();
1179  if (IDVal == ".word")
1180    return ParseDirectiveWord(4, DirectiveID.getLoc());
1181  if (IDVal == ".tc")
1182    return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1183  return true;
1184}
1185
1186/// ParseDirectiveWord
1187///  ::= .word [ expression (, expression)* ]
1188bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1189  if (getLexer().isNot(AsmToken::EndOfStatement)) {
1190    for (;;) {
1191      const MCExpr *Value;
1192      if (getParser().parseExpression(Value))
1193        return true;
1194
1195      getParser().getStreamer().EmitValue(Value, Size);
1196
1197      if (getLexer().is(AsmToken::EndOfStatement))
1198        break;
1199
1200      if (getLexer().isNot(AsmToken::Comma))
1201        return Error(L, "unexpected token in directive");
1202      Parser.Lex();
1203    }
1204  }
1205
1206  Parser.Lex();
1207  return false;
1208}
1209
1210/// ParseDirectiveTC
1211///  ::= .tc [ symbol (, expression)* ]
1212bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1213  // Skip TC symbol, which is only used with XCOFF.
1214  while (getLexer().isNot(AsmToken::EndOfStatement)
1215         && getLexer().isNot(AsmToken::Comma))
1216    Parser.Lex();
1217  if (getLexer().isNot(AsmToken::Comma))
1218    return Error(L, "unexpected token in directive");
1219  Parser.Lex();
1220
1221  // Align to word size.
1222  getParser().getStreamer().EmitValueToAlignment(Size);
1223
1224  // Emit expressions.
1225  return ParseDirectiveWord(Size, L);
1226}
1227
1228/// Force static initialization.
1229extern "C" void LLVMInitializePowerPCAsmParser() {
1230  RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1231  RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1232}
1233
1234#define GET_REGISTER_MATCHER
1235#define GET_MATCHER_IMPLEMENTATION
1236#include "PPCGenAsmMatcher.inc"
1237
1238// Define this matcher function after the auto-generated include so we
1239// have the match class enum definitions.
1240unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1241                                                  unsigned Kind) {
1242  // If the kind is a token for a literal immediate, check if our asm
1243  // operand matches. This is for InstAliases which have a fixed-value
1244  // immediate in the syntax.
1245  int64_t ImmVal;
1246  switch (Kind) {
1247    case MCK_0: ImmVal = 0; break;
1248    case MCK_1: ImmVal = 1; break;
1249    default: return Match_InvalidOperand;
1250  }
1251
1252  PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1253  if (Op->isImm() && Op->getImm() == ImmVal)
1254    return Match_Success;
1255
1256  return Match_InvalidOperand;
1257}
1258
1259