1//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an PPC MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstPrinter.h"
15#include "MCTargetDesc/PPCMCTargetDesc.h"
16#include "MCTargetDesc/PPCPredicates.h"
17#include "llvm/MC/MCExpr.h"
18#include "llvm/MC/MCInst.h"
19#include "llvm/MC/MCInstrInfo.h"
20#include "llvm/MC/MCSymbol.h"
21#include "llvm/Support/CommandLine.h"
22#include "llvm/Support/raw_ostream.h"
23#include "llvm/Target/TargetOpcodes.h"
24using namespace llvm;
25
26#define DEBUG_TYPE "asm-printer"
27
28// FIXME: Once the integrated assembler supports full register names, tie this
29// to the verbose-asm setting.
30static cl::opt<bool>
31FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
32             cl::desc("Use full register names when printing assembly"));
33
34#include "PPCGenAsmWriter.inc"
35
36void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
37  const char *RegName = getRegisterName(RegNo);
38  if (RegName[0] == 'q' /* QPX */) {
39    // The system toolchain on the BG/Q does not understand QPX register names
40    // in .cfi_* directives, so print the name of the floating-point
41    // subregister instead.
42    std::string RN(RegName);
43
44    RN[0] = 'f';
45    OS << RN;
46
47    return;
48  }
49
50  OS << RegName;
51}
52
53void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
54                               StringRef Annot, const MCSubtargetInfo &STI) {
55  // Check for slwi/srwi mnemonics.
56  if (MI->getOpcode() == PPC::RLWINM) {
57    unsigned char SH = MI->getOperand(2).getImm();
58    unsigned char MB = MI->getOperand(3).getImm();
59    unsigned char ME = MI->getOperand(4).getImm();
60    bool useSubstituteMnemonic = false;
61    if (SH <= 31 && MB == 0 && ME == (31-SH)) {
62      O << "\tslwi "; useSubstituteMnemonic = true;
63    }
64    if (SH <= 31 && MB == (32-SH) && ME == 31) {
65      O << "\tsrwi "; useSubstituteMnemonic = true;
66      SH = 32-SH;
67    }
68    if (useSubstituteMnemonic) {
69      printOperand(MI, 0, O);
70      O << ", ";
71      printOperand(MI, 1, O);
72      O << ", " << (unsigned int)SH;
73
74      printAnnotation(O, Annot);
75      return;
76    }
77  }
78
79  if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
80      MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
81    O << "\tmr ";
82    printOperand(MI, 0, O);
83    O << ", ";
84    printOperand(MI, 1, O);
85    printAnnotation(O, Annot);
86    return;
87  }
88
89  if (MI->getOpcode() == PPC::RLDICR) {
90    unsigned char SH = MI->getOperand(2).getImm();
91    unsigned char ME = MI->getOperand(3).getImm();
92    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
93    if (63-SH == ME) {
94      O << "\tsldi ";
95      printOperand(MI, 0, O);
96      O << ", ";
97      printOperand(MI, 1, O);
98      O << ", " << (unsigned int)SH;
99      printAnnotation(O, Annot);
100      return;
101    }
102  }
103
104  // For fast-isel, a COPY_TO_REGCLASS may survive this long.  This is
105  // used when converting a 32-bit float to a 64-bit float as part of
106  // conversion to an integer (see PPCFastISel.cpp:SelectFPToI()),
107  // as otherwise we have problems with incorrect register classes
108  // in machine instruction verification.  For now, just avoid trying
109  // to print it as such an instruction has no effect (a 32-bit float
110  // in a register is already in 64-bit form, just with lower
111  // precision).  FIXME: Is there a better solution?
112  if (MI->getOpcode() == TargetOpcode::COPY_TO_REGCLASS)
113    return;
114
115  printInstruction(MI, O);
116  printAnnotation(O, Annot);
117}
118
119
120void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
121                                           raw_ostream &O,
122                                           const char *Modifier) {
123  unsigned Code = MI->getOperand(OpNo).getImm();
124
125  if (StringRef(Modifier) == "cc") {
126    switch ((PPC::Predicate)Code) {
127    case PPC::PRED_LT_MINUS:
128    case PPC::PRED_LT_PLUS:
129    case PPC::PRED_LT:
130      O << "lt";
131      return;
132    case PPC::PRED_LE_MINUS:
133    case PPC::PRED_LE_PLUS:
134    case PPC::PRED_LE:
135      O << "le";
136      return;
137    case PPC::PRED_EQ_MINUS:
138    case PPC::PRED_EQ_PLUS:
139    case PPC::PRED_EQ:
140      O << "eq";
141      return;
142    case PPC::PRED_GE_MINUS:
143    case PPC::PRED_GE_PLUS:
144    case PPC::PRED_GE:
145      O << "ge";
146      return;
147    case PPC::PRED_GT_MINUS:
148    case PPC::PRED_GT_PLUS:
149    case PPC::PRED_GT:
150      O << "gt";
151      return;
152    case PPC::PRED_NE_MINUS:
153    case PPC::PRED_NE_PLUS:
154    case PPC::PRED_NE:
155      O << "ne";
156      return;
157    case PPC::PRED_UN_MINUS:
158    case PPC::PRED_UN_PLUS:
159    case PPC::PRED_UN:
160      O << "un";
161      return;
162    case PPC::PRED_NU_MINUS:
163    case PPC::PRED_NU_PLUS:
164    case PPC::PRED_NU:
165      O << "nu";
166      return;
167    case PPC::PRED_BIT_SET:
168    case PPC::PRED_BIT_UNSET:
169      llvm_unreachable("Invalid use of bit predicate code");
170    }
171    llvm_unreachable("Invalid predicate code");
172  }
173
174  if (StringRef(Modifier) == "pm") {
175    switch ((PPC::Predicate)Code) {
176    case PPC::PRED_LT:
177    case PPC::PRED_LE:
178    case PPC::PRED_EQ:
179    case PPC::PRED_GE:
180    case PPC::PRED_GT:
181    case PPC::PRED_NE:
182    case PPC::PRED_UN:
183    case PPC::PRED_NU:
184      return;
185    case PPC::PRED_LT_MINUS:
186    case PPC::PRED_LE_MINUS:
187    case PPC::PRED_EQ_MINUS:
188    case PPC::PRED_GE_MINUS:
189    case PPC::PRED_GT_MINUS:
190    case PPC::PRED_NE_MINUS:
191    case PPC::PRED_UN_MINUS:
192    case PPC::PRED_NU_MINUS:
193      O << "-";
194      return;
195    case PPC::PRED_LT_PLUS:
196    case PPC::PRED_LE_PLUS:
197    case PPC::PRED_EQ_PLUS:
198    case PPC::PRED_GE_PLUS:
199    case PPC::PRED_GT_PLUS:
200    case PPC::PRED_NE_PLUS:
201    case PPC::PRED_UN_PLUS:
202    case PPC::PRED_NU_PLUS:
203      O << "+";
204      return;
205    case PPC::PRED_BIT_SET:
206    case PPC::PRED_BIT_UNSET:
207      llvm_unreachable("Invalid use of bit predicate code");
208    }
209    llvm_unreachable("Invalid predicate code");
210  }
211
212  assert(StringRef(Modifier) == "reg" &&
213         "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
214  printOperand(MI, OpNo+1, O);
215}
216
217void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
218                                       raw_ostream &O) {
219  unsigned int Value = MI->getOperand(OpNo).getImm();
220  assert(Value <= 1 && "Invalid u1imm argument!");
221  O << (unsigned int)Value;
222}
223
224void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
225                                       raw_ostream &O) {
226  unsigned int Value = MI->getOperand(OpNo).getImm();
227  assert(Value <= 3 && "Invalid u2imm argument!");
228  O << (unsigned int)Value;
229}
230
231void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
232                                       raw_ostream &O) {
233  unsigned int Value = MI->getOperand(OpNo).getImm();
234  assert(Value <= 8 && "Invalid u3imm argument!");
235  O << (unsigned int)Value;
236}
237
238void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
239                                       raw_ostream &O) {
240  unsigned int Value = MI->getOperand(OpNo).getImm();
241  assert(Value <= 15 && "Invalid u4imm argument!");
242  O << (unsigned int)Value;
243}
244
245void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
246                                       raw_ostream &O) {
247  int Value = MI->getOperand(OpNo).getImm();
248  Value = SignExtend32<5>(Value);
249  O << (int)Value;
250}
251
252void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
253                                       raw_ostream &O) {
254  unsigned int Value = MI->getOperand(OpNo).getImm();
255  assert(Value <= 31 && "Invalid u5imm argument!");
256  O << (unsigned int)Value;
257}
258
259void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
260                                       raw_ostream &O) {
261  unsigned int Value = MI->getOperand(OpNo).getImm();
262  assert(Value <= 63 && "Invalid u6imm argument!");
263  O << (unsigned int)Value;
264}
265
266void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
267                                        raw_ostream &O) {
268  unsigned short Value = MI->getOperand(OpNo).getImm();
269  assert(Value <= 4095 && "Invalid u12imm argument!");
270  O << (unsigned short)Value;
271}
272
273void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
274                                        raw_ostream &O) {
275  if (MI->getOperand(OpNo).isImm())
276    O << (short)MI->getOperand(OpNo).getImm();
277  else
278    printOperand(MI, OpNo, O);
279}
280
281void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
282                                        raw_ostream &O) {
283  if (MI->getOperand(OpNo).isImm())
284    O << (unsigned short)MI->getOperand(OpNo).getImm();
285  else
286    printOperand(MI, OpNo, O);
287}
288
289void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
290                                        raw_ostream &O) {
291  if (!MI->getOperand(OpNo).isImm())
292    return printOperand(MI, OpNo, O);
293
294  // Branches can take an immediate operand.  This is used by the branch
295  // selection pass to print .+8, an eight byte displacement from the PC.
296  O << ".+";
297  printAbsBranchOperand(MI, OpNo, O);
298}
299
300void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
301                                           raw_ostream &O) {
302  if (!MI->getOperand(OpNo).isImm())
303    return printOperand(MI, OpNo, O);
304
305  O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
306}
307
308
309void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
310                                 raw_ostream &O) {
311  unsigned CCReg = MI->getOperand(OpNo).getReg();
312  unsigned RegNo;
313  switch (CCReg) {
314  default: llvm_unreachable("Unknown CR register");
315  case PPC::CR0: RegNo = 0; break;
316  case PPC::CR1: RegNo = 1; break;
317  case PPC::CR2: RegNo = 2; break;
318  case PPC::CR3: RegNo = 3; break;
319  case PPC::CR4: RegNo = 4; break;
320  case PPC::CR5: RegNo = 5; break;
321  case PPC::CR6: RegNo = 6; break;
322  case PPC::CR7: RegNo = 7; break;
323  }
324  O << (0x80 >> RegNo);
325}
326
327void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
328                                    raw_ostream &O) {
329  printS16ImmOperand(MI, OpNo, O);
330  O << '(';
331  if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
332    O << "0";
333  else
334    printOperand(MI, OpNo+1, O);
335  O << ')';
336}
337
338void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
339                                    raw_ostream &O) {
340  // When used as the base register, r0 reads constant zero rather than
341  // the value contained in the register.  For this reason, the darwin
342  // assembler requires that we print r0 as 0 (no r) when used as the base.
343  if (MI->getOperand(OpNo).getReg() == PPC::R0)
344    O << "0";
345  else
346    printOperand(MI, OpNo, O);
347  O << ", ";
348  printOperand(MI, OpNo+1, O);
349}
350
351void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
352                                  raw_ostream &O) {
353  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
354  // come at the _end_ of the expression.
355  const MCOperand &Op = MI->getOperand(OpNo);
356  const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
357  O << refExp.getSymbol().getName();
358  O << '(';
359  printOperand(MI, OpNo+1, O);
360  O << ')';
361  if (refExp.getKind() != MCSymbolRefExpr::VK_None)
362    O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
363}
364
365
366/// stripRegisterPrefix - This method strips the character prefix from a
367/// register name so that only the number is left.  Used by for linux asm.
368static const char *stripRegisterPrefix(const char *RegName) {
369  if (FullRegNames)
370    return RegName;
371
372  switch (RegName[0]) {
373  case 'r':
374  case 'f':
375  case 'q': // for QPX
376  case 'v':
377    if (RegName[1] == 's')
378      return RegName + 2;
379    return RegName + 1;
380  case 'c': if (RegName[1] == 'r') return RegName + 2;
381  }
382
383  return RegName;
384}
385
386void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
387                                  raw_ostream &O) {
388  const MCOperand &Op = MI->getOperand(OpNo);
389  if (Op.isReg()) {
390    const char *RegName = getRegisterName(Op.getReg());
391    // The linux and AIX assembler does not take register prefixes.
392    if (!isDarwinSyntax())
393      RegName = stripRegisterPrefix(RegName);
394
395    O << RegName;
396    return;
397  }
398
399  if (Op.isImm()) {
400    O << Op.getImm();
401    return;
402  }
403
404  assert(Op.isExpr() && "unknown operand kind in printOperand");
405  O << *Op.getExpr();
406}
407
408