1//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Top-level implementation for the PowerPC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCTargetMachine.h"
15#include "PPC.h"
16#include "PPCTargetObjectFile.h"
17#include "PPCTargetTransformInfo.h"
18#include "llvm/CodeGen/Passes.h"
19#include "llvm/IR/Function.h"
20#include "llvm/IR/LegacyPassManager.h"
21#include "llvm/MC/MCStreamer.h"
22#include "llvm/Support/CommandLine.h"
23#include "llvm/Support/FormattedStream.h"
24#include "llvm/Support/TargetRegistry.h"
25#include "llvm/Target/TargetOptions.h"
26#include "llvm/Transforms/Scalar.h"
27using namespace llvm;
28
29static cl::
30opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
31                        cl::desc("Disable CTR loops for PPC"));
32
33static cl::
34opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
35                            cl::desc("Disable PPC loop preinc prep"));
36
37static cl::opt<bool>
38VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
39  cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
40
41static cl::opt<bool>
42EnableGEPOpt("ppc-gep-opt", cl::Hidden,
43             cl::desc("Enable optimizations on complex GEPs"),
44             cl::init(true));
45
46static cl::opt<bool>
47EnablePrefetch("enable-ppc-prefetching",
48                  cl::desc("disable software prefetching on PPC"),
49                  cl::init(false), cl::Hidden);
50
51extern "C" void LLVMInitializePowerPCTarget() {
52  // Register the targets
53  RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
54  RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
55  RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
56}
57
58/// Return the datalayout string of a subtarget.
59static std::string getDataLayoutString(const Triple &T) {
60  bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
61  std::string Ret;
62
63  // Most PPC* platforms are big endian, PPC64LE is little endian.
64  if (T.getArch() == Triple::ppc64le)
65    Ret = "e";
66  else
67    Ret = "E";
68
69  Ret += DataLayout::getManglingComponent(T);
70
71  // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
72  // pointers.
73  if (!is64Bit || T.getOS() == Triple::Lv2)
74    Ret += "-p:32:32";
75
76  // Note, the alignment values for f64 and i64 on ppc64 in Darwin
77  // documentation are wrong; these are correct (i.e. "what gcc does").
78  if (is64Bit || !T.isOSDarwin())
79    Ret += "-i64:64";
80  else
81    Ret += "-f64:32:64";
82
83  // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
84  if (is64Bit)
85    Ret += "-n32:64";
86  else
87    Ret += "-n32";
88
89  return Ret;
90}
91
92static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
93  std::string FullFS = FS;
94  Triple TargetTriple(TT);
95
96  // Make sure 64-bit features are available when CPUname is generic
97  if (TargetTriple.getArch() == Triple::ppc64 ||
98      TargetTriple.getArch() == Triple::ppc64le) {
99    if (!FullFS.empty())
100      FullFS = "+64bit," + FullFS;
101    else
102      FullFS = "+64bit";
103  }
104
105  if (OL >= CodeGenOpt::Default) {
106    if (!FullFS.empty())
107      FullFS = "+crbits," + FullFS;
108    else
109      FullFS = "+crbits";
110  }
111
112  if (OL != CodeGenOpt::None) {
113     if (!FullFS.empty())
114      FullFS = "+invariant-function-descriptors," + FullFS;
115    else
116      FullFS = "+invariant-function-descriptors";
117  }
118
119  return FullFS;
120}
121
122static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
123  // If it isn't a Mach-O file then it's going to be a linux ELF
124  // object file.
125  if (TT.isOSDarwin())
126    return make_unique<TargetLoweringObjectFileMachO>();
127
128  return make_unique<PPC64LinuxTargetObjectFile>();
129}
130
131static PPCTargetMachine::PPCABI computeTargetABI(const Triple &TT,
132                                                 const TargetOptions &Options) {
133  if (Options.MCOptions.getABIName().startswith("elfv1"))
134    return PPCTargetMachine::PPC_ABI_ELFv1;
135  else if (Options.MCOptions.getABIName().startswith("elfv2"))
136    return PPCTargetMachine::PPC_ABI_ELFv2;
137
138  assert(Options.MCOptions.getABIName().empty() &&
139	 "Unknown target-abi option!");
140
141  if (!TT.isMacOSX()) {
142    switch (TT.getArch()) {
143    case Triple::ppc64le:
144      return PPCTargetMachine::PPC_ABI_ELFv2;
145    case Triple::ppc64:
146      return PPCTargetMachine::PPC_ABI_ELFv1;
147    default:
148      // Fallthrough.
149      ;
150    }
151  }
152  return PPCTargetMachine::PPC_ABI_UNKNOWN;
153}
154
155// The FeatureString here is a little subtle. We are modifying the feature string
156// with what are (currently) non-function specific overrides as it goes into the
157// LLVMTargetMachine constructor and then using the stored value in the
158// Subtarget constructor below it.
159PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
160                                   StringRef FS, const TargetOptions &Options,
161                                   Reloc::Model RM, CodeModel::Model CM,
162                                   CodeGenOpt::Level OL)
163    : LLVMTargetMachine(T, getDataLayoutString(Triple(TT)), TT, CPU,
164                        computeFSAdditions(FS, OL, TT), Options, RM, CM, OL),
165      TLOF(createTLOF(Triple(getTargetTriple()))),
166      TargetABI(computeTargetABI(Triple(TT), Options)) {
167  initAsmInfo();
168}
169
170PPCTargetMachine::~PPCTargetMachine() {}
171
172void PPC32TargetMachine::anchor() { }
173
174PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
175                                       StringRef CPU, StringRef FS,
176                                       const TargetOptions &Options,
177                                       Reloc::Model RM, CodeModel::Model CM,
178                                       CodeGenOpt::Level OL)
179  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
180}
181
182void PPC64TargetMachine::anchor() { }
183
184PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
185                                       StringRef CPU,  StringRef FS,
186                                       const TargetOptions &Options,
187                                       Reloc::Model RM, CodeModel::Model CM,
188                                       CodeGenOpt::Level OL)
189  : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
190}
191
192const PPCSubtarget *
193PPCTargetMachine::getSubtargetImpl(const Function &F) const {
194  Attribute CPUAttr = F.getFnAttribute("target-cpu");
195  Attribute FSAttr = F.getFnAttribute("target-features");
196
197  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
198                        ? CPUAttr.getValueAsString().str()
199                        : TargetCPU;
200  std::string FS = !FSAttr.hasAttribute(Attribute::None)
201                       ? FSAttr.getValueAsString().str()
202                       : TargetFS;
203
204  auto &I = SubtargetMap[CPU + FS];
205  if (!I) {
206    // This needs to be done before we create a new subtarget since any
207    // creation will depend on the TM and the code generation flags on the
208    // function that reside in TargetOptions.
209    resetTargetOptions(F);
210    I = llvm::make_unique<PPCSubtarget>(
211        TargetTriple, CPU,
212        // FIXME: It would be good to have the subtarget additions here
213        // not necessary. Anything that turns them on/off (overrides) ends
214        // up being put at the end of the feature string, but the defaults
215        // shouldn't require adding them. Fixing this means pulling Feature64Bit
216        // out of most of the target cpus in the .td file and making it set only
217        // as part of initialization via the TargetTriple.
218        computeFSAdditions(FS, getOptLevel(), getTargetTriple()), *this);
219  }
220  return I.get();
221}
222
223//===----------------------------------------------------------------------===//
224// Pass Pipeline Configuration
225//===----------------------------------------------------------------------===//
226
227namespace {
228/// PPC Code Generator Pass Configuration Options.
229class PPCPassConfig : public TargetPassConfig {
230public:
231  PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
232    : TargetPassConfig(TM, PM) {}
233
234  PPCTargetMachine &getPPCTargetMachine() const {
235    return getTM<PPCTargetMachine>();
236  }
237
238  void addIRPasses() override;
239  bool addPreISel() override;
240  bool addILPOpts() override;
241  bool addInstSelector() override;
242  void addPreRegAlloc() override;
243  void addPreSched2() override;
244  void addPreEmitPass() override;
245};
246} // namespace
247
248TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
249  return new PPCPassConfig(this, PM);
250}
251
252void PPCPassConfig::addIRPasses() {
253  addPass(createAtomicExpandPass(&getPPCTargetMachine()));
254
255  // For the BG/Q (or if explicitly requested), add explicit data prefetch
256  // intrinsics.
257  bool UsePrefetching =
258    Triple(TM->getTargetTriple()).getVendor() == Triple::BGQ &&
259    getOptLevel() != CodeGenOpt::None;
260  if (EnablePrefetch.getNumOccurrences() > 0)
261    UsePrefetching = EnablePrefetch;
262  if (UsePrefetching)
263    addPass(createPPCLoopDataPrefetchPass());
264
265  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
266    // Call SeparateConstOffsetFromGEP pass to extract constants within indices
267    // and lower a GEP with multiple indices to either arithmetic operations or
268    // multiple GEPs with single index.
269    addPass(createSeparateConstOffsetFromGEPPass(TM, true));
270    // Call EarlyCSE pass to find and remove subexpressions in the lowered
271    // result.
272    addPass(createEarlyCSEPass());
273    // Do loop invariant code motion in case part of the lowered result is
274    // invariant.
275    addPass(createLICMPass());
276  }
277
278  TargetPassConfig::addIRPasses();
279}
280
281bool PPCPassConfig::addPreISel() {
282  if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
283    addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
284
285  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
286    addPass(createPPCCTRLoops(getPPCTargetMachine()));
287
288  return false;
289}
290
291bool PPCPassConfig::addILPOpts() {
292  addPass(&EarlyIfConverterID);
293  return true;
294}
295
296bool PPCPassConfig::addInstSelector() {
297  // Install an instruction selector.
298  addPass(createPPCISelDag(getPPCTargetMachine()));
299
300#ifndef NDEBUG
301  if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
302    addPass(createPPCCTRLoopsVerify());
303#endif
304
305  addPass(createPPCVSXCopyPass());
306  return false;
307}
308
309void PPCPassConfig::addPreRegAlloc() {
310  initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
311  insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
312             &PPCVSXFMAMutateID);
313  if (getPPCTargetMachine().getRelocationModel() == Reloc::PIC_)
314    addPass(createPPCTLSDynamicCallPass());
315}
316
317void PPCPassConfig::addPreSched2() {
318  if (getOptLevel() != CodeGenOpt::None)
319    addPass(&IfConverterID);
320}
321
322void PPCPassConfig::addPreEmitPass() {
323  if (getOptLevel() != CodeGenOpt::None)
324    addPass(createPPCEarlyReturnPass(), false);
325  // Must run branch selection immediately preceding the asm printer.
326  addPass(createPPCBranchSelectionPass(), false);
327}
328
329TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
330  return TargetIRAnalysis(
331      [this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
332}
333