X86AsmPrinter.cpp revision b12ee503f7c91542ed8de3f38b309b860a274679
1//===-- X86AsmPrinter.cpp - Convert X86 LLVM code to Intel assembly -------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to Intel-format assembly language. This 12// printer is the output mechanism used by `llc' and `lli -print-machineinstrs' 13// on X86. 14// 15//===----------------------------------------------------------------------===// 16 17#include "X86.h" 18#include "X86InstrInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Module.h" 23#include "llvm/Assembly/Writer.h" 24#include "llvm/CodeGen/MachineCodeEmitter.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFunctionPass.h" 27#include "llvm/CodeGen/MachineInstr.h" 28#include "llvm/CodeGen/ValueTypes.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Support/Mangler.h" 31#include "Support/Statistic.h" 32#include "Support/StringExtras.h" 33#include "Support/CommandLine.h" 34using namespace llvm; 35 36namespace { 37 Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); 38 39 // FIXME: This should be automatically picked up by autoconf from the C 40 // frontend 41 cl::opt<bool> EmitCygwin("enable-cygwin-compatible-output", cl::Hidden, 42 cl::desc("Emit X86 assembly code suitable for consumption by cygwin")); 43 44 struct GasBugWorkaroundEmitter : public MachineCodeEmitter { 45 GasBugWorkaroundEmitter(std::ostream& o) 46 : O(o), OldFlags(O.flags()), firstByte(true) { 47 O << std::hex; 48 } 49 50 ~GasBugWorkaroundEmitter() { 51 O.flags(OldFlags); 52 O << "\t# "; 53 } 54 55 virtual void emitByte(unsigned char B) { 56 if (!firstByte) O << "\n\t"; 57 firstByte = false; 58 O << ".byte 0x" << (unsigned) B; 59 } 60 61 // These should never be called 62 virtual void emitWord(unsigned W) { assert(0); } 63 virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); } 64 virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); } 65 virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); } 66 virtual uint64_t getCurrentPCValue() { abort(); } 67 virtual uint64_t forceCompilationOf(Function *F) { abort(); } 68 69 private: 70 std::ostream& O; 71 std::ios::fmtflags OldFlags; 72 bool firstByte; 73 }; 74 75 struct X86AsmPrinter : public MachineFunctionPass { 76 /// Output stream on which we're printing assembly code. 77 /// 78 std::ostream &O; 79 80 /// Target machine description which we query for reg. names, data 81 /// layout, etc. 82 /// 83 TargetMachine &TM; 84 85 /// Name-mangler for global names. 86 /// 87 Mangler *Mang; 88 89 X86AsmPrinter(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } 90 91 /// Cache of mangled name for current function. This is 92 /// recalculated at the beginning of each call to 93 /// runOnMachineFunction(). 94 /// 95 std::string CurrentFnName; 96 97 virtual const char *getPassName() const { 98 return "X86 Assembly Printer"; 99 } 100 101 /// printInstruction - This method is automatically generated by tablegen 102 /// from the instruction set description. This method returns true if the 103 /// machine instruction was sufficiently described to print it, otherwise it 104 /// returns false. 105 bool printInstruction(const MachineInstr *MI); 106 107 // This method is used by the tablegen'erated instruction printer. 108 void printOperand(const MachineOperand &MO, MVT::ValueType VT) { 109 printOp(MO); 110 } 111 112 void printImplUsesBefore(const TargetInstrDescriptor &Desc); 113 bool printImplDefsBefore(const TargetInstrDescriptor &Desc); 114 bool printImplUsesAfter(const TargetInstrDescriptor &Desc, const bool LC); 115 bool printImplDefsAfter(const TargetInstrDescriptor &Desc, const bool LC); 116 void printMachineInstruction(const MachineInstr *MI); 117 void printOp(const MachineOperand &MO, bool elideOffsetKeyword = false); 118 void printMemReference(const MachineInstr *MI, unsigned Op); 119 void printConstantPool(MachineConstantPool *MCP); 120 bool runOnMachineFunction(MachineFunction &F); 121 bool doInitialization(Module &M); 122 bool doFinalization(Module &M); 123 void emitGlobalConstant(const Constant* CV); 124 void emitConstantValueOnly(const Constant *CV); 125 }; 126} // end of anonymous namespace 127 128/// createX86CodePrinterPass - Returns a pass that prints the X86 129/// assembly code for a MachineFunction to the given output stream, 130/// using the given target machine description. This should work 131/// regardless of whether the function is in SSA form. 132/// 133FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ 134 return new X86AsmPrinter(o, tm); 135} 136 137 138// Include the auto-generated portion of the assembly writer. 139#include "X86GenAsmWriter.inc" 140 141 142/// toOctal - Convert the low order bits of X into an octal digit. 143/// 144static inline char toOctal(int X) { 145 return (X&7)+'0'; 146} 147 148/// getAsCString - Return the specified array as a C compatible 149/// string, only if the predicate isStringCompatible is true. 150/// 151static void printAsCString(std::ostream &O, const ConstantArray *CVA) { 152 assert(CVA->isString() && "Array is not string compatible!"); 153 154 O << "\""; 155 for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { 156 unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue(); 157 158 if (C == '"') { 159 O << "\\\""; 160 } else if (C == '\\') { 161 O << "\\\\"; 162 } else if (isprint(C)) { 163 O << C; 164 } else { 165 switch(C) { 166 case '\b': O << "\\b"; break; 167 case '\f': O << "\\f"; break; 168 case '\n': O << "\\n"; break; 169 case '\r': O << "\\r"; break; 170 case '\t': O << "\\t"; break; 171 default: 172 O << '\\'; 173 O << toOctal(C >> 6); 174 O << toOctal(C >> 3); 175 O << toOctal(C >> 0); 176 break; 177 } 178 } 179 } 180 O << "\""; 181} 182 183// Print out the specified constant, without a storage class. Only the 184// constants valid in constant expressions can occur here. 185void X86AsmPrinter::emitConstantValueOnly(const Constant *CV) { 186 if (CV->isNullValue()) 187 O << "0"; 188 else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) { 189 assert(CB == ConstantBool::True); 190 O << "1"; 191 } else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV)) 192 if (((CI->getValue() << 32) >> 32) == CI->getValue()) 193 O << CI->getValue(); 194 else 195 O << (unsigned long long)CI->getValue(); 196 else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV)) 197 O << CI->getValue(); 198 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) 199 // This is a constant address for a global variable or function. Use the 200 // name of the variable or function as the address value. 201 O << Mang->getValueName(GV); 202 else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) { 203 const TargetData &TD = TM.getTargetData(); 204 switch(CE->getOpcode()) { 205 case Instruction::GetElementPtr: { 206 // generate a symbolic expression for the byte address 207 const Constant *ptrVal = CE->getOperand(0); 208 std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end()); 209 if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { 210 O << "("; 211 emitConstantValueOnly(ptrVal); 212 O << ") + " << Offset; 213 } else { 214 emitConstantValueOnly(ptrVal); 215 } 216 break; 217 } 218 case Instruction::Cast: { 219 // Support only non-converting or widening casts for now, that is, ones 220 // that do not involve a change in value. This assertion is really gross, 221 // and may not even be a complete check. 222 Constant *Op = CE->getOperand(0); 223 const Type *OpTy = Op->getType(), *Ty = CE->getType(); 224 225 // Remember, kids, pointers on x86 can be losslessly converted back and 226 // forth into 32-bit or wider integers, regardless of signedness. :-P 227 assert(((isa<PointerType>(OpTy) 228 && (Ty == Type::LongTy || Ty == Type::ULongTy 229 || Ty == Type::IntTy || Ty == Type::UIntTy)) 230 || (isa<PointerType>(Ty) 231 && (OpTy == Type::LongTy || OpTy == Type::ULongTy 232 || OpTy == Type::IntTy || OpTy == Type::UIntTy)) 233 || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) 234 && OpTy->isLosslesslyConvertibleTo(Ty)))) 235 && "FIXME: Don't yet support this kind of constant cast expr"); 236 O << "("; 237 emitConstantValueOnly(Op); 238 O << ")"; 239 break; 240 } 241 case Instruction::Add: 242 O << "("; 243 emitConstantValueOnly(CE->getOperand(0)); 244 O << ") + ("; 245 emitConstantValueOnly(CE->getOperand(1)); 246 O << ")"; 247 break; 248 default: 249 assert(0 && "Unsupported operator!"); 250 } 251 } else { 252 assert(0 && "Unknown constant value!"); 253 } 254} 255 256// Print a constant value or values, with the appropriate storage class as a 257// prefix. 258void X86AsmPrinter::emitGlobalConstant(const Constant *CV) { 259 const TargetData &TD = TM.getTargetData(); 260 261 if (CV->isNullValue()) { 262 O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n"; 263 return; 264 } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) { 265 if (CVA->isString()) { 266 O << "\t.ascii\t"; 267 printAsCString(O, CVA); 268 O << "\n"; 269 } else { // Not a string. Print the values in successive locations 270 const std::vector<Use> &constValues = CVA->getValues(); 271 for (unsigned i=0; i < constValues.size(); i++) 272 emitGlobalConstant(cast<Constant>(constValues[i].get())); 273 } 274 return; 275 } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) { 276 // Print the fields in successive locations. Pad to align if needed! 277 const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); 278 const std::vector<Use>& constValues = CVS->getValues(); 279 unsigned sizeSoFar = 0; 280 for (unsigned i=0, N = constValues.size(); i < N; i++) { 281 const Constant* field = cast<Constant>(constValues[i].get()); 282 283 // Check if padding is needed and insert one or more 0s. 284 unsigned fieldSize = TD.getTypeSize(field->getType()); 285 unsigned padSize = ((i == N-1? cvsLayout->StructSize 286 : cvsLayout->MemberOffsets[i+1]) 287 - cvsLayout->MemberOffsets[i]) - fieldSize; 288 sizeSoFar += fieldSize + padSize; 289 290 // Now print the actual field value 291 emitGlobalConstant(field); 292 293 // Insert the field padding unless it's zero bytes... 294 if (padSize) 295 O << "\t.zero\t " << padSize << "\n"; 296 } 297 assert(sizeSoFar == cvsLayout->StructSize && 298 "Layout of constant struct may be incorrect!"); 299 return; 300 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 301 // FP Constants are printed as integer constants to avoid losing 302 // precision... 303 double Val = CFP->getValue(); 304 switch (CFP->getType()->getTypeID()) { 305 default: assert(0 && "Unknown floating point type!"); 306 case Type::FloatTyID: { 307 union FU { // Abide by C TBAA rules 308 float FVal; 309 unsigned UVal; 310 } U; 311 U.FVal = Val; 312 O << ".long\t" << U.UVal << "\t# float " << Val << "\n"; 313 return; 314 } 315 case Type::DoubleTyID: { 316 union DU { // Abide by C TBAA rules 317 double FVal; 318 uint64_t UVal; 319 } U; 320 U.FVal = Val; 321 O << ".quad\t" << U.UVal << "\t# double " << Val << "\n"; 322 return; 323 } 324 } 325 } 326 327 const Type *type = CV->getType(); 328 O << "\t"; 329 switch (type->getTypeID()) { 330 case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: 331 O << ".byte"; 332 break; 333 case Type::UShortTyID: case Type::ShortTyID: 334 O << ".word"; 335 break; 336 case Type::FloatTyID: case Type::PointerTyID: 337 case Type::UIntTyID: case Type::IntTyID: 338 O << ".long"; 339 break; 340 case Type::DoubleTyID: 341 case Type::ULongTyID: case Type::LongTyID: 342 O << ".quad"; 343 break; 344 default: 345 assert (0 && "Can't handle printing this type of thing"); 346 break; 347 } 348 O << "\t"; 349 emitConstantValueOnly(CV); 350 O << "\n"; 351} 352 353/// printConstantPool - Print to the current output stream assembly 354/// representations of the constants in the constant pool MCP. This is 355/// used to print out constants which have been "spilled to memory" by 356/// the code generator. 357/// 358void X86AsmPrinter::printConstantPool(MachineConstantPool *MCP) { 359 const std::vector<Constant*> &CP = MCP->getConstants(); 360 const TargetData &TD = TM.getTargetData(); 361 362 if (CP.empty()) return; 363 364 for (unsigned i = 0, e = CP.size(); i != e; ++i) { 365 O << "\t.section .rodata\n"; 366 O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) 367 << "\n"; 368 O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#" 369 << *CP[i] << "\n"; 370 emitGlobalConstant(CP[i]); 371 } 372} 373 374/// runOnMachineFunction - This uses the printMachineInstruction() 375/// method to print assembly for each instruction. 376/// 377bool X86AsmPrinter::runOnMachineFunction(MachineFunction &MF) { 378 O << "\n\n"; 379 // What's my mangled name? 380 CurrentFnName = Mang->getValueName(MF.getFunction()); 381 382 // Print out constants referenced by the function 383 printConstantPool(MF.getConstantPool()); 384 385 // Print out labels for the function. 386 O << "\t.text\n"; 387 O << "\t.align 16\n"; 388 O << "\t.globl\t" << CurrentFnName << "\n"; 389 if (!EmitCygwin) 390 O << "\t.type\t" << CurrentFnName << ", @function\n"; 391 O << CurrentFnName << ":\n"; 392 393 // Print out code for the function. 394 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 395 I != E; ++I) { 396 // Print a label for the basic block. 397 O << ".LBB" << CurrentFnName << "_" << I->getNumber() << ":\t# " 398 << I->getBasicBlock()->getName() << "\n"; 399 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); 400 II != E; ++II) { 401 // Print the assembly for the instruction. 402 O << "\t"; 403 printMachineInstruction(II); 404 } 405 } 406 407 // We didn't modify anything. 408 return false; 409} 410 411static bool isScale(const MachineOperand &MO) { 412 return MO.isImmediate() && 413 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || 414 MO.getImmedValue() == 4 || MO.getImmedValue() == 8); 415} 416 417static bool isMem(const MachineInstr *MI, unsigned Op) { 418 if (MI->getOperand(Op).isFrameIndex()) return true; 419 if (MI->getOperand(Op).isConstantPoolIndex()) return true; 420 return Op+4 <= MI->getNumOperands() && 421 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && 422 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); 423} 424 425 426 427void X86AsmPrinter::printOp(const MachineOperand &MO, 428 bool elideOffsetKeyword /* = false */) { 429 const MRegisterInfo &RI = *TM.getRegisterInfo(); 430 switch (MO.getType()) { 431 case MachineOperand::MO_VirtualRegister: 432 if (Value *V = MO.getVRegValueOrNull()) { 433 O << "<" << V->getName() << ">"; 434 return; 435 } 436 // FALLTHROUGH 437 case MachineOperand::MO_MachineRegister: 438 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) 439 // Bug Workaround: See note in Printer::doInitialization about %. 440 O << "%" << RI.get(MO.getReg()).Name; 441 else 442 O << "%reg" << MO.getReg(); 443 return; 444 445 case MachineOperand::MO_SignExtendedImmed: 446 case MachineOperand::MO_UnextendedImmed: 447 O << (int)MO.getImmedValue(); 448 return; 449 case MachineOperand::MO_MachineBasicBlock: { 450 MachineBasicBlock *MBBOp = MO.getMachineBasicBlock(); 451 O << ".LBB" << Mang->getValueName(MBBOp->getParent()->getFunction()) 452 << "_" << MBBOp->getNumber () << "\t# " 453 << MBBOp->getBasicBlock ()->getName (); 454 return; 455 } 456 case MachineOperand::MO_PCRelativeDisp: 457 std::cerr << "Shouldn't use addPCDisp() when building X86 MachineInstrs"; 458 abort (); 459 return; 460 case MachineOperand::MO_GlobalAddress: 461 if (!elideOffsetKeyword) 462 O << "OFFSET "; 463 O << Mang->getValueName(MO.getGlobal()); 464 return; 465 case MachineOperand::MO_ExternalSymbol: 466 O << MO.getSymbolName(); 467 return; 468 default: 469 O << "<unknown operand type>"; return; 470 } 471} 472 473static const char* const sizePtr(const TargetInstrDescriptor &Desc) { 474 switch (Desc.TSFlags & X86II::MemMask) { 475 default: assert(0 && "Unknown arg size!"); 476 case X86II::Mem8: return "BYTE PTR"; 477 case X86II::Mem16: return "WORD PTR"; 478 case X86II::Mem32: return "DWORD PTR"; 479 case X86II::Mem64: return "QWORD PTR"; 480 case X86II::Mem80: return "XWORD PTR"; 481 } 482} 483 484void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) { 485 assert(isMem(MI, Op) && "Invalid memory reference!"); 486 487 if (MI->getOperand(Op).isFrameIndex()) { 488 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); 489 if (MI->getOperand(Op+3).getImmedValue()) 490 O << " + " << MI->getOperand(Op+3).getImmedValue(); 491 O << "]"; 492 return; 493 } else if (MI->getOperand(Op).isConstantPoolIndex()) { 494 O << "[.CPI" << CurrentFnName << "_" 495 << MI->getOperand(Op).getConstantPoolIndex(); 496 if (MI->getOperand(Op+3).getImmedValue()) 497 O << " + " << MI->getOperand(Op+3).getImmedValue(); 498 O << "]"; 499 return; 500 } 501 502 const MachineOperand &BaseReg = MI->getOperand(Op); 503 int ScaleVal = MI->getOperand(Op+1).getImmedValue(); 504 const MachineOperand &IndexReg = MI->getOperand(Op+2); 505 int DispVal = MI->getOperand(Op+3).getImmedValue(); 506 507 O << "["; 508 bool NeedPlus = false; 509 if (BaseReg.getReg()) { 510 printOp(BaseReg); 511 NeedPlus = true; 512 } 513 514 if (IndexReg.getReg()) { 515 if (NeedPlus) O << " + "; 516 if (ScaleVal != 1) 517 O << ScaleVal << "*"; 518 printOp(IndexReg); 519 NeedPlus = true; 520 } 521 522 if (DispVal) { 523 if (NeedPlus) 524 if (DispVal > 0) 525 O << " + "; 526 else { 527 O << " - "; 528 DispVal = -DispVal; 529 } 530 O << DispVal; 531 } 532 O << "]"; 533} 534 535 536/// printImplUsesBefore - Emit the implicit-use registers for the instruction 537/// described by DESC, if its PrintImplUsesBefore flag is set. 538/// 539void X86AsmPrinter::printImplUsesBefore(const TargetInstrDescriptor &Desc) { 540 const MRegisterInfo &RI = *TM.getRegisterInfo(); 541 if (Desc.TSFlags & X86II::PrintImplUsesBefore) { 542 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { 543 // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. 544 O << "%" << RI.get(*p).Name << ", "; 545 } 546 } 547} 548 549/// printImplDefsBefore - Emit the implicit-def registers for the instruction 550/// described by DESC, if its PrintImplUsesBefore flag is set. Return true if 551/// we printed any registers. 552/// 553bool X86AsmPrinter::printImplDefsBefore(const TargetInstrDescriptor &Desc) { 554 bool Printed = false; 555 const MRegisterInfo &RI = *TM.getRegisterInfo(); 556 if (Desc.TSFlags & X86II::PrintImplDefsBefore) { 557 const unsigned *p = Desc.ImplicitDefs; 558 if (*p) { 559 O << (Printed ? ", %" : "%") << RI.get (*p).Name; 560 Printed = true; 561 ++p; 562 } 563 while (*p) { 564 // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. 565 O << ", %" << RI.get(*p).Name; 566 ++p; 567 } 568 } 569 return Printed; 570} 571 572 573/// printImplUsesAfter - Emit the implicit-use registers for the instruction 574/// described by DESC, if its PrintImplUsesAfter flag is set. 575/// 576/// Inputs: 577/// Comma - List of registers will need a leading comma. 578/// Desc - Description of the Instruction. 579/// 580/// Return value: 581/// true - Emitted one or more registers. 582/// false - Emitted no registers. 583/// 584bool X86AsmPrinter::printImplUsesAfter(const TargetInstrDescriptor &Desc, 585 const bool Comma = true) { 586 const MRegisterInfo &RI = *TM.getRegisterInfo(); 587 if (Desc.TSFlags & X86II::PrintImplUsesAfter) { 588 bool emitted = false; 589 const unsigned *p = Desc.ImplicitUses; 590 if (*p) { 591 O << (Comma ? ", %" : "%") << RI.get (*p).Name; 592 emitted = true; 593 ++p; 594 } 595 while (*p) { 596 // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. 597 O << ", %" << RI.get(*p).Name; 598 ++p; 599 } 600 return emitted; 601 } 602 return false; 603} 604 605/// printImplDefsAfter - Emit the implicit-definition registers for the 606/// instruction described by DESC, if its PrintImplDefsAfter flag is set. 607/// 608/// Inputs: 609/// Comma - List of registers will need a leading comma. 610/// Desc - Description of the Instruction 611/// 612/// Return value: 613/// true - Emitted one or more registers. 614/// false - Emitted no registers. 615/// 616bool X86AsmPrinter::printImplDefsAfter(const TargetInstrDescriptor &Desc, 617 const bool Comma = true) { 618 const MRegisterInfo &RI = *TM.getRegisterInfo(); 619 if (Desc.TSFlags & X86II::PrintImplDefsAfter) { 620 bool emitted = false; 621 const unsigned *p = Desc.ImplicitDefs; 622 if (*p) { 623 O << (Comma ? ", %" : "%") << RI.get (*p).Name; 624 emitted = true; 625 ++p; 626 } 627 while (*p) { 628 // Bug Workaround: See note in X86AsmPrinter::doInitialization about %. 629 O << ", %" << RI.get(*p).Name; 630 ++p; 631 } 632 return emitted; 633 } 634 return false; 635} 636 637/// printMachineInstruction -- Print out a single X86 LLVM instruction 638/// MI in Intel syntax to the current output stream. 639/// 640void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) { 641 ++EmittedInsts; 642 if (printInstruction(MI)) 643 return; // Printer was automatically generated 644 645 unsigned Opcode = MI->getOpcode(); 646 const TargetInstrInfo &TII = *TM.getInstrInfo(); 647 const TargetInstrDescriptor &Desc = TII.get(Opcode); 648 649 switch (Desc.TSFlags & X86II::FormMask) { 650 case X86II::Pseudo: 651 // Print pseudo-instructions as comments; either they should have been 652 // turned into real instructions by now, or they don't need to be 653 // seen by the assembler (e.g., IMPLICIT_USEs.) 654 O << "# "; 655 if (Opcode == X86::PHI) { 656 printOp(MI->getOperand(0)); 657 O << " = phi "; 658 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 659 if (i != 1) O << ", "; 660 O << "["; 661 printOp(MI->getOperand(i)); 662 O << ", "; 663 printOp(MI->getOperand(i+1)); 664 O << "]"; 665 } 666 } else { 667 unsigned i = 0; 668 if (MI->getNumOperands() && MI->getOperand(0).isDef()) { 669 printOp(MI->getOperand(0)); 670 O << " = "; 671 ++i; 672 } 673 O << TII.getName(MI->getOpcode()); 674 675 for (unsigned e = MI->getNumOperands(); i != e; ++i) { 676 O << " "; 677 if (MI->getOperand(i).isDef()) O << "*"; 678 printOp(MI->getOperand(i)); 679 if (MI->getOperand(i).isDef()) O << "*"; 680 } 681 } 682 O << "\n"; 683 return; 684 685 case X86II::RawFrm: 686 { 687 // The accepted forms of Raw instructions are: 688 // 1. jmp foo - MachineBasicBlock operand 689 // 2. call bar - GlobalAddress Operand or External Symbol Operand 690 // 3. in AL, imm - Immediate operand 691 // 692 assert(MI->getNumOperands() == 1 && 693 (MI->getOperand(0).isMachineBasicBlock() || 694 MI->getOperand(0).isGlobalAddress() || 695 MI->getOperand(0).isExternalSymbol() || 696 MI->getOperand(0).isImmediate()) && 697 "Illegal raw instruction!"); 698 O << TII.getName(MI->getOpcode()) << " "; 699 700 bool LeadingComma = printImplDefsBefore(Desc); 701 702 if (MI->getNumOperands() == 1) { 703 if (LeadingComma) O << ", "; 704 printOp(MI->getOperand(0), true); // Don't print "OFFSET"... 705 LeadingComma = true; 706 } 707 LeadingComma = printImplDefsAfter(Desc, LeadingComma) || LeadingComma; 708 printImplUsesAfter(Desc, LeadingComma); 709 O << "\n"; 710 return; 711 } 712 713 case X86II::AddRegFrm: { 714 // There are currently two forms of acceptable AddRegFrm instructions. 715 // Either the instruction JUST takes a single register (like inc, dec, etc), 716 // or it takes a register and an immediate of the same size as the register 717 // (move immediate f.e.). Note that this immediate value might be stored as 718 // an LLVM value, to represent, for example, loading the address of a global 719 // into a register. The initial register might be duplicated if this is a 720 // M_2_ADDR_REG instruction 721 // 722 assert(MI->getOperand(0).isRegister() && 723 (MI->getNumOperands() == 1 || 724 (MI->getNumOperands() == 2 && 725 (MI->getOperand(1).getVRegValueOrNull() || 726 MI->getOperand(1).isImmediate() || 727 MI->getOperand(1).isRegister() || 728 MI->getOperand(1).isGlobalAddress() || 729 MI->getOperand(1).isExternalSymbol()))) && 730 "Illegal form for AddRegFrm instruction!"); 731 732 unsigned Reg = MI->getOperand(0).getReg(); 733 734 O << TII.getName(MI->getOpcode()) << " "; 735 736 printImplUsesBefore(Desc); // fcmov* 737 738 printOp(MI->getOperand(0)); 739 if (MI->getNumOperands() == 2 && 740 (!MI->getOperand(1).isRegister() || 741 MI->getOperand(1).getVRegValueOrNull() || 742 MI->getOperand(1).isGlobalAddress() || 743 MI->getOperand(1).isExternalSymbol())) { 744 O << ", "; 745 printOp(MI->getOperand(1)); 746 } 747 printImplUsesAfter(Desc); 748 O << "\n"; 749 return; 750 } 751 case X86II::MRMDestReg: { 752 // There are three forms of MRMDestReg instructions, those with 2 753 // or 3 operands: 754 // 755 // 2 Operands: this is for things like mov that do not read a 756 // second input. 757 // 758 // 2 Operands: two address instructions which def&use the first 759 // argument and use the second as input. 760 // 761 // 3 Operands: in this form, two address instructions are the same 762 // as in 2 but have a constant argument as well. 763 // 764 bool isTwoAddr = TII.isTwoAddrInstr(Opcode); 765 assert(MI->getOperand(0).isRegister() && 766 (MI->getNumOperands() == 2 || 767 (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate())) 768 && "Bad format for MRMDestReg!"); 769 770 O << TII.getName(MI->getOpcode()) << " "; 771 printOp(MI->getOperand(0)); 772 O << ", "; 773 printOp(MI->getOperand(1)); 774 if (MI->getNumOperands() == 3) { 775 O << ", "; 776 printOp(MI->getOperand(2)); 777 } 778 printImplUsesAfter(Desc); 779 O << "\n"; 780 return; 781 } 782 783 case X86II::MRMDestMem: { 784 // These instructions are the same as MRMDestReg, but instead of having a 785 // register reference for the mod/rm field, it's a memory reference. 786 // 787 assert(isMem(MI, 0) && 788 (MI->getNumOperands() == 4+1 || 789 (MI->getNumOperands() == 4+2 && MI->getOperand(5).isImmediate())) 790 && "Bad format for MRMDestMem!"); 791 792 O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " "; 793 printMemReference(MI, 0); 794 O << ", "; 795 printOp(MI->getOperand(4)); 796 if (MI->getNumOperands() == 4+2) { 797 O << ", "; 798 printOp(MI->getOperand(5)); 799 } 800 printImplUsesAfter(Desc); 801 O << "\n"; 802 return; 803 } 804 805 case X86II::MRMSrcReg: { 806 // There are three forms that are acceptable for MRMSrcReg 807 // instructions, those with 2 or 3 operands: 808 // 809 // 2 Operands: this is for things like mov that do not read a 810 // second input. 811 // 812 // 2 Operands: in this form, the last register is the ModR/M 813 // input. The first operand is a def&use. This is for things 814 // like: add r32, r/m32 815 // 816 // 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used 817 // for instructions like the IMULrri instructions. 818 // 819 // 820 assert(MI->getOperand(0).isRegister() && 821 MI->getOperand(1).isRegister() && 822 (MI->getNumOperands() == 2 || 823 (MI->getNumOperands() == 3 && 824 (MI->getOperand(2).isImmediate()))) 825 && "Bad format for MRMSrcReg!"); 826 827 O << TII.getName(MI->getOpcode()) << " "; 828 printOp(MI->getOperand(0)); 829 O << ", "; 830 printOp(MI->getOperand(1)); 831 if (MI->getNumOperands() == 3) { 832 O << ", "; 833 printOp(MI->getOperand(2)); 834 } 835 O << "\n"; 836 return; 837 } 838 839 case X86II::MRMSrcMem: { 840 // These instructions are the same as MRMSrcReg, but instead of having a 841 // register reference for the mod/rm field, it's a memory reference. 842 // 843 assert(MI->getOperand(0).isRegister() && 844 ((MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 845 (MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && 846 isMem(MI, 1))) 847 && "Bad format for MRMSrcMem!"); 848 O << TII.getName(MI->getOpcode()) << " "; 849 printOp(MI->getOperand(0)); 850 O << ", " << sizePtr(Desc) << " "; 851 printMemReference(MI, 1); 852 if (MI->getNumOperands() == 2+4) { 853 O << ", "; 854 printOp(MI->getOperand(5)); 855 } 856 O << "\n"; 857 return; 858 } 859 860 case X86II::MRM0r: case X86II::MRM1r: 861 case X86II::MRM2r: case X86II::MRM3r: 862 case X86II::MRM4r: case X86II::MRM5r: 863 case X86II::MRM6r: case X86II::MRM7r: { 864 // In this form, the following are valid formats: 865 // 1. sete r 866 // 2. cmp reg, immediate 867 // 2. shl rdest, rinput <implicit CL or 1> 868 // 3. sbb rdest, rinput, immediate [rdest = rinput] 869 // 870 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && 871 MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); 872 assert((MI->getNumOperands() != 2 || 873 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& 874 "Bad MRMSxR format!"); 875 assert((MI->getNumOperands() < 3 || 876 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && 877 "Bad MRMSxR format!"); 878 879 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && 880 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 881 O << "**"; 882 883 O << TII.getName(MI->getOpcode()) << " "; 884 printOp(MI->getOperand(0)); 885 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { 886 O << ", "; 887 printOp(MI->getOperand(MI->getNumOperands()-1)); 888 } 889 printImplUsesAfter(Desc); 890 O << "\n"; 891 892 return; 893 } 894 895 case X86II::MRM0m: case X86II::MRM1m: 896 case X86II::MRM2m: case X86II::MRM3m: 897 case X86II::MRM4m: case X86II::MRM5m: 898 case X86II::MRM6m: case X86II::MRM7m: { 899 // In this form, the following are valid formats: 900 // 1. sete [m] 901 // 2. cmp [m], immediate 902 // 2. shl [m], rinput <implicit CL or 1> 903 // 3. sbb [m], immediate 904 // 905 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && 906 isMem(MI, 0) && "Bad MRMSxM format!"); 907 assert((MI->getNumOperands() != 5 || 908 (MI->getOperand(4).isImmediate() || 909 MI->getOperand(4).isGlobalAddress())) && 910 "Bad MRMSxM format!"); 911 912 const MachineOperand &Op3 = MI->getOperand(3); 913 914 // gas bugs: 915 // 916 // The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" 917 // is misassembled by gas in intel_syntax mode as its 32-bit 918 // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw 919 // opcode bytes instead of the instruction. 920 // 921 // The 80-bit FP load instruction "fld XWORD PTR [...]" is 922 // misassembled by gas in intel_syntax mode as its 32-bit 923 // equivalent "fld DWORD PTR [...]". Workaround: Output the raw 924 // opcode bytes instead of the instruction. 925 // 926 // gas intel_syntax mode treats "fild QWORD PTR [...]" as an 927 // invalid opcode, saying "64 bit operations are only supported in 928 // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR 929 // [...]", which is wrong. Workaround: Output the raw opcode bytes 930 // instead of the instruction. 931 // 932 // gas intel_syntax mode treats "fistp QWORD PTR [...]" as an 933 // invalid opcode, saying "64 bit operations are only supported in 934 // 64 bit modes." libopcodes disassembles it as "fistpll DWORD PTR 935 // [...]", which is wrong. Workaround: Output the raw opcode bytes 936 // instead of the instruction. 937 if (MI->getOpcode() == X86::FSTP80m || 938 MI->getOpcode() == X86::FLD80m || 939 MI->getOpcode() == X86::FILD64m || 940 MI->getOpcode() == X86::FISTP64m) { 941 GasBugWorkaroundEmitter gwe(O); 942 X86::emitInstruction(gwe, (X86InstrInfo&)*TM.getInstrInfo(), *MI); 943 } 944 945 O << TII.getName(MI->getOpcode()) << " "; 946 O << sizePtr(Desc) << " "; 947 printMemReference(MI, 0); 948 if (MI->getNumOperands() == 5) { 949 O << ", "; 950 printOp(MI->getOperand(4)); 951 } 952 printImplUsesAfter(Desc); 953 O << "\n"; 954 return; 955 } 956 default: 957 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, &TM); break; 958 } 959} 960 961bool X86AsmPrinter::doInitialization(Module &M) { 962 // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. 963 // 964 // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an 965 // instruction as a reference to the register named sp, and if you try to 966 // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased 967 // before being looked up in the symbol table. This creates spurious 968 // `undefined symbol' errors when linking. Workaround: Do not use `noprefix' 969 // mode, and decorate all register names with percent signs. 970 O << "\t.intel_syntax\n"; 971 Mang = new Mangler(M, EmitCygwin); 972 return false; // success 973} 974 975// SwitchSection - Switch to the specified section of the executable if we are 976// not already in it! 977// 978static void SwitchSection(std::ostream &OS, std::string &CurSection, 979 const char *NewSection) { 980 if (CurSection != NewSection) { 981 CurSection = NewSection; 982 if (!CurSection.empty()) 983 OS << "\t" << NewSection << "\n"; 984 } 985} 986 987bool X86AsmPrinter::doFinalization(Module &M) { 988 const TargetData &TD = TM.getTargetData(); 989 std::string CurSection; 990 991 // Print out module-level global variables here. 992 for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) 993 if (I->hasInitializer()) { // External global require no code 994 O << "\n\n"; 995 std::string name = Mang->getValueName(I); 996 Constant *C = I->getInitializer(); 997 unsigned Size = TD.getTypeSize(C->getType()); 998 unsigned Align = TD.getTypeAlignment(C->getType()); 999 1000 if (C->isNullValue() && 1001 (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || 1002 I->hasWeakLinkage() /* FIXME: Verify correct */)) { 1003 SwitchSection(O, CurSection, ".data"); 1004 if (I->hasInternalLinkage()) 1005 O << "\t.local " << name << "\n"; 1006 1007 O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) 1008 << "," << (unsigned)TD.getTypeAlignment(C->getType()); 1009 O << "\t\t# "; 1010 WriteAsOperand(O, I, true, true, &M); 1011 O << "\n"; 1012 } else { 1013 switch (I->getLinkage()) { 1014 case GlobalValue::LinkOnceLinkage: 1015 case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak. 1016 // Nonnull linkonce -> weak 1017 O << "\t.weak " << name << "\n"; 1018 SwitchSection(O, CurSection, ""); 1019 O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n"; 1020 break; 1021 1022 case GlobalValue::AppendingLinkage: 1023 // FIXME: appending linkage variables should go into a section of 1024 // their name or something. For now, just emit them as external. 1025 case GlobalValue::ExternalLinkage: 1026 // If external or appending, declare as a global symbol 1027 O << "\t.globl " << name << "\n"; 1028 // FALL THROUGH 1029 case GlobalValue::InternalLinkage: 1030 if (C->isNullValue()) 1031 SwitchSection(O, CurSection, ".bss"); 1032 else 1033 SwitchSection(O, CurSection, ".data"); 1034 break; 1035 } 1036 1037 O << "\t.align " << Align << "\n"; 1038 O << "\t.type " << name << ",@object\n"; 1039 O << "\t.size " << name << "," << Size << "\n"; 1040 O << name << ":\t\t\t\t# "; 1041 WriteAsOperand(O, I, true, true, &M); 1042 O << " = "; 1043 WriteAsOperand(O, C, false, false, &M); 1044 O << "\n"; 1045 emitGlobalConstant(C); 1046 } 1047 } 1048 1049 delete Mang; 1050 return false; // success 1051} 1052