X86AsmPrinter.cpp revision b708944fc2752ca7f100c5a3c1f6385229777ea1 
1//===-- X86/Printer.cpp - Convert X86 code to human readable rep. ---------===//
2//
3// This file contains a printer that converts from our internal representation
4// of LLVM code to a nice human readable form that is suitable for debuggging.
5//
6//===----------------------------------------------------------------------===//
7
8#include "X86.h"
9#include "X86InstrInfo.h"
10#include "llvm/Function.h"
11#include "llvm/Constant.h"
12#include "llvm/Target/TargetMachine.h"
13#include "llvm/CodeGen/MachineFunctionPass.h"
14#include "llvm/CodeGen/MachineConstantPool.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "Support/Statistic.h"
17
18namespace {
19  struct Printer : public MachineFunctionPass {
20    std::ostream &O;
21    unsigned ConstIdx;
22    Printer(std::ostream &o) : O(o), ConstIdx(0) {}
23
24    virtual const char *getPassName() const {
25      return "X86 Assembly Printer";
26    }
27
28    void printConstantPool(MachineConstantPool *MCP, const TargetData &TD);
29    bool runOnMachineFunction(MachineFunction &F);
30  };
31}
32
33/// createX86CodePrinterPass - Print out the specified machine code function to
34/// the specified stream.  This function should work regardless of whether or
35/// not the function is in SSA form or not.
36///
37Pass *createX86CodePrinterPass(std::ostream &O) {
38  return new Printer(O);
39}
40
41
42// printConstantPool - Print out any constants which have been spilled to
43// memory...
44void Printer::printConstantPool(MachineConstantPool *MCP, const TargetData &TD){
45  const std::vector<Constant*> &CP = MCP->getConstants();
46  if (CP.empty()) return;
47
48  for (unsigned i = 0, e = CP.size(); i != e; ++i) {
49    O << "\t.section .rodata\n";
50    O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) << "\n";
51    O << ".CPI" << i+ConstIdx << ":\t\t\t\t\t;" << *CP[i] << "\n";
52    O << "\t*Constant output not implemented yet!*\n\n";
53  }
54  ConstIdx += CP.size();  // Don't recycle constant pool index numbers
55}
56
57/// runOnFunction - This uses the X86InstructionInfo::print method
58/// to print assembly for each instruction.
59bool Printer::runOnMachineFunction(MachineFunction &MF) {
60  static unsigned BBNumber = 0;
61  const TargetMachine &TM = MF.getTarget();
62  const MachineInstrInfo &MII = TM.getInstrInfo();
63
64  // Print out constants referenced by the function
65  printConstantPool(MF.getConstantPool(), TM.getTargetData());
66
67  // Print out labels for the function.
68  O << "\t.text\n";
69  O << "\t.align 16\n";
70  O << "\t.globl\t" << MF.getFunction()->getName() << "\n";
71  O << "\t.type\t" << MF.getFunction()->getName() << ", @function\n";
72  O << MF.getFunction()->getName() << ":\n";
73
74  // Print out code for the function.
75  for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
76       I != E; ++I) {
77    // Print a label for the basic block.
78    O << ".BB" << BBNumber++ << ":\n";
79    for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
80	 II != E; ++II) {
81      // Print the assembly for the instruction.
82      O << "\t";
83      MII.print(*II, O, TM);
84    }
85  }
86
87  // We didn't modify anything.
88  return false;
89}
90
91static bool isScale(const MachineOperand &MO) {
92  return MO.isImmediate() &&
93           (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
94            MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
95}
96
97static bool isMem(const MachineInstr *MI, unsigned Op) {
98  if (MI->getOperand(Op).isFrameIndex()) return true;
99  if (MI->getOperand(Op).isConstantPoolIndex()) return true;
100  return Op+4 <= MI->getNumOperands() &&
101         MI->getOperand(Op  ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
102         MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
103}
104
105static void printOp(std::ostream &O, const MachineOperand &MO,
106                    const MRegisterInfo &RI) {
107  switch (MO.getType()) {
108  case MachineOperand::MO_VirtualRegister:
109    if (Value *V = MO.getVRegValueOrNull()) {
110      O << "<" << V->getName() << ">";
111      return;
112    }
113    // FALLTHROUGH
114  case MachineOperand::MO_MachineRegister:
115    if (MO.getReg() < MRegisterInfo::FirstVirtualRegister)
116      O << RI.get(MO.getReg()).Name;
117    else
118      O << "%reg" << MO.getReg();
119    return;
120
121  case MachineOperand::MO_SignExtendedImmed:
122  case MachineOperand::MO_UnextendedImmed:
123    O << (int)MO.getImmedValue();
124    return;
125  case MachineOperand::MO_PCRelativeDisp:
126    O << "<" << MO.getVRegValue()->getName() << ">";
127    return;
128  case MachineOperand::MO_GlobalAddress:
129    O << "<" << MO.getGlobal()->getName() << ">";
130    return;
131  case MachineOperand::MO_ExternalSymbol:
132    O << "<" << MO.getSymbolName() << ">";
133    return;
134  default:
135    O << "<unknown op ty>"; return;
136  }
137}
138
139static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
140  switch (Desc.TSFlags & X86II::ArgMask) {
141    default: assert(0 && "Unknown arg size!");
142    case X86II::Arg8:   return "BYTE PTR";
143    case X86II::Arg16:  return "WORD PTR";
144    case X86II::Arg32:  return "DWORD PTR";
145    case X86II::Arg64:  return "QWORD PTR";
146    case X86II::ArgF32:  return "DWORD PTR";
147    case X86II::ArgF64:  return "QWORD PTR";
148    case X86II::ArgF80:  return "XWORD PTR";
149  }
150}
151
152static void printMemReference(std::ostream &O, const MachineInstr *MI,
153                              unsigned Op, const MRegisterInfo &RI) {
154  assert(isMem(MI, Op) && "Invalid memory reference!");
155
156  if (MI->getOperand(Op).isFrameIndex()) {
157    O << "[frame slot #" << MI->getOperand(Op).getFrameIndex();
158    if (MI->getOperand(Op+3).getImmedValue())
159      O << " + " << MI->getOperand(Op+3).getImmedValue();
160    O << "]";
161    return;
162  } else if (MI->getOperand(Op).isConstantPoolIndex()) {
163    O << "[.CPI" << MI->getOperand(Op).getConstantPoolIndex();
164    if (MI->getOperand(Op+3).getImmedValue())
165      O << " + " << MI->getOperand(Op+3).getImmedValue();
166    O << "]";
167    return;
168  }
169
170  const MachineOperand &BaseReg  = MI->getOperand(Op);
171  int ScaleVal                   = MI->getOperand(Op+1).getImmedValue();
172  const MachineOperand &IndexReg = MI->getOperand(Op+2);
173  int DispVal                    = MI->getOperand(Op+3).getImmedValue();
174
175  O << "[";
176  bool NeedPlus = false;
177  if (BaseReg.getReg()) {
178    printOp(O, BaseReg, RI);
179    NeedPlus = true;
180  }
181
182  if (IndexReg.getReg()) {
183    if (NeedPlus) O << " + ";
184    if (ScaleVal != 1)
185      O << ScaleVal << "*";
186    printOp(O, IndexReg, RI);
187    NeedPlus = true;
188  }
189
190  if (DispVal) {
191    if (NeedPlus)
192      if (DispVal > 0)
193	O << " + ";
194      else {
195	O << " - ";
196	DispVal = -DispVal;
197      }
198    O << DispVal;
199  }
200  O << "]";
201}
202
203// print - Print out an x86 instruction in intel syntax
204void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
205                         const TargetMachine &TM) const {
206  unsigned Opcode = MI->getOpcode();
207  const MachineInstrDescriptor &Desc = get(Opcode);
208
209  switch (Desc.TSFlags & X86II::FormMask) {
210  case X86II::Pseudo:
211    if (Opcode == X86::PHI) {
212      printOp(O, MI->getOperand(0), RI);
213      O << " = phi ";
214      for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
215	if (i != 1) O << ", ";
216	O << "[";
217	printOp(O, MI->getOperand(i), RI);
218	O << ", ";
219	printOp(O, MI->getOperand(i+1), RI);
220	O << "]";
221      }
222    } else {
223      unsigned i = 0;
224      if (MI->getNumOperands() && MI->getOperand(0).opIsDef()) {
225	printOp(O, MI->getOperand(0), RI);
226	O << " = ";
227	++i;
228      }
229      O << getName(MI->getOpcode());
230
231      for (unsigned e = MI->getNumOperands(); i != e; ++i) {
232	O << " ";
233	if (MI->getOperand(i).opIsDef()) O << "*";
234	printOp(O, MI->getOperand(i), RI);
235	if (MI->getOperand(i).opIsDef()) O << "*";
236      }
237    }
238    O << "\n";
239    return;
240
241  case X86II::RawFrm:
242    // The accepted forms of Raw instructions are:
243    //   1. nop     - No operand required
244    //   2. jmp foo - PC relative displacement operand
245    //   3. call bar - GlobalAddress Operand or External Symbol Operand
246    //
247    assert(MI->getNumOperands() == 0 ||
248           (MI->getNumOperands() == 1 &&
249	    (MI->getOperand(0).isPCRelativeDisp() ||
250	     MI->getOperand(0).isGlobalAddress() ||
251	     MI->getOperand(0).isExternalSymbol())) &&
252           "Illegal raw instruction!");
253    O << getName(MI->getOpcode()) << " ";
254
255    if (MI->getNumOperands() == 1) {
256      printOp(O, MI->getOperand(0), RI);
257    }
258    O << "\n";
259    return;
260
261  case X86II::AddRegFrm: {
262    // There are currently two forms of acceptable AddRegFrm instructions.
263    // Either the instruction JUST takes a single register (like inc, dec, etc),
264    // or it takes a register and an immediate of the same size as the register
265    // (move immediate f.e.).  Note that this immediate value might be stored as
266    // an LLVM value, to represent, for example, loading the address of a global
267    // into a register.  The initial register might be duplicated if this is a
268    // M_2_ADDR_REG instruction
269    //
270    assert(MI->getOperand(0).isRegister() &&
271           (MI->getNumOperands() == 1 ||
272            (MI->getNumOperands() == 2 &&
273             (MI->getOperand(1).getVRegValueOrNull() ||
274              MI->getOperand(1).isImmediate() ||
275	      MI->getOperand(1).isRegister() ||
276	      MI->getOperand(1).isGlobalAddress() ||
277	      MI->getOperand(1).isExternalSymbol()))) &&
278           "Illegal form for AddRegFrm instruction!");
279
280    unsigned Reg = MI->getOperand(0).getReg();
281
282    O << getName(MI->getOpCode()) << " ";
283    printOp(O, MI->getOperand(0), RI);
284    if (MI->getNumOperands() == 2 &&
285	(!MI->getOperand(1).isRegister() ||
286	 MI->getOperand(1).getVRegValueOrNull() ||
287	 MI->getOperand(1).isGlobalAddress() ||
288	 MI->getOperand(1).isExternalSymbol())) {
289      O << ", ";
290      printOp(O, MI->getOperand(1), RI);
291    }
292    O << "\n";
293    return;
294  }
295  case X86II::MRMDestReg: {
296    // There are two acceptable forms of MRMDestReg instructions, those with 2,
297    // 3 and 4 operands:
298    //
299    // 2 Operands: this is for things like mov that do not read a second input
300    //
301    // 3 Operands: in this form, the first two registers (the destination, and
302    // the first operand) should be the same, post register allocation.  The 3rd
303    // operand is an additional input.  This should be for things like add
304    // instructions.
305    //
306    // 4 Operands: This form is for instructions which are 3 operands forms, but
307    // have a constant argument as well.
308    //
309    bool isTwoAddr = isTwoAddrInstr(Opcode);
310    assert(MI->getOperand(0).isRegister() &&
311           (MI->getNumOperands() == 2 ||
312	    (isTwoAddr && MI->getOperand(1).isRegister() &&
313	     MI->getOperand(0).getReg() == MI->getOperand(1).getReg() &&
314	     (MI->getNumOperands() == 3 ||
315	      (MI->getNumOperands() == 4 && MI->getOperand(3).isImmediate()))))
316           && "Bad format for MRMDestReg!");
317
318    O << getName(MI->getOpCode()) << " ";
319    printOp(O, MI->getOperand(0), RI);
320    O << ", ";
321    printOp(O, MI->getOperand(1+isTwoAddr), RI);
322    if (MI->getNumOperands() == 4) {
323      O << ", ";
324      printOp(O, MI->getOperand(3), RI);
325    }
326    O << "\n";
327    return;
328  }
329
330  case X86II::MRMDestMem: {
331    // These instructions are the same as MRMDestReg, but instead of having a
332    // register reference for the mod/rm field, it's a memory reference.
333    //
334    assert(isMem(MI, 0) && MI->getNumOperands() == 4+1 &&
335           MI->getOperand(4).isRegister() && "Bad format for MRMDestMem!");
336
337    O << getName(MI->getOpCode()) << " " << sizePtr(Desc) << " ";
338    printMemReference(O, MI, 0, RI);
339    O << ", ";
340    printOp(O, MI->getOperand(4), RI);
341    O << "\n";
342    return;
343  }
344
345  case X86II::MRMSrcReg: {
346    // There is a two forms that are acceptable for MRMSrcReg instructions,
347    // those with 3 and 2 operands:
348    //
349    // 3 Operands: in this form, the last register (the second input) is the
350    // ModR/M input.  The first two operands should be the same, post register
351    // allocation.  This is for things like: add r32, r/m32
352    //
353    // 2 Operands: this is for things like mov that do not read a second input
354    //
355    assert(MI->getOperand(0).isRegister() &&
356           MI->getOperand(1).isRegister() &&
357           (MI->getNumOperands() == 2 ||
358            (MI->getNumOperands() == 3 && MI->getOperand(2).isRegister()))
359           && "Bad format for MRMSrcReg!");
360    if (MI->getNumOperands() == 3 &&
361        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
362      O << "**";
363
364    O << getName(MI->getOpCode()) << " ";
365    printOp(O, MI->getOperand(0), RI);
366    O << ", ";
367    printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
368    O << "\n";
369    return;
370  }
371
372  case X86II::MRMSrcMem: {
373    // These instructions are the same as MRMSrcReg, but instead of having a
374    // register reference for the mod/rm field, it's a memory reference.
375    //
376    assert(MI->getOperand(0).isRegister() &&
377           (MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
378           (MI->getNumOperands() == 2+4 && MI->getOperand(1).isRegister() &&
379            isMem(MI, 2))
380           && "Bad format for MRMDestReg!");
381    if (MI->getNumOperands() == 2+4 &&
382        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
383      O << "**";
384
385    O << getName(MI->getOpCode()) << " ";
386    printOp(O, MI->getOperand(0), RI);
387    O << ", " << sizePtr(Desc) << " ";
388    printMemReference(O, MI, MI->getNumOperands()-4, RI);
389    O << "\n";
390    return;
391  }
392
393  case X86II::MRMS0r: case X86II::MRMS1r:
394  case X86II::MRMS2r: case X86II::MRMS3r:
395  case X86II::MRMS4r: case X86II::MRMS5r:
396  case X86II::MRMS6r: case X86II::MRMS7r: {
397    // In this form, the following are valid formats:
398    //  1. sete r
399    //  2. cmp reg, immediate
400    //  2. shl rdest, rinput  <implicit CL or 1>
401    //  3. sbb rdest, rinput, immediate   [rdest = rinput]
402    //
403    assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
404           MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
405    assert((MI->getNumOperands() != 2 ||
406            MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
407           "Bad MRMSxR format!");
408    assert((MI->getNumOperands() < 3 ||
409        (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
410           "Bad MRMSxR format!");
411
412    if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
413        MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
414      O << "**";
415
416    O << getName(MI->getOpCode()) << " ";
417    printOp(O, MI->getOperand(0), RI);
418    if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
419      O << ", ";
420      printOp(O, MI->getOperand(MI->getNumOperands()-1), RI);
421    }
422    O << "\n";
423
424    return;
425  }
426
427  case X86II::MRMS0m: case X86II::MRMS1m:
428  case X86II::MRMS2m: case X86II::MRMS3m:
429  case X86II::MRMS4m: case X86II::MRMS5m:
430  case X86II::MRMS6m: case X86II::MRMS7m: {
431    // In this form, the following are valid formats:
432    //  1. sete [m]
433    //  2. cmp [m], immediate
434    //  2. shl [m], rinput  <implicit CL or 1>
435    //  3. sbb [m], immediate
436    //
437    assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
438           isMem(MI, 0) && "Bad MRMSxM format!");
439    assert((MI->getNumOperands() != 5 || MI->getOperand(4).isImmediate()) &&
440           "Bad MRMSxM format!");
441
442    O << getName(MI->getOpCode()) << " ";
443    O << sizePtr(Desc) << " ";
444    printMemReference(O, MI, 0, RI);
445    if (MI->getNumOperands() == 5) {
446      O << ", ";
447      printOp(O, MI->getOperand(4), RI);
448    }
449    O << "\n";
450    return;
451  }
452
453  default:
454    O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
455  }
456}
457