X86AsmPrinter.cpp revision db760d00c3db53e600a0fd4050f0be29bfc79b2c
1//===-- X86/Printer.cpp - Convert X86 LLVM code to Intel assembly ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains a printer that converts from our internal representation 11// of machine-dependent LLVM code to Intel-format assembly language. This 12// printer is the output mechanism used by `llc' and `lli -print-machineinstrs' 13// on X86. 14// 15//===----------------------------------------------------------------------===// 16 17#include "X86.h" 18#include "X86InstrInfo.h" 19#include "X86TargetMachine.h" 20#include "llvm/Constants.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/Module.h" 23#include "llvm/Assembly/Writer.h" 24#include "llvm/CodeGen/MachineCodeEmitter.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFunctionPass.h" 27#include "llvm/CodeGen/MachineInstr.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Support/Mangler.h" 30#include "Support/Statistic.h" 31#include "Support/StringExtras.h" 32#include "Support/CommandLine.h" 33using namespace llvm; 34 35namespace { 36 Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); 37 38 // FIXME: This should be automatically picked up by autoconf from the C 39 // frontend 40 cl::opt<bool> EmitCygwin("enable-cygwin-compatible-output", cl::Hidden, 41 cl::desc("Emit X86 assembly code suitable for consumption by cygwin")); 42 43 struct GasBugWorkaroundEmitter : public MachineCodeEmitter { 44 GasBugWorkaroundEmitter(std::ostream& o) 45 : O(o), OldFlags(O.flags()), firstByte(true) { 46 O << std::hex; 47 } 48 49 ~GasBugWorkaroundEmitter() { 50 O.flags(OldFlags); 51 O << "\t# "; 52 } 53 54 virtual void emitByte(unsigned char B) { 55 if (!firstByte) O << "\n\t"; 56 firstByte = false; 57 O << ".byte 0x" << (unsigned) B; 58 } 59 60 // These should never be called 61 virtual void emitWord(unsigned W) { assert(0); } 62 virtual uint64_t getGlobalValueAddress(GlobalValue *V) { abort(); } 63 virtual uint64_t getGlobalValueAddress(const std::string &Name) { abort(); } 64 virtual uint64_t getConstantPoolEntryAddress(unsigned Index) { abort(); } 65 virtual uint64_t getCurrentPCValue() { abort(); } 66 virtual uint64_t forceCompilationOf(Function *F) { abort(); } 67 68 private: 69 std::ostream& O; 70 std::ios::fmtflags OldFlags; 71 bool firstByte; 72 }; 73 74 struct Printer : public MachineFunctionPass { 75 /// Output stream on which we're printing assembly code. 76 /// 77 std::ostream &O; 78 79 /// Target machine description which we query for reg. names, data 80 /// layout, etc. 81 /// 82 TargetMachine &TM; 83 84 /// Name-mangler for global names. 85 /// 86 Mangler *Mang; 87 88 Printer(std::ostream &o, TargetMachine &tm) : O(o), TM(tm) { } 89 90 /// We name each basic block in a Function with a unique number, so 91 /// that we can consistently refer to them later. This is cleared 92 /// at the beginning of each call to runOnMachineFunction(). 93 /// 94 typedef std::map<const Value *, unsigned> ValueMapTy; 95 ValueMapTy NumberForBB; 96 97 /// Cache of mangled name for current function. This is 98 /// recalculated at the beginning of each call to 99 /// runOnMachineFunction(). 100 /// 101 std::string CurrentFnName; 102 103 virtual const char *getPassName() const { 104 return "X86 Assembly Printer"; 105 } 106 107 void checkImplUses (const TargetInstrDescriptor &Desc); 108 void printMachineInstruction(const MachineInstr *MI); 109 void printOp(const MachineOperand &MO, 110 bool elideOffsetKeyword = false); 111 void printMemReference(const MachineInstr *MI, unsigned Op); 112 void printConstantPool(MachineConstantPool *MCP); 113 bool runOnMachineFunction(MachineFunction &F); 114 bool doInitialization(Module &M); 115 bool doFinalization(Module &M); 116 void emitGlobalConstant(const Constant* CV); 117 void emitConstantValueOnly(const Constant *CV); 118 }; 119} // end of anonymous namespace 120 121/// createX86CodePrinterPass - Returns a pass that prints the X86 122/// assembly code for a MachineFunction to the given output stream, 123/// using the given target machine description. This should work 124/// regardless of whether the function is in SSA form. 125/// 126FunctionPass *llvm::createX86CodePrinterPass(std::ostream &o,TargetMachine &tm){ 127 return new Printer(o, tm); 128} 129 130/// toOctal - Convert the low order bits of X into an octal digit. 131/// 132static inline char toOctal(int X) { 133 return (X&7)+'0'; 134} 135 136/// getAsCString - Return the specified array as a C compatible 137/// string, only if the predicate isStringCompatible is true. 138/// 139static void printAsCString(std::ostream &O, const ConstantArray *CVA) { 140 assert(CVA->isString() && "Array is not string compatible!"); 141 142 O << "\""; 143 for (unsigned i = 0; i != CVA->getNumOperands(); ++i) { 144 unsigned char C = cast<ConstantInt>(CVA->getOperand(i))->getRawValue(); 145 146 if (C == '"') { 147 O << "\\\""; 148 } else if (C == '\\') { 149 O << "\\\\"; 150 } else if (isprint(C)) { 151 O << C; 152 } else { 153 switch(C) { 154 case '\b': O << "\\b"; break; 155 case '\f': O << "\\f"; break; 156 case '\n': O << "\\n"; break; 157 case '\r': O << "\\r"; break; 158 case '\t': O << "\\t"; break; 159 default: 160 O << '\\'; 161 O << toOctal(C >> 6); 162 O << toOctal(C >> 3); 163 O << toOctal(C >> 0); 164 break; 165 } 166 } 167 } 168 O << "\""; 169} 170 171// Print out the specified constant, without a storage class. Only the 172// constants valid in constant expressions can occur here. 173void Printer::emitConstantValueOnly(const Constant *CV) { 174 if (CV->isNullValue()) 175 O << "0"; 176 else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) { 177 assert(CB == ConstantBool::True); 178 O << "1"; 179 } else if (const ConstantSInt *CI = dyn_cast<ConstantSInt>(CV)) 180 if (((CI->getValue() << 32) >> 32) == CI->getValue()) 181 O << CI->getValue(); 182 else 183 O << (unsigned long long)CI->getValue(); 184 else if (const ConstantUInt *CI = dyn_cast<ConstantUInt>(CV)) 185 O << CI->getValue(); 186 else if (const ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(CV)) 187 // This is a constant address for a global variable or function. Use the 188 // name of the variable or function as the address value. 189 O << Mang->getValueName(CPR->getValue()); 190 else if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(CV)) { 191 const TargetData &TD = TM.getTargetData(); 192 switch(CE->getOpcode()) { 193 case Instruction::GetElementPtr: { 194 // generate a symbolic expression for the byte address 195 const Constant *ptrVal = CE->getOperand(0); 196 std::vector<Value*> idxVec(CE->op_begin()+1, CE->op_end()); 197 if (unsigned Offset = TD.getIndexedOffset(ptrVal->getType(), idxVec)) { 198 O << "("; 199 emitConstantValueOnly(ptrVal); 200 O << ") + " << Offset; 201 } else { 202 emitConstantValueOnly(ptrVal); 203 } 204 break; 205 } 206 case Instruction::Cast: { 207 // Support only non-converting or widening casts for now, that is, ones 208 // that do not involve a change in value. This assertion is really gross, 209 // and may not even be a complete check. 210 Constant *Op = CE->getOperand(0); 211 const Type *OpTy = Op->getType(), *Ty = CE->getType(); 212 213 // Remember, kids, pointers on x86 can be losslessly converted back and 214 // forth into 32-bit or wider integers, regardless of signedness. :-P 215 assert(((isa<PointerType>(OpTy) 216 && (Ty == Type::LongTy || Ty == Type::ULongTy 217 || Ty == Type::IntTy || Ty == Type::UIntTy)) 218 || (isa<PointerType>(Ty) 219 && (OpTy == Type::LongTy || OpTy == Type::ULongTy 220 || OpTy == Type::IntTy || OpTy == Type::UIntTy)) 221 || (((TD.getTypeSize(Ty) >= TD.getTypeSize(OpTy)) 222 && OpTy->isLosslesslyConvertibleTo(Ty)))) 223 && "FIXME: Don't yet support this kind of constant cast expr"); 224 O << "("; 225 emitConstantValueOnly(Op); 226 O << ")"; 227 break; 228 } 229 case Instruction::Add: 230 O << "("; 231 emitConstantValueOnly(CE->getOperand(0)); 232 O << ") + ("; 233 emitConstantValueOnly(CE->getOperand(1)); 234 O << ")"; 235 break; 236 default: 237 assert(0 && "Unsupported operator!"); 238 } 239 } else { 240 assert(0 && "Unknown constant value!"); 241 } 242} 243 244// Print a constant value or values, with the appropriate storage class as a 245// prefix. 246void Printer::emitGlobalConstant(const Constant *CV) { 247 const TargetData &TD = TM.getTargetData(); 248 249 if (CV->isNullValue()) { 250 O << "\t.zero\t " << TD.getTypeSize(CV->getType()) << "\n"; 251 return; 252 } else if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) { 253 if (CVA->isString()) { 254 O << "\t.ascii\t"; 255 printAsCString(O, CVA); 256 O << "\n"; 257 } else { // Not a string. Print the values in successive locations 258 const std::vector<Use> &constValues = CVA->getValues(); 259 for (unsigned i=0; i < constValues.size(); i++) 260 emitGlobalConstant(cast<Constant>(constValues[i].get())); 261 } 262 return; 263 } else if (const ConstantStruct *CVS = dyn_cast<ConstantStruct>(CV)) { 264 // Print the fields in successive locations. Pad to align if needed! 265 const StructLayout *cvsLayout = TD.getStructLayout(CVS->getType()); 266 const std::vector<Use>& constValues = CVS->getValues(); 267 unsigned sizeSoFar = 0; 268 for (unsigned i=0, N = constValues.size(); i < N; i++) { 269 const Constant* field = cast<Constant>(constValues[i].get()); 270 271 // Check if padding is needed and insert one or more 0s. 272 unsigned fieldSize = TD.getTypeSize(field->getType()); 273 unsigned padSize = ((i == N-1? cvsLayout->StructSize 274 : cvsLayout->MemberOffsets[i+1]) 275 - cvsLayout->MemberOffsets[i]) - fieldSize; 276 sizeSoFar += fieldSize + padSize; 277 278 // Now print the actual field value 279 emitGlobalConstant(field); 280 281 // Insert the field padding unless it's zero bytes... 282 if (padSize) 283 O << "\t.zero\t " << padSize << "\n"; 284 } 285 assert(sizeSoFar == cvsLayout->StructSize && 286 "Layout of constant struct may be incorrect!"); 287 return; 288 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 289 // FP Constants are printed as integer constants to avoid losing 290 // precision... 291 double Val = CFP->getValue(); 292 switch (CFP->getType()->getPrimitiveID()) { 293 default: assert(0 && "Unknown floating point type!"); 294 case Type::FloatTyID: { 295 union FU { // Abide by C TBAA rules 296 float FVal; 297 unsigned UVal; 298 } U; 299 U.FVal = Val; 300 O << ".long\t" << U.UVal << "\t# float " << Val << "\n"; 301 return; 302 } 303 case Type::DoubleTyID: { 304 union DU { // Abide by C TBAA rules 305 double FVal; 306 uint64_t UVal; 307 } U; 308 U.FVal = Val; 309 O << ".quad\t" << U.UVal << "\t# double " << Val << "\n"; 310 return; 311 } 312 } 313 } 314 315 const Type *type = CV->getType(); 316 O << "\t"; 317 switch (type->getPrimitiveID()) { 318 case Type::BoolTyID: case Type::UByteTyID: case Type::SByteTyID: 319 O << ".byte"; 320 break; 321 case Type::UShortTyID: case Type::ShortTyID: 322 O << ".word"; 323 break; 324 case Type::FloatTyID: case Type::PointerTyID: 325 case Type::UIntTyID: case Type::IntTyID: 326 O << ".long"; 327 break; 328 case Type::DoubleTyID: 329 case Type::ULongTyID: case Type::LongTyID: 330 O << ".quad"; 331 break; 332 default: 333 assert (0 && "Can't handle printing this type of thing"); 334 break; 335 } 336 O << "\t"; 337 emitConstantValueOnly(CV); 338 O << "\n"; 339} 340 341/// printConstantPool - Print to the current output stream assembly 342/// representations of the constants in the constant pool MCP. This is 343/// used to print out constants which have been "spilled to memory" by 344/// the code generator. 345/// 346void Printer::printConstantPool(MachineConstantPool *MCP) { 347 const std::vector<Constant*> &CP = MCP->getConstants(); 348 const TargetData &TD = TM.getTargetData(); 349 350 if (CP.empty()) return; 351 352 for (unsigned i = 0, e = CP.size(); i != e; ++i) { 353 O << "\t.section .rodata\n"; 354 O << "\t.align " << (unsigned)TD.getTypeAlignment(CP[i]->getType()) 355 << "\n"; 356 O << ".CPI" << CurrentFnName << "_" << i << ":\t\t\t\t\t#" 357 << *CP[i] << "\n"; 358 emitGlobalConstant(CP[i]); 359 } 360} 361 362/// runOnMachineFunction - This uses the printMachineInstruction() 363/// method to print assembly for each instruction. 364/// 365bool Printer::runOnMachineFunction(MachineFunction &MF) { 366 // BBNumber is used here so that a given Printer will never give two 367 // BBs the same name. (If you have a better way, please let me know!) 368 static unsigned BBNumber = 0; 369 370 O << "\n\n"; 371 // What's my mangled name? 372 CurrentFnName = Mang->getValueName(MF.getFunction()); 373 374 // Print out constants referenced by the function 375 printConstantPool(MF.getConstantPool()); 376 377 // Print out labels for the function. 378 O << "\t.text\n"; 379 O << "\t.align 16\n"; 380 O << "\t.globl\t" << CurrentFnName << "\n"; 381 if (!EmitCygwin) 382 O << "\t.type\t" << CurrentFnName << ", @function\n"; 383 O << CurrentFnName << ":\n"; 384 385 // Number each basic block so that we can consistently refer to them 386 // in PC-relative references. 387 NumberForBB.clear(); 388 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 389 I != E; ++I) { 390 NumberForBB[I->getBasicBlock()] = BBNumber++; 391 } 392 393 // Print out code for the function. 394 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end(); 395 I != E; ++I) { 396 // Print a label for the basic block. 397 O << ".LBB" << NumberForBB[I->getBasicBlock()] << ":\t# " 398 << I->getBasicBlock()->getName() << "\n"; 399 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end(); 400 II != E; ++II) { 401 // Print the assembly for the instruction. 402 O << "\t"; 403 printMachineInstruction(II); 404 } 405 } 406 407 // We didn't modify anything. 408 return false; 409} 410 411static bool isScale(const MachineOperand &MO) { 412 return MO.isImmediate() && 413 (MO.getImmedValue() == 1 || MO.getImmedValue() == 2 || 414 MO.getImmedValue() == 4 || MO.getImmedValue() == 8); 415} 416 417static bool isMem(const MachineInstr *MI, unsigned Op) { 418 if (MI->getOperand(Op).isFrameIndex()) return true; 419 if (MI->getOperand(Op).isConstantPoolIndex()) return true; 420 return Op+4 <= MI->getNumOperands() && 421 MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) && 422 MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate(); 423} 424 425 426 427void Printer::printOp(const MachineOperand &MO, 428 bool elideOffsetKeyword /* = false */) { 429 const MRegisterInfo &RI = *TM.getRegisterInfo(); 430 switch (MO.getType()) { 431 case MachineOperand::MO_VirtualRegister: 432 if (Value *V = MO.getVRegValueOrNull()) { 433 O << "<" << V->getName() << ">"; 434 return; 435 } 436 // FALLTHROUGH 437 case MachineOperand::MO_MachineRegister: 438 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) 439 // Bug Workaround: See note in Printer::doInitialization about %. 440 O << "%" << RI.get(MO.getReg()).Name; 441 else 442 O << "%reg" << MO.getReg(); 443 return; 444 445 case MachineOperand::MO_SignExtendedImmed: 446 case MachineOperand::MO_UnextendedImmed: 447 O << (int)MO.getImmedValue(); 448 return; 449 case MachineOperand::MO_PCRelativeDisp: { 450 ValueMapTy::const_iterator i = NumberForBB.find(MO.getVRegValue()); 451 assert (i != NumberForBB.end() 452 && "Could not find a BB in the NumberForBB map!"); 453 O << ".LBB" << i->second << " # PC rel: " << MO.getVRegValue()->getName(); 454 return; 455 } 456 case MachineOperand::MO_GlobalAddress: 457 if (!elideOffsetKeyword) 458 O << "OFFSET "; 459 O << Mang->getValueName(MO.getGlobal()); 460 return; 461 case MachineOperand::MO_ExternalSymbol: 462 O << MO.getSymbolName(); 463 return; 464 default: 465 O << "<unknown operand type>"; return; 466 } 467} 468 469static const char* const sizePtr(const TargetInstrDescriptor &Desc) { 470 switch (Desc.TSFlags & X86II::MemMask) { 471 default: assert(0 && "Unknown arg size!"); 472 case X86II::Mem8: return "BYTE PTR"; 473 case X86II::Mem16: return "WORD PTR"; 474 case X86II::Mem32: return "DWORD PTR"; 475 case X86II::Mem64: return "QWORD PTR"; 476 case X86II::Mem80: return "XWORD PTR"; 477 } 478} 479 480void Printer::printMemReference(const MachineInstr *MI, unsigned Op) { 481 assert(isMem(MI, Op) && "Invalid memory reference!"); 482 483 if (MI->getOperand(Op).isFrameIndex()) { 484 O << "[frame slot #" << MI->getOperand(Op).getFrameIndex(); 485 if (MI->getOperand(Op+3).getImmedValue()) 486 O << " + " << MI->getOperand(Op+3).getImmedValue(); 487 O << "]"; 488 return; 489 } else if (MI->getOperand(Op).isConstantPoolIndex()) { 490 O << "[.CPI" << CurrentFnName << "_" 491 << MI->getOperand(Op).getConstantPoolIndex(); 492 if (MI->getOperand(Op+3).getImmedValue()) 493 O << " + " << MI->getOperand(Op+3).getImmedValue(); 494 O << "]"; 495 return; 496 } 497 498 const MachineOperand &BaseReg = MI->getOperand(Op); 499 int ScaleVal = MI->getOperand(Op+1).getImmedValue(); 500 const MachineOperand &IndexReg = MI->getOperand(Op+2); 501 int DispVal = MI->getOperand(Op+3).getImmedValue(); 502 503 O << "["; 504 bool NeedPlus = false; 505 if (BaseReg.getReg()) { 506 printOp(BaseReg); 507 NeedPlus = true; 508 } 509 510 if (IndexReg.getReg()) { 511 if (NeedPlus) O << " + "; 512 if (ScaleVal != 1) 513 O << ScaleVal << "*"; 514 printOp(IndexReg); 515 NeedPlus = true; 516 } 517 518 if (DispVal) { 519 if (NeedPlus) 520 if (DispVal > 0) 521 O << " + "; 522 else { 523 O << " - "; 524 DispVal = -DispVal; 525 } 526 O << DispVal; 527 } 528 O << "]"; 529} 530 531/// checkImplUses - Emit the implicit-use registers for the 532/// instruction described by DESC, if its PrintImplUses flag is set. 533/// 534void Printer::checkImplUses (const TargetInstrDescriptor &Desc) { 535 const MRegisterInfo &RI = *TM.getRegisterInfo(); 536 if (Desc.TSFlags & X86II::PrintImplUses) { 537 for (const unsigned *p = Desc.ImplicitUses; *p; ++p) { 538 // Bug Workaround: See note in Printer::doInitialization about %. 539 O << ", %" << RI.get(*p).Name; 540 } 541 } 542} 543 544/// printMachineInstruction -- Print out a single X86 LLVM instruction 545/// MI in Intel syntax to the current output stream. 546/// 547void Printer::printMachineInstruction(const MachineInstr *MI) { 548 unsigned Opcode = MI->getOpcode(); 549 const TargetInstrInfo &TII = TM.getInstrInfo(); 550 const TargetInstrDescriptor &Desc = TII.get(Opcode); 551 552 ++EmittedInsts; 553 switch (Desc.TSFlags & X86II::FormMask) { 554 case X86II::Pseudo: 555 // Print pseudo-instructions as comments; either they should have been 556 // turned into real instructions by now, or they don't need to be 557 // seen by the assembler (e.g., IMPLICIT_USEs.) 558 O << "# "; 559 if (Opcode == X86::PHI) { 560 printOp(MI->getOperand(0)); 561 O << " = phi "; 562 for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) { 563 if (i != 1) O << ", "; 564 O << "["; 565 printOp(MI->getOperand(i)); 566 O << ", "; 567 printOp(MI->getOperand(i+1)); 568 O << "]"; 569 } 570 } else { 571 unsigned i = 0; 572 if (MI->getNumOperands() && MI->getOperand(0).isDef()) { 573 printOp(MI->getOperand(0)); 574 O << " = "; 575 ++i; 576 } 577 O << TII.getName(MI->getOpcode()); 578 579 for (unsigned e = MI->getNumOperands(); i != e; ++i) { 580 O << " "; 581 if (MI->getOperand(i).isDef()) O << "*"; 582 printOp(MI->getOperand(i)); 583 if (MI->getOperand(i).isDef()) O << "*"; 584 } 585 } 586 O << "\n"; 587 return; 588 589 case X86II::RawFrm: 590 // The accepted forms of Raw instructions are: 591 // 1. nop - No operand required 592 // 2. jmp foo - PC relative displacement operand 593 // 3. call bar - GlobalAddress Operand or External Symbol Operand 594 // 595 assert(MI->getNumOperands() == 0 || 596 (MI->getNumOperands() == 1 && 597 (MI->getOperand(0).isPCRelativeDisp() || 598 MI->getOperand(0).isGlobalAddress() || 599 MI->getOperand(0).isExternalSymbol())) && 600 "Illegal raw instruction!"); 601 O << TII.getName(MI->getOpcode()) << " "; 602 603 if (MI->getNumOperands() == 1) { 604 printOp(MI->getOperand(0), true); // Don't print "OFFSET"... 605 } 606 O << "\n"; 607 return; 608 609 case X86II::AddRegFrm: { 610 // There are currently two forms of acceptable AddRegFrm instructions. 611 // Either the instruction JUST takes a single register (like inc, dec, etc), 612 // or it takes a register and an immediate of the same size as the register 613 // (move immediate f.e.). Note that this immediate value might be stored as 614 // an LLVM value, to represent, for example, loading the address of a global 615 // into a register. The initial register might be duplicated if this is a 616 // M_2_ADDR_REG instruction 617 // 618 assert(MI->getOperand(0).isRegister() && 619 (MI->getNumOperands() == 1 || 620 (MI->getNumOperands() == 2 && 621 (MI->getOperand(1).getVRegValueOrNull() || 622 MI->getOperand(1).isImmediate() || 623 MI->getOperand(1).isRegister() || 624 MI->getOperand(1).isGlobalAddress() || 625 MI->getOperand(1).isExternalSymbol()))) && 626 "Illegal form for AddRegFrm instruction!"); 627 628 unsigned Reg = MI->getOperand(0).getReg(); 629 630 O << TII.getName(MI->getOpcode()) << " "; 631 printOp(MI->getOperand(0)); 632 if (MI->getNumOperands() == 2 && 633 (!MI->getOperand(1).isRegister() || 634 MI->getOperand(1).getVRegValueOrNull() || 635 MI->getOperand(1).isGlobalAddress() || 636 MI->getOperand(1).isExternalSymbol())) { 637 O << ", "; 638 printOp(MI->getOperand(1)); 639 } 640 checkImplUses(Desc); 641 O << "\n"; 642 return; 643 } 644 case X86II::MRMDestReg: { 645 // There are three forms of MRMDestReg instructions, those with 2 646 // or 3 operands: 647 // 648 // 2 Operands: this is for things like mov that do not read a 649 // second input. 650 // 651 // 2 Operands: two address instructions which def&use the first 652 // argument and use the second as input. 653 // 654 // 3 Operands: in this form, two address instructions are the same 655 // as in 2 but have a constant argument as well. 656 // 657 bool isTwoAddr = TII.isTwoAddrInstr(Opcode); 658 assert(MI->getOperand(0).isRegister() && 659 (MI->getNumOperands() == 2 || 660 (MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate())) 661 && "Bad format for MRMDestReg!"); 662 663 O << TII.getName(MI->getOpcode()) << " "; 664 printOp(MI->getOperand(0)); 665 O << ", "; 666 printOp(MI->getOperand(1)); 667 if (MI->getNumOperands() == 3) { 668 O << ", "; 669 printOp(MI->getOperand(2)); 670 } 671 checkImplUses(Desc); 672 O << "\n"; 673 return; 674 } 675 676 case X86II::MRMDestMem: { 677 // These instructions are the same as MRMDestReg, but instead of having a 678 // register reference for the mod/rm field, it's a memory reference. 679 // 680 assert(isMem(MI, 0) && 681 (MI->getNumOperands() == 4+1 || 682 (MI->getNumOperands() == 4+2 && MI->getOperand(5).isImmediate())) 683 && "Bad format for MRMDestMem!"); 684 685 O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " "; 686 printMemReference(MI, 0); 687 O << ", "; 688 printOp(MI->getOperand(4)); 689 if (MI->getNumOperands() == 4+2) { 690 O << ", "; 691 printOp(MI->getOperand(5)); 692 } 693 checkImplUses(Desc); 694 O << "\n"; 695 return; 696 } 697 698 case X86II::MRMSrcReg: { 699 // There are three forms that are acceptable for MRMSrcReg 700 // instructions, those with 2 or 3 operands: 701 // 702 // 2 Operands: this is for things like mov that do not read a 703 // second input. 704 // 705 // 2 Operands: in this form, the last register is the ModR/M 706 // input. The first operand is a def&use. This is for things 707 // like: add r32, r/m32 708 // 709 // 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used 710 // for instructions like the IMULrri instructions. 711 // 712 // 713 assert(MI->getOperand(0).isRegister() && 714 MI->getOperand(1).isRegister() && 715 (MI->getNumOperands() == 2 || 716 (MI->getNumOperands() == 3 && 717 (MI->getOperand(2).isImmediate()))) 718 && "Bad format for MRMSrcReg!"); 719 720 O << TII.getName(MI->getOpcode()) << " "; 721 printOp(MI->getOperand(0)); 722 O << ", "; 723 printOp(MI->getOperand(1)); 724 if (MI->getNumOperands() == 3) { 725 O << ", "; 726 printOp(MI->getOperand(2)); 727 } 728 O << "\n"; 729 return; 730 } 731 732 case X86II::MRMSrcMem: { 733 // These instructions are the same as MRMSrcReg, but instead of having a 734 // register reference for the mod/rm field, it's a memory reference. 735 // 736 assert(MI->getOperand(0).isRegister() && 737 (MI->getNumOperands() == 1+4 && isMem(MI, 1)) || 738(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() && isMem(MI, 1)) 739 && "Bad format for MRMSrcMem!"); 740 O << TII.getName(MI->getOpcode()) << " "; 741 printOp(MI->getOperand(0)); 742 O << ", " << sizePtr(Desc) << " "; 743 printMemReference(MI, 1); 744 if (MI->getNumOperands() == 2+4) { 745 O << ", "; 746 printOp(MI->getOperand(5)); 747 } 748 O << "\n"; 749 return; 750 } 751 752 case X86II::MRM0r: case X86II::MRM1r: 753 case X86II::MRM2r: case X86II::MRM3r: 754 case X86II::MRM4r: case X86II::MRM5r: 755 case X86II::MRM6r: case X86II::MRM7r: { 756 // In this form, the following are valid formats: 757 // 1. sete r 758 // 2. cmp reg, immediate 759 // 2. shl rdest, rinput <implicit CL or 1> 760 // 3. sbb rdest, rinput, immediate [rdest = rinput] 761 // 762 assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 && 763 MI->getOperand(0).isRegister() && "Bad MRMSxR format!"); 764 assert((MI->getNumOperands() != 2 || 765 MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&& 766 "Bad MRMSxR format!"); 767 assert((MI->getNumOperands() < 3 || 768 (MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) && 769 "Bad MRMSxR format!"); 770 771 if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() && 772 MI->getOperand(0).getReg() != MI->getOperand(1).getReg()) 773 O << "**"; 774 775 O << TII.getName(MI->getOpcode()) << " "; 776 printOp(MI->getOperand(0)); 777 if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) { 778 O << ", "; 779 printOp(MI->getOperand(MI->getNumOperands()-1)); 780 } 781 checkImplUses(Desc); 782 O << "\n"; 783 784 return; 785 } 786 787 case X86II::MRM0m: case X86II::MRM1m: 788 case X86II::MRM2m: case X86II::MRM3m: 789 case X86II::MRM4m: case X86II::MRM5m: 790 case X86II::MRM6m: case X86II::MRM7m: { 791 // In this form, the following are valid formats: 792 // 1. sete [m] 793 // 2. cmp [m], immediate 794 // 2. shl [m], rinput <implicit CL or 1> 795 // 3. sbb [m], immediate 796 // 797 assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 && 798 isMem(MI, 0) && "Bad MRMSxM format!"); 799 assert((MI->getNumOperands() != 5 || 800 (MI->getOperand(4).isImmediate() || 801 MI->getOperand(4).isGlobalAddress())) && 802 "Bad MRMSxM format!"); 803 804 const MachineOperand &Op3 = MI->getOperand(3); 805 806 // gas bugs: 807 // 808 // The 80-bit FP store-pop instruction "fstp XWORD PTR [...]" 809 // is misassembled by gas in intel_syntax mode as its 32-bit 810 // equivalent "fstp DWORD PTR [...]". Workaround: Output the raw 811 // opcode bytes instead of the instruction. 812 // 813 // The 80-bit FP load instruction "fld XWORD PTR [...]" is 814 // misassembled by gas in intel_syntax mode as its 32-bit 815 // equivalent "fld DWORD PTR [...]". Workaround: Output the raw 816 // opcode bytes instead of the instruction. 817 // 818 // gas intel_syntax mode treats "fild QWORD PTR [...]" as an 819 // invalid opcode, saying "64 bit operations are only supported in 820 // 64 bit modes." libopcodes disassembles it as "fild DWORD PTR 821 // [...]", which is wrong. Workaround: Output the raw opcode bytes 822 // instead of the instruction. 823 // 824 // gas intel_syntax mode treats "fistp QWORD PTR [...]" as an 825 // invalid opcode, saying "64 bit operations are only supported in 826 // 64 bit modes." libopcodes disassembles it as "fistpll DWORD PTR 827 // [...]", which is wrong. Workaround: Output the raw opcode bytes 828 // instead of the instruction. 829 if (MI->getOpcode() == X86::FSTP80m || 830 MI->getOpcode() == X86::FLD80m || 831 MI->getOpcode() == X86::FILD64m || 832 MI->getOpcode() == X86::FISTP64m) { 833 GasBugWorkaroundEmitter gwe(O); 834 X86::emitInstruction(gwe, (X86InstrInfo&)TM.getInstrInfo(), *MI); 835 } 836 837 O << TII.getName(MI->getOpcode()) << " "; 838 O << sizePtr(Desc) << " "; 839 printMemReference(MI, 0); 840 if (MI->getNumOperands() == 5) { 841 O << ", "; 842 printOp(MI->getOperand(4)); 843 } 844 checkImplUses(Desc); 845 O << "\n"; 846 return; 847 } 848 default: 849 O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; 850 } 851} 852 853bool Printer::doInitialization(Module &M) { 854 // Tell gas we are outputting Intel syntax (not AT&T syntax) assembly. 855 // 856 // Bug: gas in `intel_syntax noprefix' mode interprets the symbol `Sp' in an 857 // instruction as a reference to the register named sp, and if you try to 858 // reference a symbol `Sp' (e.g. `mov ECX, OFFSET Sp') then it gets lowercased 859 // before being looked up in the symbol table. This creates spurious 860 // `undefined symbol' errors when linking. Workaround: Do not use `noprefix' 861 // mode, and decorate all register names with percent signs. 862 O << "\t.intel_syntax\n"; 863 Mang = new Mangler(M, EmitCygwin); 864 return false; // success 865} 866 867// SwitchSection - Switch to the specified section of the executable if we are 868// not already in it! 869// 870static void SwitchSection(std::ostream &OS, std::string &CurSection, 871 const char *NewSection) { 872 if (CurSection != NewSection) { 873 CurSection = NewSection; 874 if (!CurSection.empty()) 875 OS << "\t" << NewSection << "\n"; 876 } 877} 878 879bool Printer::doFinalization(Module &M) { 880 const TargetData &TD = TM.getTargetData(); 881 std::string CurSection; 882 883 // Print out module-level global variables here. 884 for (Module::const_giterator I = M.gbegin(), E = M.gend(); I != E; ++I) 885 if (I->hasInitializer()) { // External global require no code 886 O << "\n\n"; 887 std::string name = Mang->getValueName(I); 888 Constant *C = I->getInitializer(); 889 unsigned Size = TD.getTypeSize(C->getType()); 890 unsigned Align = TD.getTypeAlignment(C->getType()); 891 892 if (C->isNullValue() && 893 (I->hasLinkOnceLinkage() || I->hasInternalLinkage() || 894 I->hasWeakLinkage() /* FIXME: Verify correct */)) { 895 SwitchSection(O, CurSection, ".data"); 896 if (I->hasInternalLinkage()) 897 O << "\t.local " << name << "\n"; 898 899 O << "\t.comm " << name << "," << TD.getTypeSize(C->getType()) 900 << "," << (unsigned)TD.getTypeAlignment(C->getType()); 901 O << "\t\t# "; 902 WriteAsOperand(O, I, true, true, &M); 903 O << "\n"; 904 } else { 905 switch (I->getLinkage()) { 906 case GlobalValue::LinkOnceLinkage: 907 case GlobalValue::WeakLinkage: // FIXME: Verify correct for weak. 908 // Nonnull linkonce -> weak 909 O << "\t.weak " << name << "\n"; 910 SwitchSection(O, CurSection, ""); 911 O << "\t.section\t.llvm.linkonce.d." << name << ",\"aw\",@progbits\n"; 912 break; 913 914 case GlobalValue::AppendingLinkage: 915 // FIXME: appending linkage variables should go into a section of 916 // their name or something. For now, just emit them as external. 917 case GlobalValue::ExternalLinkage: 918 // If external or appending, declare as a global symbol 919 O << "\t.globl " << name << "\n"; 920 // FALL THROUGH 921 case GlobalValue::InternalLinkage: 922 if (C->isNullValue()) 923 SwitchSection(O, CurSection, ".bss"); 924 else 925 SwitchSection(O, CurSection, ".data"); 926 break; 927 } 928 929 O << "\t.align " << Align << "\n"; 930 O << "\t.type " << name << ",@object\n"; 931 O << "\t.size " << name << "," << Size << "\n"; 932 O << name << ":\t\t\t\t# "; 933 WriteAsOperand(O, I, true, true, &M); 934 O << " = "; 935 WriteAsOperand(O, C, false, false, &M); 936 O << "\n"; 937 emitGlobalConstant(C); 938 } 939 } 940 941 delete Mang; 942 return false; // success 943} 944