nvc0_screen.c revision 587c221a29fe01e24c69952a7a9b0034f7652e4e
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "vl/vl_decoder.h" 28#include "vl/vl_video_buffer.h" 29 30#include "nvc0_context.h" 31#include "nvc0_screen.h" 32 33#include "nvc0_graph_macros.h" 34 35static boolean 36nvc0_screen_is_format_supported(struct pipe_screen *pscreen, 37 enum pipe_format format, 38 enum pipe_texture_target target, 39 unsigned sample_count, 40 unsigned bindings) 41{ 42 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 43 return FALSE; 44 45 if (!util_format_is_supported(format, bindings)) 46 return FALSE; 47 48 switch (format) { 49 case PIPE_FORMAT_R8G8B8A8_UNORM: 50 case PIPE_FORMAT_R8G8B8X8_UNORM: 51 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 52 if (bindings & PIPE_BIND_RENDER_TARGET) 53 return FALSE; 54 default: 55 break; 56 } 57 58 /* transfers & shared are always supported */ 59 bindings &= ~(PIPE_BIND_TRANSFER_READ | 60 PIPE_BIND_TRANSFER_WRITE | 61 PIPE_BIND_SHARED); 62 63 return (nvc0_format_table[format].usage & bindings) == bindings; 64} 65 66static int 67nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 68{ 69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; 70 71 switch (param) { 72 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 73 return 16 * PIPE_SHADER_TYPES; /* NOTE: should not count COMPUTE */ 74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 76 return 15; 77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 78 return 12; 79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 80 return 2048; 81 case PIPE_CAP_MIN_TEXEL_OFFSET: 82 return -8; 83 case PIPE_CAP_MAX_TEXEL_OFFSET: 84 return 7; 85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 86 case PIPE_CAP_TEXTURE_SWIZZLE: 87 case PIPE_CAP_TEXTURE_SHADOW_MAP: 88 case PIPE_CAP_NPOT_TEXTURES: 89 case PIPE_CAP_ANISOTROPIC_FILTER: 90 case PIPE_CAP_SEAMLESS_CUBE_MAP: 91 return 1; 92 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 93 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0; 94 case PIPE_CAP_TWO_SIDED_STENCIL: 95 case PIPE_CAP_DEPTH_CLIP_DISABLE: 96 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 97 case PIPE_CAP_POINT_SPRITE: 98 return 1; 99 case PIPE_CAP_SM3: 100 return 1; 101 case PIPE_CAP_GLSL_FEATURE_LEVEL: 102 return 150; 103 case PIPE_CAP_MAX_RENDER_TARGETS: 104 return 8; 105 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 106 return 1; 107 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 108 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 109 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 110 return 1; 111 case PIPE_CAP_TIMER_QUERY: 112 case PIPE_CAP_OCCLUSION_QUERY: 113 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 114 return 1; 115 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 116 return 4; 117 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 118 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 119 return 128; 120 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 121 case PIPE_CAP_INDEP_BLEND_ENABLE: 122 case PIPE_CAP_INDEP_BLEND_FUNC: 123 return 1; 124 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 125 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 126 return 1; 127 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 128 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 129 return 0; 130 case PIPE_CAP_SHADER_STENCIL_EXPORT: 131 return 0; 132 case PIPE_CAP_PRIMITIVE_RESTART: 133 case PIPE_CAP_TGSI_INSTANCEID: 134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 135 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 136 case PIPE_CAP_CONDITIONAL_RENDER: 137 case PIPE_CAP_TEXTURE_BARRIER: 138 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 139 return 1; 140 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 141 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 142 return 0; /* state trackers will know better */ 143 case PIPE_CAP_USER_VERTEX_BUFFERS: 144 return 1; 145 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 146 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 147 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 148 return 0; 149 default: 150 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 151 return 0; 152 } 153} 154 155static int 156nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 157 enum pipe_shader_cap param) 158{ 159 switch (shader) { 160 case PIPE_SHADER_VERTEX: 161 /* 162 case PIPE_SHADER_TESSELLATION_CONTROL: 163 case PIPE_SHADER_TESSELLATION_EVALUATION: 164 */ 165 case PIPE_SHADER_GEOMETRY: 166 case PIPE_SHADER_FRAGMENT: 167 break; 168 default: 169 return 0; 170 } 171 172 switch (param) { 173 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 174 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 175 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 176 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 177 return 16384; 178 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 179 return 16; 180 case PIPE_SHADER_CAP_MAX_INPUTS: 181 if (shader == PIPE_SHADER_VERTEX) 182 return 32; 183 if (shader == PIPE_SHADER_FRAGMENT) 184 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */ 185 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */ 186 case PIPE_SHADER_CAP_MAX_CONSTS: 187 return 65536 / 16; 188 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 189 return 14; 190 case PIPE_SHADER_CAP_MAX_ADDRS: 191 return 1; 192 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 193 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 194 return shader != PIPE_SHADER_FRAGMENT; 195 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 196 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 197 return 1; 198 case PIPE_SHADER_CAP_MAX_PREDS: 199 return 0; 200 case PIPE_SHADER_CAP_MAX_TEMPS: 201 return NVC0_CAP_MAX_PROGRAM_TEMPS; 202 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 203 return 1; 204 case PIPE_SHADER_CAP_SUBROUTINES: 205 return 1; /* but inlining everything, we need function declarations */ 206 case PIPE_SHADER_CAP_INTEGERS: 207 return 1; 208 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 209 return 16; /* would be 32 in linked (OpenGL-style) mode */ 210 /* 211 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS: 212 return 32; 213 */ 214 default: 215 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 216 return 0; 217 } 218} 219 220static float 221nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 222{ 223 switch (param) { 224 case PIPE_CAPF_MAX_LINE_WIDTH: 225 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 226 return 10.0f; 227 case PIPE_CAPF_MAX_POINT_WIDTH: 228 return 63.0f; 229 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 230 return 63.375f; 231 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 232 return 16.0f; 233 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 234 return 15.0f; 235 default: 236 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 237 return 0.0f; 238 } 239} 240 241static void 242nvc0_screen_destroy(struct pipe_screen *pscreen) 243{ 244 struct nvc0_screen *screen = nvc0_screen(pscreen); 245 246 if (screen->base.fence.current) { 247 nouveau_fence_wait(screen->base.fence.current); 248 nouveau_fence_ref(NULL, &screen->base.fence.current); 249 } 250 if (screen->base.pushbuf) 251 screen->base.pushbuf->user_priv = NULL; 252 253 if (screen->blitctx) 254 FREE(screen->blitctx); 255 256 nouveau_bo_ref(NULL, &screen->text); 257 nouveau_bo_ref(NULL, &screen->uniform_bo); 258 nouveau_bo_ref(NULL, &screen->tls); 259 nouveau_bo_ref(NULL, &screen->txc); 260 nouveau_bo_ref(NULL, &screen->fence.bo); 261 nouveau_bo_ref(NULL, &screen->poly_cache); 262 263 nouveau_heap_destroy(&screen->lib_code); 264 nouveau_heap_destroy(&screen->text_heap); 265 266 if (screen->tic.entries) 267 FREE(screen->tic.entries); 268 269 nouveau_mm_destroy(screen->mm_VRAM_fe0); 270 271 nouveau_object_del(&screen->eng3d); 272 nouveau_object_del(&screen->eng2d); 273 nouveau_object_del(&screen->m2mf); 274 275 nouveau_screen_fini(&screen->base); 276 277 FREE(screen); 278} 279 280static int 281nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos, 282 unsigned size, const uint32_t *data) 283{ 284 struct nouveau_pushbuf *push = screen->base.pushbuf; 285 286 size /= 4; 287 288 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2); 289 PUSH_DATA (push, (m - 0x3800) / 8); 290 PUSH_DATA (push, pos); 291 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1); 292 PUSH_DATA (push, pos); 293 PUSH_DATAp(push, data, size); 294 295 return pos + size; 296} 297 298static void 299nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class) 300{ 301 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1); 302 PUSH_DATA (push, 0xff); 303 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2); 304 PUSH_DATA (push, 0xff); 305 PUSH_DATA (push, 0xff); 306 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2); 307 PUSH_DATA (push, 0xff); 308 PUSH_DATA (push, 0xff); 309 BEGIN_NVC0(push, SUBC_3D(0x074c), 1); 310 PUSH_DATA (push, 0x3f); 311 312 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1); 313 PUSH_DATA (push, (3 << 16) | 3); 314 BEGIN_NVC0(push, SUBC_3D(0x1794), 1); 315 PUSH_DATA (push, (2 << 16) | 2); 316 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1); 317 PUSH_DATA (push, 1); 318 319 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1); 320 PUSH_DATA (push, 0); 321 BEGIN_NVC0(push, SUBC_3D(0x0218), 1); 322 PUSH_DATA (push, 0x10); 323 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1); 324 PUSH_DATA (push, 0x10); 325 BEGIN_NVC0(push, SUBC_3D(0x1290), 1); 326 PUSH_DATA (push, 0x10); 327 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2); 328 PUSH_DATA (push, 0x10); 329 PUSH_DATA (push, 0x10); 330 BEGIN_NVC0(push, SUBC_3D(0x1140), 1); 331 PUSH_DATA (push, 0x10); 332 BEGIN_NVC0(push, SUBC_3D(0x1610), 1); 333 PUSH_DATA (push, 0xe); 334 335 BEGIN_NVC0(push, SUBC_3D(0x164c), 1); 336 PUSH_DATA (push, 1 << 12); 337 BEGIN_NVC0(push, SUBC_3D(0x030c), 1); 338 PUSH_DATA (push, 0); 339 BEGIN_NVC0(push, SUBC_3D(0x0300), 1); 340 PUSH_DATA (push, 3); 341 342 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1); 343 PUSH_DATA (push, 0x3fffff); 344 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1); 345 PUSH_DATA (push, 1); 346 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1); 347 PUSH_DATA (push, 1); 348 BEGIN_NVC0(push, SUBC_3D(0x075c), 1); 349 PUSH_DATA (push, 3); 350 351 if (obj_class >= NVE4_3D_CLASS) { 352 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1); 353 PUSH_DATA (push, 1); 354 } 355 356 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc 357 * are supposed to do */ 358} 359 360static void 361nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 362{ 363 struct nvc0_screen *screen = nvc0_screen(pscreen); 364 struct nouveau_pushbuf *push = screen->base.pushbuf; 365 366 /* we need to do it after possible flush in MARK_RING */ 367 *sequence = ++screen->base.fence.sequence; 368 369 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4); 370 PUSH_DATAh(push, screen->fence.bo->offset); 371 PUSH_DATA (push, screen->fence.bo->offset); 372 PUSH_DATA (push, *sequence); 373 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT | 374 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT)); 375} 376 377static u32 378nvc0_screen_fence_update(struct pipe_screen *pscreen) 379{ 380 struct nvc0_screen *screen = nvc0_screen(pscreen); 381 return screen->fence.map[0]; 382} 383 384#define FAIL_SCREEN_INIT(str, err) \ 385 do { \ 386 NOUVEAU_ERR(str, err); \ 387 nvc0_screen_destroy(pscreen); \ 388 return NULL; \ 389 } while(0) 390 391struct pipe_screen * 392nvc0_screen_create(struct nouveau_device *dev) 393{ 394 struct nvc0_screen *screen; 395 struct pipe_screen *pscreen; 396 struct nouveau_object *chan; 397 struct nouveau_pushbuf *push; 398 uint32_t obj_class; 399 int ret; 400 unsigned i; 401 union nouveau_bo_config mm_config; 402 403 switch (dev->chipset & ~0xf) { 404 case 0xc0: 405 case 0xd0: 406 case 0xe0: 407 break; 408 default: 409 return NULL; 410 } 411 412 screen = CALLOC_STRUCT(nvc0_screen); 413 if (!screen) 414 return NULL; 415 pscreen = &screen->base.base; 416 417 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER; 418 419 ret = nouveau_screen_init(&screen->base, dev); 420 if (ret) { 421 nvc0_screen_destroy(pscreen); 422 return NULL; 423 } 424 chan = screen->base.channel; 425 push = screen->base.pushbuf; 426 push->user_priv = screen; 427 428 pscreen->destroy = nvc0_screen_destroy; 429 pscreen->context_create = nvc0_create; 430 pscreen->is_format_supported = nvc0_screen_is_format_supported; 431 pscreen->get_param = nvc0_screen_get_param; 432 pscreen->get_shader_param = nvc0_screen_get_shader_param; 433 pscreen->get_paramf = nvc0_screen_get_paramf; 434 435 nvc0_screen_init_resource_functions(pscreen); 436 437 nouveau_screen_init_vdec(&screen->base); 438 439 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL, 440 &screen->fence.bo); 441 if (ret) 442 goto fail; 443 nouveau_bo_map(screen->fence.bo, 0, NULL); 444 screen->fence.map = screen->fence.bo->map; 445 screen->base.fence.emit = nvc0_screen_fence_emit; 446 screen->base.fence.update = nvc0_screen_fence_update; 447 448 switch (dev->chipset & 0xf0) { 449 case 0xe0: 450 obj_class = NVE4_P2MF_CLASS; 451 break; 452 default: 453 obj_class = NVC0_M2MF_CLASS; 454 break; 455 } 456 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0, 457 &screen->m2mf); 458 if (ret) 459 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 460 461 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); 462 PUSH_DATA (push, screen->m2mf->oclass); 463 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) { 464 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1); 465 PUSH_DATA (push, 0xa0b5); 466 } 467 468 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0, 469 &screen->eng2d); 470 if (ret) 471 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 472 473 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); 474 PUSH_DATA (push, screen->eng2d->oclass); 475 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1); 476 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY); 477 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1); 478 PUSH_DATA (push, 0); 479 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1); 480 PUSH_DATA (push, 0); 481 BEGIN_NVC0(push, SUBC_2D(0x0884), 1); 482 PUSH_DATA (push, 0x3f); 483 BEGIN_NVC0(push, SUBC_2D(0x0888), 1); 484 PUSH_DATA (push, 1); 485 486 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2); 487 PUSH_DATAh(push, screen->fence.bo->offset + 16); 488 PUSH_DATA (push, screen->fence.bo->offset + 16); 489 490 switch (dev->chipset & 0xf0) { 491 case 0xe0: 492 obj_class = NVE4_3D_CLASS; 493 break; 494 case 0xd0: 495 case 0xc0: 496 default: 497 switch (dev->chipset) { 498 case 0xd9: 499 case 0xc8: 500 obj_class = NVC8_3D_CLASS; 501 break; 502 case 0xc1: 503 obj_class = NVC1_3D_CLASS; 504 break; 505 default: 506 obj_class = NVC0_3D_CLASS; 507 break; 508 } 509 break; 510 } 511 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0, 512 &screen->eng3d); 513 if (ret) 514 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 515 screen->base.class_3d = obj_class; 516 517 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); 518 PUSH_DATA (push, screen->eng3d->oclass); 519 520 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1); 521 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS); 522 523 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { 524 /* kill shaders after about 1 second (at 100 MHz) */ 525 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1); 526 PUSH_DATA (push, 0x17); 527 } 528 529 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); 530 PUSH_DATA (push, 1); 531 532 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1); 533 PUSH_DATA (push, 0); 534 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1); 535 PUSH_DATA (push, 0); 536 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1); 537 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1); 538 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1); 539 PUSH_DATA (push, 0); 540 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1); 541 PUSH_DATA (push, 1); 542 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1); 543 PUSH_DATA (push, 0); 544 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1); 545 PUSH_DATA (push, 1); 546 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1); 547 PUSH_DATA (push, 0); 548 if (screen->eng3d->oclass < NVE4_3D_CLASS) { 549 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1); 550 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 551 } else { 552 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1); 553 PUSH_DATA (push, 15); 554 } 555 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1); 556 PUSH_DATA (push, 8); /* 128 */ 557 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1); 558 PUSH_DATA (push, 1); 559 if (screen->eng3d->oclass >= NVC1_3D_CLASS) { 560 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1); 561 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1); 562 } 563 564 nvc0_magic_3d_init(push, screen->eng3d->oclass); 565 566 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 567 &screen->text); 568 if (ret) 569 goto fail; 570 571 /* XXX: getting a page fault at the end of the code buffer every few 572 * launches, don't use the last 256 bytes to work around them - prefetch ? 573 */ 574 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100); 575 576 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL, 577 &screen->uniform_bo); 578 if (ret) 579 goto fail; 580 581 for (i = 0; i < 5; ++i) { 582 /* TIC and TSC entries for each unit (nve4+ only) */ 583 /* auxiliary constants (6 user clip planes, base instance id */ 584 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); 585 PUSH_DATA (push, 512); 586 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 587 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 588 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1); 589 PUSH_DATA (push, (15 << 4) | 1); 590 if (screen->eng3d->oclass >= NVE4_3D_CLASS) { 591 unsigned j; 592 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9); 593 PUSH_DATA (push, 0); 594 for (j = 0; j < 8; ++j) 595 PUSH_DATA(push, j); 596 } else { 597 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1); 598 PUSH_DATA (push, 0x54); 599 } 600 } 601 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1); 602 PUSH_DATA (push, 0); 603 604 /* max MPs * max warps per MP (TODO: ask kernel) */ 605 if (screen->eng3d->oclass >= NVE4_3D_CLASS) 606 screen->tls_size = 8 * 64; 607 else 608 screen->tls_size = 16 * 48; 609 screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16; 610 screen->tls_size = align(screen->tls_size, 1 << 17); 611 612 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 613 screen->tls_size, NULL, &screen->tls); 614 if (ret) 615 goto fail; 616 617 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2); 618 PUSH_DATAh(push, screen->text->offset); 619 PUSH_DATA (push, screen->text->offset); 620 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4); 621 PUSH_DATAh(push, screen->tls->offset); 622 PUSH_DATA (push, screen->tls->offset); 623 PUSH_DATA (push, screen->tls_size >> 32); 624 PUSH_DATA (push, screen->tls_size); 625 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1); 626 PUSH_DATA (push, 0); 627 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1); 628 PUSH_DATA (push, 0); 629 630 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 631 &screen->poly_cache); 632 if (ret) 633 goto fail; 634 635 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3); 636 PUSH_DATAh(push, screen->poly_cache->offset); 637 PUSH_DATA (push, screen->poly_cache->offset); 638 PUSH_DATA (push, 3); 639 640 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL, 641 &screen->txc); 642 if (ret) 643 goto fail; 644 645 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3); 646 PUSH_DATAh(push, screen->txc->offset); 647 PUSH_DATA (push, screen->txc->offset); 648 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); 649 650 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3); 651 PUSH_DATAh(push, screen->txc->offset + 65536); 652 PUSH_DATA (push, screen->txc->offset + 65536); 653 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1); 654 655 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1); 656 PUSH_DATA (push, 0); 657 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2); 658 PUSH_DATA (push, 0); 659 PUSH_DATA (push, 0); 660 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 661 PUSH_DATA (push, 0x3f); 662 663 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1); 664 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY); 665 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 666 for (i = 0; i < 8 * 2; ++i) 667 PUSH_DATA(push, 0); 668 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1); 669 PUSH_DATA (push, 0); 670 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1); 671 PUSH_DATA (push, 0); 672 673 /* neither scissors, viewport nor stencil mask should affect clears */ 674 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1); 675 PUSH_DATA (push, 0); 676 677 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1); 678 PUSH_DATA (push, 1); 679 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2); 680 PUSH_DATAf(push, 0.0f); 681 PUSH_DATAf(push, 1.0f); 682 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1); 683 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1); 684 685 /* We use scissors instead of exact view volume clipping, 686 * so they're always enabled. 687 */ 688 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3); 689 PUSH_DATA (push, 1); 690 PUSH_DATA (push, 8192 << 16); 691 PUSH_DATA (push, 8192 << 16); 692 693#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n); 694 695 i = 0; 696 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf); 697 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables); 698 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select); 699 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select); 700 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select); 701 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front); 702 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back); 703 704 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1); 705 PUSH_DATA (push, 1); 706 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1); 707 PUSH_DATA (push, 1); 708 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1); 709 PUSH_DATA (push, 0x40); 710 BEGIN_NVC0(push, NVC0_3D(LAYER), 1); 711 PUSH_DATA (push, 0); 712 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1); 713 PUSH_DATA (push, 0x30); 714 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1); 715 PUSH_DATA (push, 3); 716 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1); 717 PUSH_DATA (push, 0x20); 718 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1); 719 PUSH_DATA (push, 0x00); 720 721 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1); 722 PUSH_DATA (push, 0); 723 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1); 724 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL); 725 726 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1); 727 728 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2); 729 PUSH_DATA (push, 0xab); 730 PUSH_DATA (push, 0x00000000); 731 732 PUSH_KICK (push); 733 734 screen->tic.entries = CALLOC(4096, sizeof(void *)); 735 screen->tsc.entries = screen->tic.entries + 2048; 736 737 mm_config.nvc0.tile_mode = 0; 738 mm_config.nvc0.memtype = 0xfe0; 739 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config); 740 741 if (!nvc0_blitctx_create(screen)) 742 goto fail; 743 744 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 745 746 return pscreen; 747 748fail: 749 nvc0_screen_destroy(pscreen); 750 return NULL; 751} 752 753int 754nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry) 755{ 756 int i = screen->tic.next; 757 758 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 759 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 760 761 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 762 763 if (screen->tic.entries[i]) 764 nv50_tic_entry(screen->tic.entries[i])->id = -1; 765 766 screen->tic.entries[i] = entry; 767 return i; 768} 769 770int 771nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry) 772{ 773 int i = screen->tsc.next; 774 775 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 776 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 777 778 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 779 780 if (screen->tsc.entries[i]) 781 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 782 783 screen->tsc.entries[i] = entry; 784 return i; 785} 786