nvc0_screen.c revision af372129e5c1722a3d53dd1fc2f3409207c12f7e
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "vl/vl_decoder.h" 28#include "vl/vl_video_buffer.h" 29 30#include "nvc0_context.h" 31#include "nvc0_screen.h" 32 33#include "nvc0_graph_macros.h" 34 35static boolean 36nvc0_screen_is_format_supported(struct pipe_screen *pscreen, 37 enum pipe_format format, 38 enum pipe_texture_target target, 39 unsigned sample_count, 40 unsigned bindings) 41{ 42 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 43 return FALSE; 44 45 if (!util_format_is_supported(format, bindings)) 46 return FALSE; 47 48 switch (format) { 49 case PIPE_FORMAT_R8G8B8A8_UNORM: 50 case PIPE_FORMAT_R8G8B8X8_UNORM: 51 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 52 if (bindings & PIPE_BIND_RENDER_TARGET) 53 return FALSE; 54 default: 55 break; 56 } 57 58 /* transfers & shared are always supported */ 59 bindings &= ~(PIPE_BIND_TRANSFER_READ | 60 PIPE_BIND_TRANSFER_WRITE | 61 PIPE_BIND_SHARED); 62 63 return (nvc0_format_table[format].usage & bindings) == bindings; 64} 65 66static int 67nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 68{ 69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; 70 71 switch (param) { 72 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 73 return 16 * PIPE_SHADER_TYPES; /* NOTE: should not count COMPUTE */ 74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 76 return 15; 77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 78 return 12; 79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 80 return 2048; 81 case PIPE_CAP_MIN_TEXEL_OFFSET: 82 return -8; 83 case PIPE_CAP_MAX_TEXEL_OFFSET: 84 return 7; 85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 86 case PIPE_CAP_TEXTURE_SWIZZLE: 87 case PIPE_CAP_TEXTURE_SHADOW_MAP: 88 case PIPE_CAP_NPOT_TEXTURES: 89 case PIPE_CAP_ANISOTROPIC_FILTER: 90 case PIPE_CAP_SEAMLESS_CUBE_MAP: 91 return 1; 92 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 93 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0; 94 case PIPE_CAP_TWO_SIDED_STENCIL: 95 case PIPE_CAP_DEPTH_CLIP_DISABLE: 96 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 97 case PIPE_CAP_POINT_SPRITE: 98 return 1; 99 case PIPE_CAP_SM3: 100 return 1; 101 case PIPE_CAP_GLSL_FEATURE_LEVEL: 102 return 150; 103 case PIPE_CAP_MAX_RENDER_TARGETS: 104 return 8; 105 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 106 return 1; 107 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 108 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 109 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 110 return 1; 111 case PIPE_CAP_TIMER_QUERY: 112 case PIPE_CAP_OCCLUSION_QUERY: 113 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 114 return 1; 115 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 116 return 4; 117 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 118 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 119 return 128; 120 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 121 case PIPE_CAP_INDEP_BLEND_ENABLE: 122 case PIPE_CAP_INDEP_BLEND_FUNC: 123 return 1; 124 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 125 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 126 return 1; 127 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 128 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 129 return 0; 130 case PIPE_CAP_SHADER_STENCIL_EXPORT: 131 return 0; 132 case PIPE_CAP_PRIMITIVE_RESTART: 133 case PIPE_CAP_TGSI_INSTANCEID: 134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 135 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 136 case PIPE_CAP_CONDITIONAL_RENDER: 137 case PIPE_CAP_TEXTURE_BARRIER: 138 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 139 case PIPE_CAP_START_INSTANCE: 140 return 1; 141 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 142 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 143 return 0; /* state trackers will know better */ 144 case PIPE_CAP_USER_CONSTANT_BUFFERS: 145 case PIPE_CAP_USER_INDEX_BUFFERS: 146 case PIPE_CAP_USER_VERTEX_BUFFERS: 147 return 1; 148 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 149 return 256; 150 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 151 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 152 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 153 return 0; 154 default: 155 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 156 return 0; 157 } 158} 159 160static int 161nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 162 enum pipe_shader_cap param) 163{ 164 switch (shader) { 165 case PIPE_SHADER_VERTEX: 166 /* 167 case PIPE_SHADER_TESSELLATION_CONTROL: 168 case PIPE_SHADER_TESSELLATION_EVALUATION: 169 */ 170 case PIPE_SHADER_GEOMETRY: 171 case PIPE_SHADER_FRAGMENT: 172 break; 173 default: 174 return 0; 175 } 176 177 switch (param) { 178 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 179 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 180 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 181 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 182 return 16384; 183 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 184 return 16; 185 case PIPE_SHADER_CAP_MAX_INPUTS: 186 if (shader == PIPE_SHADER_VERTEX) 187 return 32; 188 if (shader == PIPE_SHADER_FRAGMENT) 189 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */ 190 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */ 191 case PIPE_SHADER_CAP_MAX_CONSTS: 192 return 65536 / 16; 193 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 194 return NVC0_MAX_PIPE_CONSTBUFS; 195 case PIPE_SHADER_CAP_MAX_ADDRS: 196 return 1; 197 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 198 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 199 return shader != PIPE_SHADER_FRAGMENT; 200 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 201 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 202 return 1; 203 case PIPE_SHADER_CAP_MAX_PREDS: 204 return 0; 205 case PIPE_SHADER_CAP_MAX_TEMPS: 206 return NVC0_CAP_MAX_PROGRAM_TEMPS; 207 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 208 return 1; 209 case PIPE_SHADER_CAP_SUBROUTINES: 210 return 1; /* but inlining everything, we need function declarations */ 211 case PIPE_SHADER_CAP_INTEGERS: 212 return 1; 213 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 214 return 16; /* would be 32 in linked (OpenGL-style) mode */ 215 /* 216 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS: 217 return 32; 218 */ 219 default: 220 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 221 return 0; 222 } 223} 224 225static float 226nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 227{ 228 switch (param) { 229 case PIPE_CAPF_MAX_LINE_WIDTH: 230 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 231 return 10.0f; 232 case PIPE_CAPF_MAX_POINT_WIDTH: 233 return 63.0f; 234 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 235 return 63.375f; 236 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 237 return 16.0f; 238 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 239 return 15.0f; 240 default: 241 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 242 return 0.0f; 243 } 244} 245 246static void 247nvc0_screen_destroy(struct pipe_screen *pscreen) 248{ 249 struct nvc0_screen *screen = nvc0_screen(pscreen); 250 251 if (screen->base.fence.current) { 252 nouveau_fence_wait(screen->base.fence.current); 253 nouveau_fence_ref(NULL, &screen->base.fence.current); 254 } 255 if (screen->base.pushbuf) 256 screen->base.pushbuf->user_priv = NULL; 257 258 if (screen->blitctx) 259 FREE(screen->blitctx); 260 261 nouveau_bo_ref(NULL, &screen->text); 262 nouveau_bo_ref(NULL, &screen->uniform_bo); 263 nouveau_bo_ref(NULL, &screen->tls); 264 nouveau_bo_ref(NULL, &screen->txc); 265 nouveau_bo_ref(NULL, &screen->fence.bo); 266 nouveau_bo_ref(NULL, &screen->poly_cache); 267 268 nouveau_heap_destroy(&screen->lib_code); 269 nouveau_heap_destroy(&screen->text_heap); 270 271 if (screen->tic.entries) 272 FREE(screen->tic.entries); 273 274 nouveau_mm_destroy(screen->mm_VRAM_fe0); 275 276 nouveau_object_del(&screen->eng3d); 277 nouveau_object_del(&screen->eng2d); 278 nouveau_object_del(&screen->m2mf); 279 280 nouveau_screen_fini(&screen->base); 281 282 FREE(screen); 283} 284 285static int 286nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos, 287 unsigned size, const uint32_t *data) 288{ 289 struct nouveau_pushbuf *push = screen->base.pushbuf; 290 291 size /= 4; 292 293 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2); 294 PUSH_DATA (push, (m - 0x3800) / 8); 295 PUSH_DATA (push, pos); 296 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1); 297 PUSH_DATA (push, pos); 298 PUSH_DATAp(push, data, size); 299 300 return pos + size; 301} 302 303static void 304nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class) 305{ 306 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1); 307 PUSH_DATA (push, 0xff); 308 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2); 309 PUSH_DATA (push, 0xff); 310 PUSH_DATA (push, 0xff); 311 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2); 312 PUSH_DATA (push, 0xff); 313 PUSH_DATA (push, 0xff); 314 BEGIN_NVC0(push, SUBC_3D(0x074c), 1); 315 PUSH_DATA (push, 0x3f); 316 317 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1); 318 PUSH_DATA (push, (3 << 16) | 3); 319 BEGIN_NVC0(push, SUBC_3D(0x1794), 1); 320 PUSH_DATA (push, (2 << 16) | 2); 321 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1); 322 PUSH_DATA (push, 1); 323 324 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1); 325 PUSH_DATA (push, 0); 326 BEGIN_NVC0(push, SUBC_3D(0x0218), 1); 327 PUSH_DATA (push, 0x10); 328 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1); 329 PUSH_DATA (push, 0x10); 330 BEGIN_NVC0(push, SUBC_3D(0x1290), 1); 331 PUSH_DATA (push, 0x10); 332 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2); 333 PUSH_DATA (push, 0x10); 334 PUSH_DATA (push, 0x10); 335 BEGIN_NVC0(push, SUBC_3D(0x1140), 1); 336 PUSH_DATA (push, 0x10); 337 BEGIN_NVC0(push, SUBC_3D(0x1610), 1); 338 PUSH_DATA (push, 0xe); 339 340 BEGIN_NVC0(push, SUBC_3D(0x164c), 1); 341 PUSH_DATA (push, 1 << 12); 342 BEGIN_NVC0(push, SUBC_3D(0x030c), 1); 343 PUSH_DATA (push, 0); 344 BEGIN_NVC0(push, SUBC_3D(0x0300), 1); 345 PUSH_DATA (push, 3); 346 347 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1); 348 PUSH_DATA (push, 0x3fffff); 349 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1); 350 PUSH_DATA (push, 1); 351 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1); 352 PUSH_DATA (push, 1); 353 BEGIN_NVC0(push, SUBC_3D(0x075c), 1); 354 PUSH_DATA (push, 3); 355 356 if (obj_class >= NVE4_3D_CLASS) { 357 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1); 358 PUSH_DATA (push, 1); 359 } 360 361 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc 362 * are supposed to do */ 363} 364 365static void 366nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 367{ 368 struct nvc0_screen *screen = nvc0_screen(pscreen); 369 struct nouveau_pushbuf *push = screen->base.pushbuf; 370 371 /* we need to do it after possible flush in MARK_RING */ 372 *sequence = ++screen->base.fence.sequence; 373 374 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4); 375 PUSH_DATAh(push, screen->fence.bo->offset); 376 PUSH_DATA (push, screen->fence.bo->offset); 377 PUSH_DATA (push, *sequence); 378 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT | 379 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT)); 380} 381 382static u32 383nvc0_screen_fence_update(struct pipe_screen *pscreen) 384{ 385 struct nvc0_screen *screen = nvc0_screen(pscreen); 386 return screen->fence.map[0]; 387} 388 389#define FAIL_SCREEN_INIT(str, err) \ 390 do { \ 391 NOUVEAU_ERR(str, err); \ 392 nvc0_screen_destroy(pscreen); \ 393 return NULL; \ 394 } while(0) 395 396struct pipe_screen * 397nvc0_screen_create(struct nouveau_device *dev) 398{ 399 struct nvc0_screen *screen; 400 struct pipe_screen *pscreen; 401 struct nouveau_object *chan; 402 struct nouveau_pushbuf *push; 403 uint32_t obj_class; 404 int ret; 405 unsigned i; 406 union nouveau_bo_config mm_config; 407 408 switch (dev->chipset & ~0xf) { 409 case 0xc0: 410 case 0xd0: 411 case 0xe0: 412 break; 413 default: 414 return NULL; 415 } 416 417 screen = CALLOC_STRUCT(nvc0_screen); 418 if (!screen) 419 return NULL; 420 pscreen = &screen->base.base; 421 422 ret = nouveau_screen_init(&screen->base, dev); 423 if (ret) { 424 nvc0_screen_destroy(pscreen); 425 return NULL; 426 } 427 chan = screen->base.channel; 428 push = screen->base.pushbuf; 429 push->user_priv = screen; 430 431 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER | 432 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER; 433 screen->base.sysmem_bindings |= 434 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER; 435 436 pscreen->destroy = nvc0_screen_destroy; 437 pscreen->context_create = nvc0_create; 438 pscreen->is_format_supported = nvc0_screen_is_format_supported; 439 pscreen->get_param = nvc0_screen_get_param; 440 pscreen->get_shader_param = nvc0_screen_get_shader_param; 441 pscreen->get_paramf = nvc0_screen_get_paramf; 442 443 nvc0_screen_init_resource_functions(pscreen); 444 445 nouveau_screen_init_vdec(&screen->base); 446 447 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL, 448 &screen->fence.bo); 449 if (ret) 450 goto fail; 451 nouveau_bo_map(screen->fence.bo, 0, NULL); 452 screen->fence.map = screen->fence.bo->map; 453 screen->base.fence.emit = nvc0_screen_fence_emit; 454 screen->base.fence.update = nvc0_screen_fence_update; 455 456 switch (dev->chipset & 0xf0) { 457 case 0xe0: 458 obj_class = NVE4_P2MF_CLASS; 459 break; 460 default: 461 obj_class = NVC0_M2MF_CLASS; 462 break; 463 } 464 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0, 465 &screen->m2mf); 466 if (ret) 467 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 468 469 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); 470 PUSH_DATA (push, screen->m2mf->oclass); 471 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) { 472 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1); 473 PUSH_DATA (push, 0xa0b5); 474 } 475 476 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0, 477 &screen->eng2d); 478 if (ret) 479 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 480 481 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); 482 PUSH_DATA (push, screen->eng2d->oclass); 483 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1); 484 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY); 485 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1); 486 PUSH_DATA (push, 0); 487 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1); 488 PUSH_DATA (push, 0); 489 BEGIN_NVC0(push, SUBC_2D(0x0884), 1); 490 PUSH_DATA (push, 0x3f); 491 BEGIN_NVC0(push, SUBC_2D(0x0888), 1); 492 PUSH_DATA (push, 1); 493 494 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2); 495 PUSH_DATAh(push, screen->fence.bo->offset + 16); 496 PUSH_DATA (push, screen->fence.bo->offset + 16); 497 498 switch (dev->chipset & 0xf0) { 499 case 0xe0: 500 obj_class = NVE4_3D_CLASS; 501 break; 502 case 0xd0: 503 case 0xc0: 504 default: 505 switch (dev->chipset) { 506 case 0xd9: 507 case 0xc8: 508 obj_class = NVC8_3D_CLASS; 509 break; 510 case 0xc1: 511 obj_class = NVC1_3D_CLASS; 512 break; 513 default: 514 obj_class = NVC0_3D_CLASS; 515 break; 516 } 517 break; 518 } 519 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0, 520 &screen->eng3d); 521 if (ret) 522 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 523 screen->base.class_3d = obj_class; 524 525 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); 526 PUSH_DATA (push, screen->eng3d->oclass); 527 528 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1); 529 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS); 530 531 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { 532 /* kill shaders after about 1 second (at 100 MHz) */ 533 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1); 534 PUSH_DATA (push, 0x17); 535 } 536 537 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); 538 PUSH_DATA (push, 1); 539 540 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1); 541 PUSH_DATA (push, 0); 542 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1); 543 PUSH_DATA (push, 0); 544 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1); 545 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1); 546 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1); 547 PUSH_DATA (push, 0); 548 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1); 549 PUSH_DATA (push, 1); 550 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1); 551 PUSH_DATA (push, 0); 552 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1); 553 PUSH_DATA (push, 1); 554 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1); 555 PUSH_DATA (push, 0); 556 if (screen->eng3d->oclass < NVE4_3D_CLASS) { 557 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1); 558 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 559 } else { 560 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1); 561 PUSH_DATA (push, 15); 562 } 563 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1); 564 PUSH_DATA (push, 8); /* 128 */ 565 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1); 566 PUSH_DATA (push, 1); 567 if (screen->eng3d->oclass >= NVC1_3D_CLASS) { 568 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1); 569 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1); 570 } 571 572 nvc0_magic_3d_init(push, screen->eng3d->oclass); 573 574 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 575 &screen->text); 576 if (ret) 577 goto fail; 578 579 /* XXX: getting a page fault at the end of the code buffer every few 580 * launches, don't use the last 256 bytes to work around them - prefetch ? 581 */ 582 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100); 583 584 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL, 585 &screen->uniform_bo); 586 if (ret) 587 goto fail; 588 589 for (i = 0; i < 5; ++i) { 590 /* TIC and TSC entries for each unit (nve4+ only) */ 591 /* auxiliary constants (6 user clip planes, base instance id */ 592 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); 593 PUSH_DATA (push, 512); 594 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 595 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 596 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1); 597 PUSH_DATA (push, (15 << 4) | 1); 598 if (screen->eng3d->oclass >= NVE4_3D_CLASS) { 599 unsigned j; 600 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9); 601 PUSH_DATA (push, 0); 602 for (j = 0; j < 8; ++j) 603 PUSH_DATA(push, j); 604 } else { 605 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1); 606 PUSH_DATA (push, 0x54); 607 } 608 } 609 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1); 610 PUSH_DATA (push, 0); 611 612 /* max MPs * max warps per MP (TODO: ask kernel) */ 613 if (screen->eng3d->oclass >= NVE4_3D_CLASS) 614 screen->tls_size = 8 * 64; 615 else 616 screen->tls_size = 16 * 48; 617 screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16; 618 screen->tls_size = align(screen->tls_size, 1 << 17); 619 620 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 621 screen->tls_size, NULL, &screen->tls); 622 if (ret) 623 goto fail; 624 625 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2); 626 PUSH_DATAh(push, screen->text->offset); 627 PUSH_DATA (push, screen->text->offset); 628 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4); 629 PUSH_DATAh(push, screen->tls->offset); 630 PUSH_DATA (push, screen->tls->offset); 631 PUSH_DATA (push, screen->tls_size >> 32); 632 PUSH_DATA (push, screen->tls_size); 633 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1); 634 PUSH_DATA (push, 0); 635 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1); 636 PUSH_DATA (push, 0); 637 638 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 639 &screen->poly_cache); 640 if (ret) 641 goto fail; 642 643 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3); 644 PUSH_DATAh(push, screen->poly_cache->offset); 645 PUSH_DATA (push, screen->poly_cache->offset); 646 PUSH_DATA (push, 3); 647 648 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL, 649 &screen->txc); 650 if (ret) 651 goto fail; 652 653 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3); 654 PUSH_DATAh(push, screen->txc->offset); 655 PUSH_DATA (push, screen->txc->offset); 656 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); 657 658 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3); 659 PUSH_DATAh(push, screen->txc->offset + 65536); 660 PUSH_DATA (push, screen->txc->offset + 65536); 661 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1); 662 663 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1); 664 PUSH_DATA (push, 0); 665 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2); 666 PUSH_DATA (push, 0); 667 PUSH_DATA (push, 0); 668 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 669 PUSH_DATA (push, 0x3f); 670 671 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1); 672 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY); 673 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 674 for (i = 0; i < 8 * 2; ++i) 675 PUSH_DATA(push, 0); 676 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1); 677 PUSH_DATA (push, 0); 678 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1); 679 PUSH_DATA (push, 0); 680 681 /* neither scissors, viewport nor stencil mask should affect clears */ 682 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1); 683 PUSH_DATA (push, 0); 684 685 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1); 686 PUSH_DATA (push, 1); 687 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2); 688 PUSH_DATAf(push, 0.0f); 689 PUSH_DATAf(push, 1.0f); 690 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1); 691 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1); 692 693 /* We use scissors instead of exact view volume clipping, 694 * so they're always enabled. 695 */ 696 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3); 697 PUSH_DATA (push, 1); 698 PUSH_DATA (push, 8192 << 16); 699 PUSH_DATA (push, 8192 << 16); 700 701#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n); 702 703 i = 0; 704 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf); 705 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables); 706 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select); 707 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select); 708 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select); 709 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front); 710 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back); 711 712 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1); 713 PUSH_DATA (push, 1); 714 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1); 715 PUSH_DATA (push, 1); 716 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1); 717 PUSH_DATA (push, 0x40); 718 BEGIN_NVC0(push, NVC0_3D(LAYER), 1); 719 PUSH_DATA (push, 0); 720 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1); 721 PUSH_DATA (push, 0x30); 722 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1); 723 PUSH_DATA (push, 3); 724 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1); 725 PUSH_DATA (push, 0x20); 726 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1); 727 PUSH_DATA (push, 0x00); 728 729 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1); 730 PUSH_DATA (push, 0); 731 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1); 732 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL); 733 734 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1); 735 736 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2); 737 PUSH_DATA (push, 0xab); 738 PUSH_DATA (push, 0x00000000); 739 740 PUSH_KICK (push); 741 742 screen->tic.entries = CALLOC(4096, sizeof(void *)); 743 screen->tsc.entries = screen->tic.entries + 2048; 744 745 mm_config.nvc0.tile_mode = 0; 746 mm_config.nvc0.memtype = 0xfe0; 747 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config); 748 749 if (!nvc0_blitctx_create(screen)) 750 goto fail; 751 752 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 753 754 return pscreen; 755 756fail: 757 nvc0_screen_destroy(pscreen); 758 return NULL; 759} 760 761int 762nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry) 763{ 764 int i = screen->tic.next; 765 766 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 767 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 768 769 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 770 771 if (screen->tic.entries[i]) 772 nv50_tic_entry(screen->tic.entries[i])->id = -1; 773 774 screen->tic.entries[i] = entry; 775 return i; 776} 777 778int 779nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry) 780{ 781 int i = screen->tsc.next; 782 783 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 784 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 785 786 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 787 788 if (screen->tsc.entries[i]) 789 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 790 791 screen->tsc.entries[i] = entry; 792 return i; 793} 794