nvc0_screen.c revision ef7bb281292c17b762b57779306e874704c87328
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "vl/vl_decoder.h" 28#include "vl/vl_video_buffer.h" 29 30#include "nvc0_context.h" 31#include "nvc0_screen.h" 32 33#include "nvc0_graph_macros.h" 34 35static boolean 36nvc0_screen_is_format_supported(struct pipe_screen *pscreen, 37 enum pipe_format format, 38 enum pipe_texture_target target, 39 unsigned sample_count, 40 unsigned bindings) 41{ 42 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 43 return FALSE; 44 45 if (!util_format_is_supported(format, bindings)) 46 return FALSE; 47 48 switch (format) { 49 case PIPE_FORMAT_R8G8B8A8_UNORM: 50 case PIPE_FORMAT_R8G8B8X8_UNORM: 51 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 52 if (bindings & PIPE_BIND_RENDER_TARGET) 53 return FALSE; 54 default: 55 break; 56 } 57 58 /* transfers & shared are always supported */ 59 bindings &= ~(PIPE_BIND_TRANSFER_READ | 60 PIPE_BIND_TRANSFER_WRITE | 61 PIPE_BIND_SHARED); 62 63 return (nvc0_format_table[format].usage & bindings) == bindings; 64} 65 66static int 67nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 68{ 69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; 70 71 switch (param) { 72 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 73 return 16 * PIPE_SHADER_TYPES; /* NOTE: should not count COMPUTE */ 74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 76 return 15; 77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 78 return 12; 79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 80 return 2048; 81 case PIPE_CAP_MIN_TEXEL_OFFSET: 82 return -8; 83 case PIPE_CAP_MAX_TEXEL_OFFSET: 84 return 7; 85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 86 case PIPE_CAP_TEXTURE_SWIZZLE: 87 case PIPE_CAP_TEXTURE_SHADOW_MAP: 88 case PIPE_CAP_NPOT_TEXTURES: 89 case PIPE_CAP_ANISOTROPIC_FILTER: 90 case PIPE_CAP_SEAMLESS_CUBE_MAP: 91 return 1; 92 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 93 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0; 94 case PIPE_CAP_TWO_SIDED_STENCIL: 95 case PIPE_CAP_DEPTH_CLIP_DISABLE: 96 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 97 case PIPE_CAP_POINT_SPRITE: 98 return 1; 99 case PIPE_CAP_SM3: 100 return 1; 101 case PIPE_CAP_GLSL_FEATURE_LEVEL: 102 return 150; 103 case PIPE_CAP_MAX_RENDER_TARGETS: 104 return 8; 105 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 106 return 1; 107 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 108 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 109 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 110 return 1; 111 case PIPE_CAP_TIMER_QUERY: 112 case PIPE_CAP_OCCLUSION_QUERY: 113 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 114 return 1; 115 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 116 return 4; 117 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 118 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 119 return 128; 120 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 121 case PIPE_CAP_INDEP_BLEND_ENABLE: 122 case PIPE_CAP_INDEP_BLEND_FUNC: 123 return 1; 124 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 125 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 126 return 1; 127 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 128 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 129 return 0; 130 case PIPE_CAP_SHADER_STENCIL_EXPORT: 131 return 0; 132 case PIPE_CAP_PRIMITIVE_RESTART: 133 case PIPE_CAP_TGSI_INSTANCEID: 134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 135 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 136 case PIPE_CAP_CONDITIONAL_RENDER: 137 case PIPE_CAP_TEXTURE_BARRIER: 138 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 139 return 1; 140 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 141 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 142 case PIPE_CAP_USER_VERTEX_BUFFERS: 143 return 0; /* state trackers will know better */ 144 case PIPE_CAP_USER_CONSTANT_BUFFERS: 145 case PIPE_CAP_USER_INDEX_BUFFERS: 146 return 1; 147 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 148 return 256; 149 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 150 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 151 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 152 return 0; 153 default: 154 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 155 return 0; 156 } 157} 158 159static int 160nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 161 enum pipe_shader_cap param) 162{ 163 switch (shader) { 164 case PIPE_SHADER_VERTEX: 165 /* 166 case PIPE_SHADER_TESSELLATION_CONTROL: 167 case PIPE_SHADER_TESSELLATION_EVALUATION: 168 */ 169 case PIPE_SHADER_GEOMETRY: 170 case PIPE_SHADER_FRAGMENT: 171 break; 172 default: 173 return 0; 174 } 175 176 switch (param) { 177 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 178 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 179 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 180 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 181 return 16384; 182 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 183 return 16; 184 case PIPE_SHADER_CAP_MAX_INPUTS: 185 if (shader == PIPE_SHADER_VERTEX) 186 return 32; 187 if (shader == PIPE_SHADER_FRAGMENT) 188 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */ 189 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */ 190 case PIPE_SHADER_CAP_MAX_CONSTS: 191 return 65536 / 16; 192 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 193 return NVC0_MAX_PIPE_CONSTBUFS; 194 case PIPE_SHADER_CAP_MAX_ADDRS: 195 return 1; 196 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 197 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 198 return shader != PIPE_SHADER_FRAGMENT; 199 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 200 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 201 return 1; 202 case PIPE_SHADER_CAP_MAX_PREDS: 203 return 0; 204 case PIPE_SHADER_CAP_MAX_TEMPS: 205 return NVC0_CAP_MAX_PROGRAM_TEMPS; 206 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 207 return 1; 208 case PIPE_SHADER_CAP_SUBROUTINES: 209 return 1; /* but inlining everything, we need function declarations */ 210 case PIPE_SHADER_CAP_INTEGERS: 211 return 1; 212 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 213 return 16; /* would be 32 in linked (OpenGL-style) mode */ 214 /* 215 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS: 216 return 32; 217 */ 218 default: 219 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 220 return 0; 221 } 222} 223 224static float 225nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 226{ 227 switch (param) { 228 case PIPE_CAPF_MAX_LINE_WIDTH: 229 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 230 return 10.0f; 231 case PIPE_CAPF_MAX_POINT_WIDTH: 232 return 63.0f; 233 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 234 return 63.375f; 235 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 236 return 16.0f; 237 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 238 return 15.0f; 239 default: 240 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 241 return 0.0f; 242 } 243} 244 245static void 246nvc0_screen_destroy(struct pipe_screen *pscreen) 247{ 248 struct nvc0_screen *screen = nvc0_screen(pscreen); 249 250 if (screen->base.fence.current) { 251 nouveau_fence_wait(screen->base.fence.current); 252 nouveau_fence_ref(NULL, &screen->base.fence.current); 253 } 254 if (screen->base.pushbuf) 255 screen->base.pushbuf->user_priv = NULL; 256 257 if (screen->blitctx) 258 FREE(screen->blitctx); 259 260 nouveau_bo_ref(NULL, &screen->text); 261 nouveau_bo_ref(NULL, &screen->uniform_bo); 262 nouveau_bo_ref(NULL, &screen->tls); 263 nouveau_bo_ref(NULL, &screen->txc); 264 nouveau_bo_ref(NULL, &screen->fence.bo); 265 nouveau_bo_ref(NULL, &screen->poly_cache); 266 267 nouveau_heap_destroy(&screen->lib_code); 268 nouveau_heap_destroy(&screen->text_heap); 269 270 if (screen->tic.entries) 271 FREE(screen->tic.entries); 272 273 nouveau_mm_destroy(screen->mm_VRAM_fe0); 274 275 nouveau_object_del(&screen->eng3d); 276 nouveau_object_del(&screen->eng2d); 277 nouveau_object_del(&screen->m2mf); 278 279 nouveau_screen_fini(&screen->base); 280 281 FREE(screen); 282} 283 284static int 285nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos, 286 unsigned size, const uint32_t *data) 287{ 288 struct nouveau_pushbuf *push = screen->base.pushbuf; 289 290 size /= 4; 291 292 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2); 293 PUSH_DATA (push, (m - 0x3800) / 8); 294 PUSH_DATA (push, pos); 295 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1); 296 PUSH_DATA (push, pos); 297 PUSH_DATAp(push, data, size); 298 299 return pos + size; 300} 301 302static void 303nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class) 304{ 305 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1); 306 PUSH_DATA (push, 0xff); 307 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2); 308 PUSH_DATA (push, 0xff); 309 PUSH_DATA (push, 0xff); 310 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2); 311 PUSH_DATA (push, 0xff); 312 PUSH_DATA (push, 0xff); 313 BEGIN_NVC0(push, SUBC_3D(0x074c), 1); 314 PUSH_DATA (push, 0x3f); 315 316 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1); 317 PUSH_DATA (push, (3 << 16) | 3); 318 BEGIN_NVC0(push, SUBC_3D(0x1794), 1); 319 PUSH_DATA (push, (2 << 16) | 2); 320 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1); 321 PUSH_DATA (push, 1); 322 323 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1); 324 PUSH_DATA (push, 0); 325 BEGIN_NVC0(push, SUBC_3D(0x0218), 1); 326 PUSH_DATA (push, 0x10); 327 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1); 328 PUSH_DATA (push, 0x10); 329 BEGIN_NVC0(push, SUBC_3D(0x1290), 1); 330 PUSH_DATA (push, 0x10); 331 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2); 332 PUSH_DATA (push, 0x10); 333 PUSH_DATA (push, 0x10); 334 BEGIN_NVC0(push, SUBC_3D(0x1140), 1); 335 PUSH_DATA (push, 0x10); 336 BEGIN_NVC0(push, SUBC_3D(0x1610), 1); 337 PUSH_DATA (push, 0xe); 338 339 BEGIN_NVC0(push, SUBC_3D(0x164c), 1); 340 PUSH_DATA (push, 1 << 12); 341 BEGIN_NVC0(push, SUBC_3D(0x030c), 1); 342 PUSH_DATA (push, 0); 343 BEGIN_NVC0(push, SUBC_3D(0x0300), 1); 344 PUSH_DATA (push, 3); 345 346 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1); 347 PUSH_DATA (push, 0x3fffff); 348 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1); 349 PUSH_DATA (push, 1); 350 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1); 351 PUSH_DATA (push, 1); 352 BEGIN_NVC0(push, SUBC_3D(0x075c), 1); 353 PUSH_DATA (push, 3); 354 355 if (obj_class >= NVE4_3D_CLASS) { 356 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1); 357 PUSH_DATA (push, 1); 358 } 359 360 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc 361 * are supposed to do */ 362} 363 364static void 365nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 366{ 367 struct nvc0_screen *screen = nvc0_screen(pscreen); 368 struct nouveau_pushbuf *push = screen->base.pushbuf; 369 370 /* we need to do it after possible flush in MARK_RING */ 371 *sequence = ++screen->base.fence.sequence; 372 373 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4); 374 PUSH_DATAh(push, screen->fence.bo->offset); 375 PUSH_DATA (push, screen->fence.bo->offset); 376 PUSH_DATA (push, *sequence); 377 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT | 378 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT)); 379} 380 381static u32 382nvc0_screen_fence_update(struct pipe_screen *pscreen) 383{ 384 struct nvc0_screen *screen = nvc0_screen(pscreen); 385 return screen->fence.map[0]; 386} 387 388#define FAIL_SCREEN_INIT(str, err) \ 389 do { \ 390 NOUVEAU_ERR(str, err); \ 391 nvc0_screen_destroy(pscreen); \ 392 return NULL; \ 393 } while(0) 394 395struct pipe_screen * 396nvc0_screen_create(struct nouveau_device *dev) 397{ 398 struct nvc0_screen *screen; 399 struct pipe_screen *pscreen; 400 struct nouveau_object *chan; 401 struct nouveau_pushbuf *push; 402 uint32_t obj_class; 403 int ret; 404 unsigned i; 405 union nouveau_bo_config mm_config; 406 407 switch (dev->chipset & ~0xf) { 408 case 0xc0: 409 case 0xd0: 410 case 0xe0: 411 break; 412 default: 413 return NULL; 414 } 415 416 screen = CALLOC_STRUCT(nvc0_screen); 417 if (!screen) 418 return NULL; 419 pscreen = &screen->base.base; 420 421 screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER; 422 423 ret = nouveau_screen_init(&screen->base, dev); 424 if (ret) { 425 nvc0_screen_destroy(pscreen); 426 return NULL; 427 } 428 chan = screen->base.channel; 429 push = screen->base.pushbuf; 430 push->user_priv = screen; 431 432 pscreen->destroy = nvc0_screen_destroy; 433 pscreen->context_create = nvc0_create; 434 pscreen->is_format_supported = nvc0_screen_is_format_supported; 435 pscreen->get_param = nvc0_screen_get_param; 436 pscreen->get_shader_param = nvc0_screen_get_shader_param; 437 pscreen->get_paramf = nvc0_screen_get_paramf; 438 439 nvc0_screen_init_resource_functions(pscreen); 440 441 nouveau_screen_init_vdec(&screen->base); 442 443 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL, 444 &screen->fence.bo); 445 if (ret) 446 goto fail; 447 nouveau_bo_map(screen->fence.bo, 0, NULL); 448 screen->fence.map = screen->fence.bo->map; 449 screen->base.fence.emit = nvc0_screen_fence_emit; 450 screen->base.fence.update = nvc0_screen_fence_update; 451 452 switch (dev->chipset & 0xf0) { 453 case 0xe0: 454 obj_class = NVE4_P2MF_CLASS; 455 break; 456 default: 457 obj_class = NVC0_M2MF_CLASS; 458 break; 459 } 460 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0, 461 &screen->m2mf); 462 if (ret) 463 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 464 465 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); 466 PUSH_DATA (push, screen->m2mf->oclass); 467 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) { 468 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1); 469 PUSH_DATA (push, 0xa0b5); 470 } 471 472 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0, 473 &screen->eng2d); 474 if (ret) 475 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 476 477 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); 478 PUSH_DATA (push, screen->eng2d->oclass); 479 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1); 480 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY); 481 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1); 482 PUSH_DATA (push, 0); 483 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1); 484 PUSH_DATA (push, 0); 485 BEGIN_NVC0(push, SUBC_2D(0x0884), 1); 486 PUSH_DATA (push, 0x3f); 487 BEGIN_NVC0(push, SUBC_2D(0x0888), 1); 488 PUSH_DATA (push, 1); 489 490 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2); 491 PUSH_DATAh(push, screen->fence.bo->offset + 16); 492 PUSH_DATA (push, screen->fence.bo->offset + 16); 493 494 switch (dev->chipset & 0xf0) { 495 case 0xe0: 496 obj_class = NVE4_3D_CLASS; 497 break; 498 case 0xd0: 499 case 0xc0: 500 default: 501 switch (dev->chipset) { 502 case 0xd9: 503 case 0xc8: 504 obj_class = NVC8_3D_CLASS; 505 break; 506 case 0xc1: 507 obj_class = NVC1_3D_CLASS; 508 break; 509 default: 510 obj_class = NVC0_3D_CLASS; 511 break; 512 } 513 break; 514 } 515 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0, 516 &screen->eng3d); 517 if (ret) 518 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 519 screen->base.class_3d = obj_class; 520 521 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); 522 PUSH_DATA (push, screen->eng3d->oclass); 523 524 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1); 525 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS); 526 527 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { 528 /* kill shaders after about 1 second (at 100 MHz) */ 529 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1); 530 PUSH_DATA (push, 0x17); 531 } 532 533 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); 534 PUSH_DATA (push, 1); 535 536 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1); 537 PUSH_DATA (push, 0); 538 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1); 539 PUSH_DATA (push, 0); 540 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1); 541 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1); 542 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1); 543 PUSH_DATA (push, 0); 544 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1); 545 PUSH_DATA (push, 1); 546 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1); 547 PUSH_DATA (push, 0); 548 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1); 549 PUSH_DATA (push, 1); 550 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1); 551 PUSH_DATA (push, 0); 552 if (screen->eng3d->oclass < NVE4_3D_CLASS) { 553 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1); 554 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 555 } else { 556 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1); 557 PUSH_DATA (push, 15); 558 } 559 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1); 560 PUSH_DATA (push, 8); /* 128 */ 561 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1); 562 PUSH_DATA (push, 1); 563 if (screen->eng3d->oclass >= NVC1_3D_CLASS) { 564 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1); 565 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1); 566 } 567 568 nvc0_magic_3d_init(push, screen->eng3d->oclass); 569 570 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 571 &screen->text); 572 if (ret) 573 goto fail; 574 575 /* XXX: getting a page fault at the end of the code buffer every few 576 * launches, don't use the last 256 bytes to work around them - prefetch ? 577 */ 578 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100); 579 580 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL, 581 &screen->uniform_bo); 582 if (ret) 583 goto fail; 584 585 for (i = 0; i < 5; ++i) { 586 /* TIC and TSC entries for each unit (nve4+ only) */ 587 /* auxiliary constants (6 user clip planes, base instance id */ 588 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); 589 PUSH_DATA (push, 512); 590 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 591 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 592 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1); 593 PUSH_DATA (push, (15 << 4) | 1); 594 if (screen->eng3d->oclass >= NVE4_3D_CLASS) { 595 unsigned j; 596 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9); 597 PUSH_DATA (push, 0); 598 for (j = 0; j < 8; ++j) 599 PUSH_DATA(push, j); 600 } else { 601 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1); 602 PUSH_DATA (push, 0x54); 603 } 604 } 605 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1); 606 PUSH_DATA (push, 0); 607 608 /* max MPs * max warps per MP (TODO: ask kernel) */ 609 if (screen->eng3d->oclass >= NVE4_3D_CLASS) 610 screen->tls_size = 8 * 64; 611 else 612 screen->tls_size = 16 * 48; 613 screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16; 614 screen->tls_size = align(screen->tls_size, 1 << 17); 615 616 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 617 screen->tls_size, NULL, &screen->tls); 618 if (ret) 619 goto fail; 620 621 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2); 622 PUSH_DATAh(push, screen->text->offset); 623 PUSH_DATA (push, screen->text->offset); 624 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4); 625 PUSH_DATAh(push, screen->tls->offset); 626 PUSH_DATA (push, screen->tls->offset); 627 PUSH_DATA (push, screen->tls_size >> 32); 628 PUSH_DATA (push, screen->tls_size); 629 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1); 630 PUSH_DATA (push, 0); 631 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1); 632 PUSH_DATA (push, 0); 633 634 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 635 &screen->poly_cache); 636 if (ret) 637 goto fail; 638 639 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3); 640 PUSH_DATAh(push, screen->poly_cache->offset); 641 PUSH_DATA (push, screen->poly_cache->offset); 642 PUSH_DATA (push, 3); 643 644 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL, 645 &screen->txc); 646 if (ret) 647 goto fail; 648 649 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3); 650 PUSH_DATAh(push, screen->txc->offset); 651 PUSH_DATA (push, screen->txc->offset); 652 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); 653 654 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3); 655 PUSH_DATAh(push, screen->txc->offset + 65536); 656 PUSH_DATA (push, screen->txc->offset + 65536); 657 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1); 658 659 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1); 660 PUSH_DATA (push, 0); 661 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2); 662 PUSH_DATA (push, 0); 663 PUSH_DATA (push, 0); 664 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 665 PUSH_DATA (push, 0x3f); 666 667 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1); 668 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY); 669 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 670 for (i = 0; i < 8 * 2; ++i) 671 PUSH_DATA(push, 0); 672 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1); 673 PUSH_DATA (push, 0); 674 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1); 675 PUSH_DATA (push, 0); 676 677 /* neither scissors, viewport nor stencil mask should affect clears */ 678 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1); 679 PUSH_DATA (push, 0); 680 681 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1); 682 PUSH_DATA (push, 1); 683 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2); 684 PUSH_DATAf(push, 0.0f); 685 PUSH_DATAf(push, 1.0f); 686 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1); 687 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1); 688 689 /* We use scissors instead of exact view volume clipping, 690 * so they're always enabled. 691 */ 692 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3); 693 PUSH_DATA (push, 1); 694 PUSH_DATA (push, 8192 << 16); 695 PUSH_DATA (push, 8192 << 16); 696 697#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n); 698 699 i = 0; 700 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf); 701 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables); 702 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select); 703 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select); 704 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select); 705 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front); 706 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back); 707 708 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1); 709 PUSH_DATA (push, 1); 710 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1); 711 PUSH_DATA (push, 1); 712 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1); 713 PUSH_DATA (push, 0x40); 714 BEGIN_NVC0(push, NVC0_3D(LAYER), 1); 715 PUSH_DATA (push, 0); 716 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1); 717 PUSH_DATA (push, 0x30); 718 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1); 719 PUSH_DATA (push, 3); 720 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1); 721 PUSH_DATA (push, 0x20); 722 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1); 723 PUSH_DATA (push, 0x00); 724 725 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1); 726 PUSH_DATA (push, 0); 727 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1); 728 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL); 729 730 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1); 731 732 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2); 733 PUSH_DATA (push, 0xab); 734 PUSH_DATA (push, 0x00000000); 735 736 PUSH_KICK (push); 737 738 screen->tic.entries = CALLOC(4096, sizeof(void *)); 739 screen->tsc.entries = screen->tic.entries + 2048; 740 741 mm_config.nvc0.tile_mode = 0; 742 mm_config.nvc0.memtype = 0xfe0; 743 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config); 744 745 if (!nvc0_blitctx_create(screen)) 746 goto fail; 747 748 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 749 750 return pscreen; 751 752fail: 753 nvc0_screen_destroy(pscreen); 754 return NULL; 755} 756 757int 758nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry) 759{ 760 int i = screen->tic.next; 761 762 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 763 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 764 765 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 766 767 if (screen->tic.entries[i]) 768 nv50_tic_entry(screen->tic.entries[i])->id = -1; 769 770 screen->tic.entries[i] = entry; 771 return i; 772} 773 774int 775nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry) 776{ 777 int i = screen->tsc.next; 778 779 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 780 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 781 782 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 783 784 if (screen->tsc.entries[i]) 785 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 786 787 screen->tsc.entries[i] = entry; 788 return i; 789} 790