r600_texture.c revision 0d91ddf1d4be712377e80d330480ff560d449c6f
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include <errno.h> 28#include "pipe/p_screen.h" 29#include "util/u_format.h" 30#include "util/u_format_s3tc.h" 31#include "util/u_math.h" 32#include "util/u_inlines.h" 33#include "util/u_memory.h" 34#include "pipebuffer/pb_buffer.h" 35#include "r600_pipe.h" 36#include "r600_resource.h" 37#include "r600d.h" 38#include "r600_formats.h" 39 40/* Copy from a full GPU texture to a transfer's staging one. */ 41static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 42{ 43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 44 struct pipe_resource *texture = transfer->resource; 45 46 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b.b, 47 0, 0, 0, 0, texture, transfer->level, 48 &transfer->box); 49} 50 51 52/* Copy from a transfer's staging texture to a full GPU one. */ 53static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 54{ 55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 56 struct pipe_resource *texture = transfer->resource; 57 struct pipe_box sbox; 58 59 sbox.x = sbox.y = sbox.z = 0; 60 sbox.width = transfer->box.width; 61 sbox.height = transfer->box.height; 62 /* XXX that might be wrong */ 63 sbox.depth = 1; 64 ctx->resource_copy_region(ctx, texture, transfer->level, 65 transfer->box.x, transfer->box.y, transfer->box.z, 66 &rtransfer->staging->b.b.b, 67 0, &sbox); 68} 69 70unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 71 unsigned level, unsigned layer) 72{ 73 unsigned offset = rtex->offset[level]; 74 75 switch (rtex->resource.b.b.b.target) { 76 case PIPE_TEXTURE_3D: 77 case PIPE_TEXTURE_CUBE: 78 default: 79 return offset + layer * rtex->layer_size[level]; 80 } 81} 82 83static unsigned r600_get_block_alignment(struct pipe_screen *screen, 84 enum pipe_format format, 85 unsigned array_mode) 86{ 87 struct r600_screen* rscreen = (struct r600_screen *)screen; 88 unsigned pixsize = util_format_get_blocksize(format); 89 int p_align; 90 91 switch(array_mode) { 92 case V_038000_ARRAY_1D_TILED_THIN1: 93 p_align = MAX2(8, 94 ((rscreen->tiling_info.group_bytes / 8 / pixsize))); 95 break; 96 case V_038000_ARRAY_2D_TILED_THIN1: 97 p_align = MAX2(rscreen->tiling_info.num_banks, 98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) * 99 rscreen->tiling_info.num_banks)) * 8; 100 break; 101 case V_038000_ARRAY_LINEAR_ALIGNED: 102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize); 103 break; 104 case V_038000_ARRAY_LINEAR_GENERAL: 105 default: 106 p_align = rscreen->tiling_info.group_bytes / pixsize; 107 break; 108 } 109 return p_align; 110} 111 112static unsigned r600_get_height_alignment(struct pipe_screen *screen, 113 unsigned array_mode) 114{ 115 struct r600_screen* rscreen = (struct r600_screen *)screen; 116 int h_align; 117 118 switch (array_mode) { 119 case V_038000_ARRAY_2D_TILED_THIN1: 120 h_align = rscreen->tiling_info.num_channels * 8; 121 break; 122 case V_038000_ARRAY_1D_TILED_THIN1: 123 case V_038000_ARRAY_LINEAR_ALIGNED: 124 h_align = 8; 125 break; 126 case V_038000_ARRAY_LINEAR_GENERAL: 127 default: 128 h_align = 1; 129 break; 130 } 131 return h_align; 132} 133 134static unsigned r600_get_base_alignment(struct pipe_screen *screen, 135 enum pipe_format format, 136 unsigned array_mode) 137{ 138 struct r600_screen* rscreen = (struct r600_screen *)screen; 139 unsigned pixsize = util_format_get_blocksize(format); 140 int p_align = r600_get_block_alignment(screen, format, array_mode); 141 int h_align = r600_get_height_alignment(screen, array_mode); 142 int b_align; 143 144 switch (array_mode) { 145 case V_038000_ARRAY_2D_TILED_THIN1: 146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize, 147 p_align * pixsize * h_align); 148 break; 149 case V_038000_ARRAY_1D_TILED_THIN1: 150 case V_038000_ARRAY_LINEAR_ALIGNED: 151 case V_038000_ARRAY_LINEAR_GENERAL: 152 default: 153 b_align = rscreen->tiling_info.group_bytes; 154 break; 155 } 156 return b_align; 157} 158 159static unsigned mip_minify(unsigned size, unsigned level) 160{ 161 unsigned val; 162 val = u_minify(size, level); 163 if (level > 0) 164 val = util_next_power_of_two(val); 165 return val; 166} 167 168static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, 169 struct r600_resource_texture *rtex, 170 unsigned level) 171{ 172 struct pipe_resource *ptex = &rtex->resource.b.b.b; 173 unsigned nblocksx, block_align, width; 174 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 175 176 if (rtex->pitch_override) 177 return rtex->pitch_override / blocksize; 178 179 width = mip_minify(ptex->width0, level); 180 nblocksx = util_format_get_nblocksx(rtex->real_format, width); 181 182 block_align = r600_get_block_alignment(screen, rtex->real_format, 183 rtex->array_mode[level]); 184 nblocksx = align(nblocksx, block_align); 185 return nblocksx; 186} 187 188static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, 189 struct r600_resource_texture *rtex, 190 unsigned level) 191{ 192 struct pipe_resource *ptex = &rtex->resource.b.b.b; 193 unsigned height, tile_height; 194 195 height = mip_minify(ptex->height0, level); 196 height = util_format_get_nblocksy(rtex->real_format, height); 197 tile_height = r600_get_height_alignment(screen, 198 rtex->array_mode[level]); 199 200 /* XXX Hack around an alignment issue. Less tests fail with this. 201 * 202 * The thing is depth-stencil buffers should be tiled, i.e. 203 * the alignment should be >=8. If I make them tiled, stencil starts 204 * working because it no longer overlaps with the depth buffer 205 * in memory, but texturing like drawpix-stencil breaks. */ 206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) 207 tile_height = 8; 208 209 height = align(height, tile_height); 210 return height; 211} 212 213static void r600_texture_set_array_mode(struct pipe_screen *screen, 214 struct r600_resource_texture *rtex, 215 unsigned level, unsigned array_mode) 216{ 217 struct pipe_resource *ptex = &rtex->resource.b.b.b; 218 219 switch (array_mode) { 220 case V_0280A0_ARRAY_LINEAR_GENERAL: 221 case V_0280A0_ARRAY_LINEAR_ALIGNED: 222 case V_0280A0_ARRAY_1D_TILED_THIN1: 223 default: 224 rtex->array_mode[level] = array_mode; 225 break; 226 case V_0280A0_ARRAY_2D_TILED_THIN1: 227 { 228 unsigned w, h, tile_height, tile_width; 229 230 tile_height = r600_get_height_alignment(screen, array_mode); 231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); 232 233 w = mip_minify(ptex->width0, level); 234 h = mip_minify(ptex->height0, level); 235 if (w <= tile_width || h <= tile_height) 236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; 237 else 238 rtex->array_mode[level] = array_mode; 239 } 240 break; 241 } 242} 243 244static int r600_init_surface(struct radeon_surface *surface, 245 const struct pipe_resource *ptex, 246 unsigned array_mode) 247{ 248 surface->npix_x = ptex->width0; 249 surface->npix_y = ptex->height0; 250 surface->npix_z = ptex->depth0; 251 surface->blk_w = util_format_get_blockwidth(ptex->format); 252 surface->blk_h = util_format_get_blockheight(ptex->format); 253 surface->blk_d = 1; 254 surface->array_size = 1; 255 surface->last_level = ptex->last_level; 256 surface->bpe = util_format_get_blocksize(ptex->format); 257 /* align byte per element on dword */ 258 if (surface->bpe == 3) { 259 surface->bpe = 4; 260 } 261 surface->nsamples = 1; 262 surface->flags = 0; 263 switch (array_mode) { 264 case V_038000_ARRAY_1D_TILED_THIN1: 265 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 266 break; 267 case V_038000_ARRAY_2D_TILED_THIN1: 268 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 269 break; 270 case V_038000_ARRAY_LINEAR_ALIGNED: 271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 272 break; 273 case V_038000_ARRAY_LINEAR_GENERAL: 274 default: 275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 276 break; 277 } 278 switch (ptex->target) { 279 case PIPE_TEXTURE_1D: 280 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 281 break; 282 case PIPE_TEXTURE_RECT: 283 case PIPE_TEXTURE_2D: 284 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 285 break; 286 case PIPE_TEXTURE_3D: 287 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 288 break; 289 case PIPE_TEXTURE_1D_ARRAY: 290 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 291 surface->array_size = ptex->array_size; 292 break; 293 case PIPE_TEXTURE_2D_ARRAY: 294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 295 surface->array_size = ptex->array_size; 296 break; 297 case PIPE_TEXTURE_CUBE: 298 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 299 break; 300 case PIPE_BUFFER: 301 default: 302 return -EINVAL; 303 } 304 if (ptex->bind & PIPE_BIND_SCANOUT) { 305 surface->flags |= RADEON_SURF_SCANOUT; 306 } 307 if (util_format_is_depth_and_stencil(ptex->format)) { 308 surface->flags |= RADEON_SURF_ZBUFFER; 309 surface->flags |= RADEON_SURF_SBUFFER; 310 } 311 312 return 0; 313} 314 315static int r600_setup_surface(struct pipe_screen *screen, 316 struct r600_resource_texture *rtex, 317 unsigned array_mode, 318 unsigned pitch_in_bytes_override) 319{ 320 struct pipe_resource *ptex = &rtex->resource.b.b.b; 321 struct r600_screen *rscreen = (struct r600_screen*)screen; 322 unsigned i; 323 int r; 324 325 if (util_format_is_depth_or_stencil(rtex->real_format)) { 326 rtex->surface.flags |= RADEON_SURF_ZBUFFER; 327 rtex->surface.flags |= RADEON_SURF_SBUFFER; 328 } 329 330 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 331 if (r) { 332 return r; 333 } 334 rtex->size = rtex->surface.bo_size; 335 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 336 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 337 * for those 338 */ 339 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 340 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 341 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 342 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 343 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 344 } 345 } 346 for (i = 0; i <= ptex->last_level; i++) { 347 rtex->offset[i] = rtex->surface.level[i].offset; 348 rtex->layer_size[i] = rtex->surface.level[i].slice_size; 349 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes; 350 switch (rtex->surface.level[i].mode) { 351 case RADEON_SURF_MODE_LINEAR_ALIGNED: 352 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 353 break; 354 case RADEON_SURF_MODE_1D: 355 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 356 break; 357 case RADEON_SURF_MODE_2D: 358 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 359 break; 360 default: 361 case RADEON_SURF_MODE_LINEAR: 362 rtex->array_mode[i] = 0; 363 break; 364 } 365 } 366 return 0; 367} 368 369static void r600_setup_miptree(struct pipe_screen *screen, 370 struct r600_resource_texture *rtex, 371 unsigned array_mode) 372{ 373 struct pipe_resource *ptex = &rtex->resource.b.b.b; 374 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class; 375 unsigned size, layer_size, i, offset; 376 unsigned nblocksx, nblocksy; 377 378 for (i = 0, offset = 0; i <= ptex->last_level; i++) { 379 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 380 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); 381 382 r600_texture_set_array_mode(screen, rtex, i, array_mode); 383 384 nblocksx = r600_texture_get_nblocksx(screen, rtex, i); 385 nblocksy = r600_texture_get_nblocksy(screen, rtex, i); 386 387 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL) 388 layer_size = align(nblocksx, 64) * nblocksy * blocksize; 389 else 390 layer_size = nblocksx * nblocksy * blocksize; 391 392 if (ptex->target == PIPE_TEXTURE_CUBE) { 393 if (chipc >= R700) 394 size = layer_size * 8; 395 else 396 size = layer_size * 6; 397 } 398 else if (ptex->target == PIPE_TEXTURE_3D) 399 size = layer_size * u_minify(ptex->depth0, i); 400 else 401 size = layer_size * ptex->array_size; 402 403 /* align base image and start of miptree */ 404 if ((i == 0) || (i == 1)) 405 offset = align(offset, base_align); 406 rtex->offset[i] = offset; 407 rtex->layer_size[i] = layer_size; 408 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ 409 rtex->pitch_in_bytes[i] = nblocksx * blocksize; 410 411 offset += size; 412 } 413 rtex->size = offset; 414} 415 416/* Figure out whether u_blitter will fallback to a transfer operation. 417 * If so, don't use a staging resource. 418 */ 419static boolean permit_hardware_blit(struct pipe_screen *screen, 420 const struct pipe_resource *res) 421{ 422 unsigned bind; 423 424 if (util_format_is_depth_or_stencil(res->format)) 425 bind = PIPE_BIND_DEPTH_STENCIL; 426 else 427 bind = PIPE_BIND_RENDER_TARGET; 428 429 /* hackaround for S3TC */ 430 if (util_format_is_compressed(res->format)) 431 return TRUE; 432 433 if (!screen->is_format_supported(screen, 434 res->format, 435 res->target, 436 res->nr_samples, 437 bind)) 438 return FALSE; 439 440 if (!screen->is_format_supported(screen, 441 res->format, 442 res->target, 443 res->nr_samples, 444 PIPE_BIND_SAMPLER_VIEW)) 445 return FALSE; 446 447 return TRUE; 448} 449 450static boolean r600_texture_get_handle(struct pipe_screen* screen, 451 struct pipe_resource *ptex, 452 struct winsys_handle *whandle) 453{ 454 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 455 struct r600_resource *resource = &rtex->resource; 456 struct r600_screen *rscreen = (struct r600_screen*)screen; 457 458 return rscreen->ws->buffer_get_handle(resource->buf, 459 rtex->pitch_in_bytes[0], whandle); 460} 461 462static void r600_texture_destroy(struct pipe_screen *screen, 463 struct pipe_resource *ptex) 464{ 465 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 466 struct r600_resource *resource = &rtex->resource; 467 468 if (rtex->flushed_depth_texture) 469 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 470 471 if (rtex->stencil) 472 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL); 473 474 pb_reference(&resource->buf, NULL); 475 FREE(rtex); 476} 477 478static const struct u_resource_vtbl r600_texture_vtbl = 479{ 480 r600_texture_get_handle, /* get_handle */ 481 r600_texture_destroy, /* resource_destroy */ 482 r600_texture_get_transfer, /* get_transfer */ 483 r600_texture_transfer_destroy, /* transfer_destroy */ 484 r600_texture_transfer_map, /* transfer_map */ 485 NULL, /* transfer_flush_region */ 486 r600_texture_transfer_unmap, /* transfer_unmap */ 487 NULL /* transfer_inline_write */ 488}; 489 490static struct r600_resource_texture * 491r600_texture_create_object(struct pipe_screen *screen, 492 const struct pipe_resource *base, 493 unsigned array_mode, 494 unsigned pitch_in_bytes_override, 495 unsigned max_buffer_size, 496 struct pb_buffer *buf, 497 boolean alloc_bo, 498 struct radeon_surface *surface) 499{ 500 struct r600_resource_texture *rtex; 501 struct r600_resource *resource; 502 struct r600_screen *rscreen = (struct r600_screen*)screen; 503 int r; 504 505 rtex = CALLOC_STRUCT(r600_resource_texture); 506 if (rtex == NULL) 507 return NULL; 508 509 resource = &rtex->resource; 510 resource->b.b.b = *base; 511 resource->b.b.vtbl = &r600_texture_vtbl; 512 pipe_reference_init(&resource->b.b.b.reference, 1); 513 resource->b.b.b.screen = screen; 514 rtex->pitch_override = pitch_in_bytes_override; 515 rtex->real_format = base->format; 516 517 /* We must split depth and stencil into two separate buffers on Evergreen. */ 518 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) && 519 ((struct r600_screen*)screen)->chip_class >= EVERGREEN && 520 util_format_is_depth_and_stencil(base->format) && 521 !rscreen->use_surface_alloc) { 522 struct pipe_resource stencil; 523 unsigned stencil_pitch_override = 0; 524 525 switch (base->format) { 526 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 527 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; 528 break; 529 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 530 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; 531 break; 532 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 533 rtex->real_format = PIPE_FORMAT_Z32_FLOAT; 534 break; 535 default: 536 assert(0); 537 FREE(rtex); 538 return NULL; 539 } 540 541 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ 542 if (pitch_in_bytes_override) { 543 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT || 544 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM); 545 stencil_pitch_override = pitch_in_bytes_override / 4; 546 } 547 548 /* Allocate the stencil buffer. */ 549 stencil = *base; 550 stencil.format = PIPE_FORMAT_S8_UINT; 551 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, 552 stencil_pitch_override, 553 max_buffer_size, NULL, FALSE, surface); 554 if (!rtex->stencil) { 555 FREE(rtex); 556 return NULL; 557 } 558 /* Proceed in creating the depth buffer. */ 559 } 560 561 /* only mark depth textures the HW can hit as depth textures */ 562 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base)) 563 rtex->is_depth = true; 564 565 r600_setup_miptree(screen, rtex, array_mode); 566 if (rscreen->use_surface_alloc) { 567 rtex->surface = *surface; 568 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override); 569 if (r) { 570 FREE(rtex); 571 return NULL; 572 } 573 } 574 575 /* If we initialized separate stencil for Evergreen. place it after depth. */ 576 if (rtex->stencil) { 577 unsigned stencil_align, stencil_offset; 578 579 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); 580 stencil_offset = align(rtex->size, stencil_align); 581 582 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++) 583 rtex->stencil->offset[i] += stencil_offset; 584 585 rtex->size = stencil_offset + rtex->stencil->size; 586 } 587 588 /* Now create the backing buffer. */ 589 if (!buf && alloc_bo) { 590 struct pipe_resource *ptex = &rtex->resource.b.b.b; 591 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); 592 593 if (rscreen->use_surface_alloc) { 594 base_align = rtex->surface.bo_alignment; 595 } else if (util_format_is_depth_or_stencil(rtex->real_format)) { 596 /* ugly work around depth buffer need stencil room at end of bo */ 597 rtex->size += ptex->width0 * ptex->height0; 598 } 599 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 600 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); 601 FREE(rtex); 602 return NULL; 603 } 604 } else if (buf) { 605 resource->buf = buf; 606 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 607 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 608 } 609 610 if (rtex->stencil) { 611 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf); 612 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf; 613 rtex->stencil->resource.domains = rtex->resource.domains; 614 } 615 return rtex; 616} 617 618struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 619 const struct pipe_resource *templ) 620{ 621 struct r600_screen *rscreen = (struct r600_screen*)screen; 622 struct radeon_surface surface; 623 unsigned array_mode = 0; 624 int r; 625 626 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 627 if (rscreen->use_surface_alloc && 628 !(templ->bind & PIPE_BIND_SCANOUT) && 629 templ->usage != PIPE_USAGE_STAGING && 630 templ->usage != PIPE_USAGE_STREAM && 631 permit_hardware_blit(screen, templ)) { 632 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 633 } else if (util_format_is_compressed(templ->format)) { 634 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 635 } 636 } 637 638 r = r600_init_surface(&surface, templ, array_mode); 639 if (r) { 640 return NULL; 641 } 642 r = rscreen->ws->surface_best(rscreen->ws, &surface); 643 if (r) { 644 return NULL; 645 } 646 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 647 0, 0, NULL, TRUE, &surface); 648} 649 650static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 651 struct pipe_resource *texture, 652 const struct pipe_surface *surf_tmpl) 653{ 654 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 655 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 656 unsigned level = surf_tmpl->u.tex.level; 657 658 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 659 if (surface == NULL) 660 return NULL; 661 pipe_reference_init(&surface->base.reference, 1); 662 pipe_resource_reference(&surface->base.texture, texture); 663 surface->base.context = pipe; 664 surface->base.format = surf_tmpl->format; 665 surface->base.width = mip_minify(texture->width0, level); 666 surface->base.height = mip_minify(texture->height0, level); 667 surface->base.usage = surf_tmpl->usage; 668 surface->base.texture = texture; 669 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 670 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 671 surface->base.u.tex.level = level; 672 673 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, 674 rtex, level); 675 return &surface->base; 676} 677 678static void r600_surface_destroy(struct pipe_context *pipe, 679 struct pipe_surface *surface) 680{ 681 pipe_resource_reference(&surface->texture, NULL); 682 FREE(surface); 683} 684 685struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 686 const struct pipe_resource *templ, 687 struct winsys_handle *whandle) 688{ 689 struct r600_screen *rscreen = (struct r600_screen*)screen; 690 struct pb_buffer *buf = NULL; 691 unsigned stride = 0; 692 unsigned array_mode = 0; 693 enum radeon_bo_layout micro, macro; 694 struct radeon_surface surface; 695 int r; 696 697 /* Support only 2D textures without mipmaps */ 698 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 699 templ->depth0 != 1 || templ->last_level != 0) 700 return NULL; 701 702 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 703 if (!buf) 704 return NULL; 705 706 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 707 &surface.bankw, &surface.bankh, 708 &surface.tile_split, 709 &surface.stencil_tile_split, 710 &surface.mtilea); 711 712 if (macro == RADEON_LAYOUT_TILED) 713 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 714 else if (micro == RADEON_LAYOUT_TILED) 715 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 716 else 717 array_mode = 0; 718 719 r = r600_init_surface(&surface, templ, array_mode); 720 if (r) { 721 return NULL; 722 } 723 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 724 stride, 0, buf, FALSE, &surface); 725} 726 727int r600_texture_depth_flush(struct pipe_context *ctx, 728 struct pipe_resource *texture, boolean just_create) 729{ 730 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 731 struct pipe_resource resource; 732 733 if (rtex->flushed_depth_texture) 734 goto out; 735 736 resource.target = texture->target; 737 resource.format = texture->format; 738 resource.width0 = texture->width0; 739 resource.height0 = texture->height0; 740 resource.depth0 = texture->depth0; 741 resource.array_size = texture->array_size; 742 resource.last_level = texture->last_level; 743 resource.nr_samples = texture->nr_samples; 744 resource.usage = PIPE_USAGE_DYNAMIC; 745 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL; 746 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags; 747 748 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 749 if (rtex->flushed_depth_texture == NULL) { 750 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 751 return -ENOMEM; 752 } 753 754 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE; 755out: 756 if (just_create) 757 return 0; 758 759 /* XXX: only do this if the depth texture has actually changed: 760 */ 761 r600_blit_uncompress_depth(ctx, rtex); 762 return 0; 763} 764 765/* Needs adjustment for pixelformat: 766 */ 767static INLINE unsigned u_box_volume( const struct pipe_box *box ) 768{ 769 return box->width * box->depth * box->height; 770}; 771 772struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 773 struct pipe_resource *texture, 774 unsigned level, 775 unsigned usage, 776 const struct pipe_box *box) 777{ 778 struct r600_context *rctx = (struct r600_context*)ctx; 779 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 780 struct pipe_resource resource; 781 struct r600_transfer *trans; 782 int r; 783 boolean use_staging_texture = FALSE; 784 785 /* We cannot map a tiled texture directly because the data is 786 * in a different order, therefore we do detiling using a blit. 787 * 788 * Also, use a temporary in GTT memory for read transfers, as 789 * the CPU is much happier reading out of cached system memory 790 * than uncached VRAM. 791 */ 792 if (R600_TEX_IS_TILED(rtex, level)) 793 use_staging_texture = TRUE; 794 795 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 796 use_staging_texture = TRUE; 797 798 /* Use a staging texture for uploads if the underlying BO is busy. */ 799 if (!(usage & PIPE_TRANSFER_READ) && 800 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 801 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) 802 use_staging_texture = TRUE; 803 804 if (!permit_hardware_blit(ctx->screen, texture) || 805 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) 806 use_staging_texture = FALSE; 807 808 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) 809 return NULL; 810 811 trans = CALLOC_STRUCT(r600_transfer); 812 if (trans == NULL) 813 return NULL; 814 pipe_resource_reference(&trans->transfer.resource, texture); 815 trans->transfer.level = level; 816 trans->transfer.usage = usage; 817 trans->transfer.box = *box; 818 if (rtex->is_depth) { 819 /* XXX: only readback the rectangle which is being mapped? 820 */ 821 /* XXX: when discard is true, no need to read back from depth texture 822 */ 823 r = r600_texture_depth_flush(ctx, texture, FALSE); 824 if (r < 0) { 825 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 826 pipe_resource_reference(&trans->transfer.resource, NULL); 827 FREE(trans); 828 return NULL; 829 } 830 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level]; 831 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); 832 return &trans->transfer; 833 } else if (use_staging_texture) { 834 resource.target = PIPE_TEXTURE_2D; 835 resource.format = texture->format; 836 resource.width0 = box->width; 837 resource.height0 = box->height; 838 resource.depth0 = 1; 839 resource.array_size = 1; 840 resource.last_level = 0; 841 resource.nr_samples = 0; 842 resource.usage = PIPE_USAGE_STAGING; 843 resource.bind = 0; 844 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 845 /* For texture reading, the temporary (detiled) texture is used as 846 * a render target when blitting from a tiled texture. */ 847 if (usage & PIPE_TRANSFER_READ) { 848 resource.bind |= PIPE_BIND_RENDER_TARGET; 849 } 850 /* For texture writing, the temporary texture is used as a sampler 851 * when blitting into a tiled texture. */ 852 if (usage & PIPE_TRANSFER_WRITE) { 853 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 854 } 855 /* Create the temporary texture. */ 856 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 857 if (trans->staging == NULL) { 858 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 859 pipe_resource_reference(&trans->transfer.resource, NULL); 860 FREE(trans); 861 return NULL; 862 } 863 864 trans->transfer.stride = 865 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0]; 866 if (usage & PIPE_TRANSFER_READ) { 867 r600_copy_to_staging_texture(ctx, trans); 868 /* Always referenced in the blit. */ 869 r600_flush(ctx, NULL, 0); 870 } 871 return &trans->transfer; 872 } 873 trans->transfer.stride = rtex->pitch_in_bytes[level]; 874 trans->transfer.layer_stride = rtex->layer_size[level]; 875 trans->offset = r600_texture_get_offset(rtex, level, box->z); 876 return &trans->transfer; 877} 878 879void r600_texture_transfer_destroy(struct pipe_context *ctx, 880 struct pipe_transfer *transfer) 881{ 882 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 883 struct pipe_resource *texture = transfer->resource; 884 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 885 886 if (rtransfer->staging) { 887 if (transfer->usage & PIPE_TRANSFER_WRITE) { 888 r600_copy_from_staging_texture(ctx, rtransfer); 889 } 890 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 891 } 892 893 if (rtex->is_depth && !rtex->is_flushing_texture) { 894 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) 895 r600_blit_push_depth(ctx, rtex); 896 } 897 898 pipe_resource_reference(&transfer->resource, NULL); 899 FREE(transfer); 900} 901 902void* r600_texture_transfer_map(struct pipe_context *ctx, 903 struct pipe_transfer* transfer) 904{ 905 struct r600_context *rctx = (struct r600_context *)ctx; 906 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 907 struct pb_buffer *buf; 908 enum pipe_format format = transfer->resource->format; 909 unsigned offset = 0; 910 char *map; 911 912 if (rtransfer->staging) { 913 buf = ((struct r600_resource *)rtransfer->staging)->buf; 914 } else { 915 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 916 917 if (rtex->flushed_depth_texture) 918 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 919 else 920 buf = ((struct r600_resource *)transfer->resource)->buf; 921 922 offset = rtransfer->offset + 923 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 924 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 925 } 926 927 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 928 return NULL; 929 } 930 931 return map + offset; 932} 933 934void r600_texture_transfer_unmap(struct pipe_context *ctx, 935 struct pipe_transfer* transfer) 936{ 937 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 938 struct r600_context *rctx = (struct r600_context*)ctx; 939 struct pb_buffer *buf; 940 941 if (rtransfer->staging) { 942 buf = ((struct r600_resource *)rtransfer->staging)->buf; 943 } else { 944 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 945 946 if (rtex->flushed_depth_texture) { 947 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 948 } else { 949 buf = ((struct r600_resource *)transfer->resource)->buf; 950 } 951 } 952 rctx->ws->buffer_unmap(buf); 953} 954 955void r600_init_surface_functions(struct r600_context *r600) 956{ 957 r600->context.create_surface = r600_create_surface; 958 r600->context.surface_destroy = r600_surface_destroy; 959} 960 961static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 962 const unsigned char *swizzle_view) 963{ 964 unsigned i; 965 unsigned char swizzle[4]; 966 unsigned result = 0; 967 const uint32_t swizzle_shift[4] = { 968 16, 19, 22, 25, 969 }; 970 const uint32_t swizzle_bit[4] = { 971 0, 1, 2, 3, 972 }; 973 974 if (swizzle_view) { 975 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 976 } else { 977 memcpy(swizzle, swizzle_format, 4); 978 } 979 980 /* Get swizzle. */ 981 for (i = 0; i < 4; i++) { 982 switch (swizzle[i]) { 983 case UTIL_FORMAT_SWIZZLE_Y: 984 result |= swizzle_bit[1] << swizzle_shift[i]; 985 break; 986 case UTIL_FORMAT_SWIZZLE_Z: 987 result |= swizzle_bit[2] << swizzle_shift[i]; 988 break; 989 case UTIL_FORMAT_SWIZZLE_W: 990 result |= swizzle_bit[3] << swizzle_shift[i]; 991 break; 992 case UTIL_FORMAT_SWIZZLE_0: 993 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 994 break; 995 case UTIL_FORMAT_SWIZZLE_1: 996 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 997 break; 998 default: /* UTIL_FORMAT_SWIZZLE_X */ 999 result |= swizzle_bit[0] << swizzle_shift[i]; 1000 } 1001 } 1002 return result; 1003} 1004 1005/* texture format translate */ 1006uint32_t r600_translate_texformat(struct pipe_screen *screen, 1007 enum pipe_format format, 1008 const unsigned char *swizzle_view, 1009 uint32_t *word4_p, uint32_t *yuv_format_p) 1010{ 1011 uint32_t result = 0, word4 = 0, yuv_format = 0; 1012 const struct util_format_description *desc; 1013 boolean uniform = TRUE; 1014 static int r600_enable_s3tc = -1; 1015 bool is_srgb_valid = FALSE; 1016 1017 int i; 1018 const uint32_t sign_bit[4] = { 1019 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 1020 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 1021 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 1022 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 1023 }; 1024 desc = util_format_description(format); 1025 1026 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 1027 1028 /* Colorspace (return non-RGB formats directly). */ 1029 switch (desc->colorspace) { 1030 /* Depth stencil formats */ 1031 case UTIL_FORMAT_COLORSPACE_ZS: 1032 switch (format) { 1033 case PIPE_FORMAT_Z16_UNORM: 1034 result = FMT_16; 1035 goto out_word4; 1036 case PIPE_FORMAT_X24S8_UINT: 1037 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1038 case PIPE_FORMAT_Z24X8_UNORM: 1039 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1040 result = FMT_8_24; 1041 goto out_word4; 1042 case PIPE_FORMAT_S8X24_UINT: 1043 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1044 case PIPE_FORMAT_X8Z24_UNORM: 1045 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1046 result = FMT_24_8; 1047 goto out_word4; 1048 case PIPE_FORMAT_S8_UINT: 1049 result = FMT_8; 1050 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1051 goto out_word4; 1052 case PIPE_FORMAT_Z32_FLOAT: 1053 result = FMT_32_FLOAT; 1054 goto out_word4; 1055 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1056 result = FMT_X24_8_32_FLOAT; 1057 goto out_word4; 1058 default: 1059 goto out_unknown; 1060 } 1061 1062 case UTIL_FORMAT_COLORSPACE_YUV: 1063 yuv_format |= (1 << 30); 1064 switch (format) { 1065 case PIPE_FORMAT_UYVY: 1066 case PIPE_FORMAT_YUYV: 1067 default: 1068 break; 1069 } 1070 goto out_unknown; /* XXX */ 1071 1072 case UTIL_FORMAT_COLORSPACE_SRGB: 1073 word4 |= S_038010_FORCE_DEGAMMA(1); 1074 break; 1075 1076 default: 1077 break; 1078 } 1079 1080 if (r600_enable_s3tc == -1) { 1081 struct r600_screen *rscreen = (struct r600_screen *)screen; 1082 if (rscreen->info.drm_minor >= 9) 1083 r600_enable_s3tc = 1; 1084 else 1085 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 1086 } 1087 1088 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1089 if (!r600_enable_s3tc) 1090 goto out_unknown; 1091 1092 switch (format) { 1093 case PIPE_FORMAT_RGTC1_SNORM: 1094 case PIPE_FORMAT_LATC1_SNORM: 1095 word4 |= sign_bit[0]; 1096 case PIPE_FORMAT_RGTC1_UNORM: 1097 case PIPE_FORMAT_LATC1_UNORM: 1098 result = FMT_BC4; 1099 goto out_word4; 1100 case PIPE_FORMAT_RGTC2_SNORM: 1101 case PIPE_FORMAT_LATC2_SNORM: 1102 word4 |= sign_bit[0] | sign_bit[1]; 1103 case PIPE_FORMAT_RGTC2_UNORM: 1104 case PIPE_FORMAT_LATC2_UNORM: 1105 result = FMT_BC5; 1106 goto out_word4; 1107 default: 1108 goto out_unknown; 1109 } 1110 } 1111 1112 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1113 1114 if (!r600_enable_s3tc) 1115 goto out_unknown; 1116 1117 if (!util_format_s3tc_enabled) { 1118 goto out_unknown; 1119 } 1120 1121 switch (format) { 1122 case PIPE_FORMAT_DXT1_RGB: 1123 case PIPE_FORMAT_DXT1_RGBA: 1124 case PIPE_FORMAT_DXT1_SRGB: 1125 case PIPE_FORMAT_DXT1_SRGBA: 1126 result = FMT_BC1; 1127 is_srgb_valid = TRUE; 1128 goto out_word4; 1129 case PIPE_FORMAT_DXT3_RGBA: 1130 case PIPE_FORMAT_DXT3_SRGBA: 1131 result = FMT_BC2; 1132 is_srgb_valid = TRUE; 1133 goto out_word4; 1134 case PIPE_FORMAT_DXT5_RGBA: 1135 case PIPE_FORMAT_DXT5_SRGBA: 1136 result = FMT_BC3; 1137 is_srgb_valid = TRUE; 1138 goto out_word4; 1139 default: 1140 goto out_unknown; 1141 } 1142 } 1143 1144 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1145 result = FMT_5_9_9_9_SHAREDEXP; 1146 goto out_word4; 1147 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1148 result = FMT_10_11_11_FLOAT; 1149 goto out_word4; 1150 } 1151 1152 1153 for (i = 0; i < desc->nr_channels; i++) { 1154 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1155 word4 |= sign_bit[i]; 1156 } 1157 } 1158 1159 /* R8G8Bx_SNORM - XXX CxV8U8 */ 1160 1161 /* See whether the components are of the same size. */ 1162 for (i = 1; i < desc->nr_channels; i++) { 1163 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1164 } 1165 1166 /* Non-uniform formats. */ 1167 if (!uniform) { 1168 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1169 desc->channel[0].pure_integer) 1170 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1171 switch(desc->nr_channels) { 1172 case 3: 1173 if (desc->channel[0].size == 5 && 1174 desc->channel[1].size == 6 && 1175 desc->channel[2].size == 5) { 1176 result = FMT_5_6_5; 1177 goto out_word4; 1178 } 1179 goto out_unknown; 1180 case 4: 1181 if (desc->channel[0].size == 5 && 1182 desc->channel[1].size == 5 && 1183 desc->channel[2].size == 5 && 1184 desc->channel[3].size == 1) { 1185 result = FMT_1_5_5_5; 1186 goto out_word4; 1187 } 1188 if (desc->channel[0].size == 10 && 1189 desc->channel[1].size == 10 && 1190 desc->channel[2].size == 10 && 1191 desc->channel[3].size == 2) { 1192 result = FMT_2_10_10_10; 1193 goto out_word4; 1194 } 1195 goto out_unknown; 1196 } 1197 goto out_unknown; 1198 } 1199 1200 /* Find the first non-VOID channel. */ 1201 for (i = 0; i < 4; i++) { 1202 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1203 break; 1204 } 1205 } 1206 1207 if (i == 4) 1208 goto out_unknown; 1209 1210 /* uniform formats */ 1211 switch (desc->channel[i].type) { 1212 case UTIL_FORMAT_TYPE_UNSIGNED: 1213 case UTIL_FORMAT_TYPE_SIGNED: 1214#if 0 1215 if (!desc->channel[i].normalized && 1216 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 1217 goto out_unknown; 1218 } 1219#endif 1220 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1221 desc->channel[i].pure_integer) 1222 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1223 1224 switch (desc->channel[i].size) { 1225 case 4: 1226 switch (desc->nr_channels) { 1227 case 2: 1228 result = FMT_4_4; 1229 goto out_word4; 1230 case 4: 1231 result = FMT_4_4_4_4; 1232 goto out_word4; 1233 } 1234 goto out_unknown; 1235 case 8: 1236 switch (desc->nr_channels) { 1237 case 1: 1238 result = FMT_8; 1239 goto out_word4; 1240 case 2: 1241 result = FMT_8_8; 1242 goto out_word4; 1243 case 4: 1244 result = FMT_8_8_8_8; 1245 is_srgb_valid = TRUE; 1246 goto out_word4; 1247 } 1248 goto out_unknown; 1249 case 16: 1250 switch (desc->nr_channels) { 1251 case 1: 1252 result = FMT_16; 1253 goto out_word4; 1254 case 2: 1255 result = FMT_16_16; 1256 goto out_word4; 1257 case 4: 1258 result = FMT_16_16_16_16; 1259 goto out_word4; 1260 } 1261 goto out_unknown; 1262 case 32: 1263 switch (desc->nr_channels) { 1264 case 1: 1265 result = FMT_32; 1266 goto out_word4; 1267 case 2: 1268 result = FMT_32_32; 1269 goto out_word4; 1270 case 4: 1271 result = FMT_32_32_32_32; 1272 goto out_word4; 1273 } 1274 } 1275 goto out_unknown; 1276 1277 case UTIL_FORMAT_TYPE_FLOAT: 1278 switch (desc->channel[i].size) { 1279 case 16: 1280 switch (desc->nr_channels) { 1281 case 1: 1282 result = FMT_16_FLOAT; 1283 goto out_word4; 1284 case 2: 1285 result = FMT_16_16_FLOAT; 1286 goto out_word4; 1287 case 4: 1288 result = FMT_16_16_16_16_FLOAT; 1289 goto out_word4; 1290 } 1291 goto out_unknown; 1292 case 32: 1293 switch (desc->nr_channels) { 1294 case 1: 1295 result = FMT_32_FLOAT; 1296 goto out_word4; 1297 case 2: 1298 result = FMT_32_32_FLOAT; 1299 goto out_word4; 1300 case 4: 1301 result = FMT_32_32_32_32_FLOAT; 1302 goto out_word4; 1303 } 1304 } 1305 goto out_unknown; 1306 } 1307 1308out_word4: 1309 1310 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1311 return ~0; 1312 if (word4_p) 1313 *word4_p = word4; 1314 if (yuv_format_p) 1315 *yuv_format_p = yuv_format; 1316 return result; 1317out_unknown: 1318 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1319 return ~0; 1320} 1321