r600_texture.c revision 702838a7061cde91a6bcdd3382817deb61218bf1
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include <errno.h> 28#include <pipe/p_screen.h> 29#include <util/u_format.h> 30#include <util/u_format_s3tc.h> 31#include <util/u_math.h> 32#include <util/u_inlines.h> 33#include <util/u_memory.h> 34#include "pipebuffer/pb_buffer.h" 35#include "r600_pipe.h" 36#include "r600_resource.h" 37#include "r600d.h" 38#include "r600_formats.h" 39 40/* Copy from a full GPU texture to a transfer's staging one. */ 41static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 42{ 43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 44 struct pipe_resource *texture = transfer->resource; 45 46 ctx->resource_copy_region(ctx, rtransfer->staging_texture, 47 0, 0, 0, 0, texture, transfer->level, 48 &transfer->box); 49} 50 51 52/* Copy from a transfer's staging texture to a full GPU one. */ 53static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 54{ 55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 56 struct pipe_resource *texture = transfer->resource; 57 struct pipe_box sbox; 58 59 sbox.x = sbox.y = sbox.z = 0; 60 sbox.width = transfer->box.width; 61 sbox.height = transfer->box.height; 62 /* XXX that might be wrong */ 63 sbox.depth = 1; 64 ctx->resource_copy_region(ctx, texture, transfer->level, 65 transfer->box.x, transfer->box.y, transfer->box.z, 66 rtransfer->staging_texture, 67 0, &sbox); 68 69 r600_flush(ctx, NULL, RADEON_FLUSH_ASYNC); 70} 71 72unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 73 unsigned level, unsigned layer) 74{ 75 unsigned offset = rtex->offset[level]; 76 77 switch (rtex->resource.b.b.b.target) { 78 case PIPE_TEXTURE_3D: 79 case PIPE_TEXTURE_CUBE: 80 default: 81 return offset + layer * rtex->layer_size[level]; 82 } 83} 84 85static unsigned r600_get_block_alignment(struct pipe_screen *screen, 86 enum pipe_format format, 87 unsigned array_mode) 88{ 89 struct r600_screen* rscreen = (struct r600_screen *)screen; 90 unsigned pixsize = util_format_get_blocksize(format); 91 int p_align; 92 93 switch(array_mode) { 94 case V_038000_ARRAY_1D_TILED_THIN1: 95 p_align = MAX2(8, 96 ((rscreen->tiling_info->group_bytes / 8 / pixsize))); 97 break; 98 case V_038000_ARRAY_2D_TILED_THIN1: 99 p_align = MAX2(rscreen->tiling_info->num_banks, 100 (((rscreen->tiling_info->group_bytes / 8 / pixsize)) * 101 rscreen->tiling_info->num_banks)) * 8; 102 break; 103 case V_038000_ARRAY_LINEAR_ALIGNED: 104 p_align = MAX2(64, rscreen->tiling_info->group_bytes / pixsize); 105 break; 106 case V_038000_ARRAY_LINEAR_GENERAL: 107 default: 108 p_align = rscreen->tiling_info->group_bytes / pixsize; 109 break; 110 } 111 return p_align; 112} 113 114static unsigned r600_get_height_alignment(struct pipe_screen *screen, 115 unsigned array_mode) 116{ 117 struct r600_screen* rscreen = (struct r600_screen *)screen; 118 int h_align; 119 120 switch (array_mode) { 121 case V_038000_ARRAY_2D_TILED_THIN1: 122 h_align = rscreen->tiling_info->num_channels * 8; 123 break; 124 case V_038000_ARRAY_1D_TILED_THIN1: 125 case V_038000_ARRAY_LINEAR_ALIGNED: 126 h_align = 8; 127 break; 128 case V_038000_ARRAY_LINEAR_GENERAL: 129 default: 130 h_align = 1; 131 break; 132 } 133 return h_align; 134} 135 136static unsigned r600_get_base_alignment(struct pipe_screen *screen, 137 enum pipe_format format, 138 unsigned array_mode) 139{ 140 struct r600_screen* rscreen = (struct r600_screen *)screen; 141 unsigned pixsize = util_format_get_blocksize(format); 142 int p_align = r600_get_block_alignment(screen, format, array_mode); 143 int h_align = r600_get_height_alignment(screen, array_mode); 144 int b_align; 145 146 switch (array_mode) { 147 case V_038000_ARRAY_2D_TILED_THIN1: 148 b_align = MAX2(rscreen->tiling_info->num_banks * rscreen->tiling_info->num_channels * 8 * 8 * pixsize, 149 p_align * pixsize * h_align); 150 break; 151 case V_038000_ARRAY_1D_TILED_THIN1: 152 case V_038000_ARRAY_LINEAR_ALIGNED: 153 case V_038000_ARRAY_LINEAR_GENERAL: 154 default: 155 b_align = rscreen->tiling_info->group_bytes; 156 break; 157 } 158 return b_align; 159} 160 161static unsigned mip_minify(unsigned size, unsigned level) 162{ 163 unsigned val; 164 val = u_minify(size, level); 165 if (level > 0) 166 val = util_next_power_of_two(val); 167 return val; 168} 169 170static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, 171 struct r600_resource_texture *rtex, 172 unsigned level) 173{ 174 struct pipe_resource *ptex = &rtex->resource.b.b.b; 175 unsigned nblocksx, block_align, width; 176 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 177 178 if (rtex->pitch_override) 179 return rtex->pitch_override / blocksize; 180 181 width = mip_minify(ptex->width0, level); 182 nblocksx = util_format_get_nblocksx(rtex->real_format, width); 183 184 block_align = r600_get_block_alignment(screen, rtex->real_format, 185 rtex->array_mode[level]); 186 nblocksx = align(nblocksx, block_align); 187 return nblocksx; 188} 189 190static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, 191 struct r600_resource_texture *rtex, 192 unsigned level) 193{ 194 struct pipe_resource *ptex = &rtex->resource.b.b.b; 195 unsigned height, tile_height; 196 197 height = mip_minify(ptex->height0, level); 198 height = util_format_get_nblocksy(rtex->real_format, height); 199 tile_height = r600_get_height_alignment(screen, 200 rtex->array_mode[level]); 201 202 /* XXX Hack around an alignment issue. Less tests fail with this. 203 * 204 * The thing is depth-stencil buffers should be tiled, i.e. 205 * the alignment should be >=8. If I make them tiled, stencil starts 206 * working because it no longer overlaps with the depth buffer 207 * in memory, but texturing like drawpix-stencil breaks. */ 208 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) 209 tile_height = 8; 210 211 height = align(height, tile_height); 212 return height; 213} 214 215static void r600_texture_set_array_mode(struct pipe_screen *screen, 216 struct r600_resource_texture *rtex, 217 unsigned level, unsigned array_mode) 218{ 219 struct pipe_resource *ptex = &rtex->resource.b.b.b; 220 221 switch (array_mode) { 222 case V_0280A0_ARRAY_LINEAR_GENERAL: 223 case V_0280A0_ARRAY_LINEAR_ALIGNED: 224 case V_0280A0_ARRAY_1D_TILED_THIN1: 225 default: 226 rtex->array_mode[level] = array_mode; 227 break; 228 case V_0280A0_ARRAY_2D_TILED_THIN1: 229 { 230 unsigned w, h, tile_height, tile_width; 231 232 tile_height = r600_get_height_alignment(screen, array_mode); 233 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); 234 235 w = mip_minify(ptex->width0, level); 236 h = mip_minify(ptex->height0, level); 237 if (w <= tile_width || h <= tile_height) 238 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; 239 else 240 rtex->array_mode[level] = array_mode; 241 } 242 break; 243 } 244} 245 246static void r600_setup_miptree(struct pipe_screen *screen, 247 struct r600_resource_texture *rtex, 248 unsigned array_mode) 249{ 250 struct pipe_resource *ptex = &rtex->resource.b.b.b; 251 struct radeon *radeon = ((struct r600_screen*)screen)->radeon; 252 enum chip_class chipc = r600_get_family_class(radeon); 253 unsigned size, layer_size, i, offset; 254 unsigned nblocksx, nblocksy; 255 256 for (i = 0, offset = 0; i <= ptex->last_level; i++) { 257 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 258 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); 259 260 r600_texture_set_array_mode(screen, rtex, i, array_mode); 261 262 nblocksx = r600_texture_get_nblocksx(screen, rtex, i); 263 nblocksy = r600_texture_get_nblocksy(screen, rtex, i); 264 265 layer_size = nblocksx * nblocksy * blocksize; 266 if (ptex->target == PIPE_TEXTURE_CUBE) { 267 if (chipc >= R700) 268 size = layer_size * 8; 269 else 270 size = layer_size * 6; 271 } 272 else if (ptex->target == PIPE_TEXTURE_3D) 273 size = layer_size * u_minify(ptex->depth0, i); 274 else 275 size = layer_size * ptex->array_size; 276 277 /* align base image and start of miptree */ 278 if ((i == 0) || (i == 1)) 279 offset = align(offset, base_align); 280 rtex->offset[i] = offset; 281 rtex->layer_size[i] = layer_size; 282 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ 283 rtex->pitch_in_bytes[i] = nblocksx * blocksize; 284 285 offset += size; 286 } 287 rtex->size = offset; 288} 289 290/* Figure out whether u_blitter will fallback to a transfer operation. 291 * If so, don't use a staging resource. 292 */ 293static boolean permit_hardware_blit(struct pipe_screen *screen, 294 const struct pipe_resource *res) 295{ 296 unsigned bind; 297 298 if (util_format_is_depth_or_stencil(res->format)) 299 bind = PIPE_BIND_DEPTH_STENCIL; 300 else 301 bind = PIPE_BIND_RENDER_TARGET; 302 303 /* hackaround for S3TC */ 304 if (util_format_is_compressed(res->format)) 305 return TRUE; 306 307 if (!screen->is_format_supported(screen, 308 res->format, 309 res->target, 310 res->nr_samples, 311 bind)) 312 return FALSE; 313 314 if (!screen->is_format_supported(screen, 315 res->format, 316 res->target, 317 res->nr_samples, 318 PIPE_BIND_SAMPLER_VIEW)) 319 return FALSE; 320 321 switch (res->usage) { 322 case PIPE_USAGE_STREAM: 323 case PIPE_USAGE_STAGING: 324 return FALSE; 325 326 default: 327 return TRUE; 328 } 329} 330 331static boolean r600_texture_get_handle(struct pipe_screen* screen, 332 struct pipe_resource *ptex, 333 struct winsys_handle *whandle) 334{ 335 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 336 struct r600_resource *resource = &rtex->resource; 337 struct radeon *radeon = ((struct r600_screen*)screen)->radeon; 338 339 return r600_bo_get_winsys_handle(radeon, resource->bo, 340 rtex->pitch_in_bytes[0], whandle); 341} 342 343static void r600_texture_destroy(struct pipe_screen *screen, 344 struct pipe_resource *ptex) 345{ 346 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 347 struct r600_resource *resource = &rtex->resource; 348 349 if (rtex->flushed_depth_texture) 350 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 351 352 if (resource->bo) { 353 r600_bo_reference(&resource->bo, NULL); 354 } 355 FREE(rtex); 356} 357 358static const struct u_resource_vtbl r600_texture_vtbl = 359{ 360 r600_texture_get_handle, /* get_handle */ 361 r600_texture_destroy, /* resource_destroy */ 362 r600_texture_get_transfer, /* get_transfer */ 363 r600_texture_transfer_destroy, /* transfer_destroy */ 364 r600_texture_transfer_map, /* transfer_map */ 365 u_default_transfer_flush_region,/* transfer_flush_region */ 366 r600_texture_transfer_unmap, /* transfer_unmap */ 367 u_default_transfer_inline_write /* transfer_inline_write */ 368}; 369 370static struct r600_resource_texture * 371r600_texture_create_object(struct pipe_screen *screen, 372 const struct pipe_resource *base, 373 unsigned array_mode, 374 unsigned pitch_in_bytes_override, 375 unsigned max_buffer_size, 376 struct r600_bo *bo, 377 boolean alloc_bo) 378{ 379 struct r600_resource_texture *rtex; 380 struct r600_resource *resource; 381 struct radeon *radeon = ((struct r600_screen*)screen)->radeon; 382 383 rtex = CALLOC_STRUCT(r600_resource_texture); 384 if (rtex == NULL) 385 return NULL; 386 387 resource = &rtex->resource; 388 resource->b.b.b = *base; 389 resource->b.b.vtbl = &r600_texture_vtbl; 390 pipe_reference_init(&resource->b.b.b.reference, 1); 391 resource->b.b.b.screen = screen; 392 resource->bo = bo; 393 rtex->pitch_override = pitch_in_bytes_override; 394 rtex->real_format = base->format; 395 396 /* We must split depth and stencil into two separate buffers on Evergreen. */ 397 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) && 398 r600_get_family_class(((struct r600_screen*)screen)->radeon) >= EVERGREEN && 399 util_format_is_depth_and_stencil(base->format)) { 400 struct pipe_resource stencil; 401 unsigned stencil_pitch_override = 0; 402 403 switch (base->format) { 404 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 405 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; 406 break; 407 case PIPE_FORMAT_S8_USCALED_Z24_UNORM: 408 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; 409 break; 410 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED: 411 rtex->real_format = PIPE_FORMAT_Z32_FLOAT; 412 break; 413 default: 414 assert(0); 415 FREE(rtex); 416 return NULL; 417 } 418 419 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ 420 if (pitch_in_bytes_override) { 421 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_USCALED || 422 base->format == PIPE_FORMAT_S8_USCALED_Z24_UNORM); 423 stencil_pitch_override = pitch_in_bytes_override / 4; 424 } 425 426 /* Allocate the stencil buffer. */ 427 stencil = *base; 428 stencil.format = PIPE_FORMAT_S8_USCALED; 429 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, 430 stencil_pitch_override, 431 max_buffer_size, NULL, FALSE); 432 if (!rtex->stencil) { 433 FREE(rtex); 434 return NULL; 435 } 436 /* Proceed in creating the depth buffer. */ 437 } 438 439 /* only mark depth textures the HW can hit as depth textures */ 440 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base)) 441 rtex->depth = 1; 442 443 r600_setup_miptree(screen, rtex, array_mode); 444 445 /* If we initialized separate stencil for Evergreen. place it after depth. */ 446 if (rtex->stencil) { 447 unsigned stencil_align, stencil_offset; 448 449 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); 450 stencil_offset = align(rtex->size, stencil_align); 451 452 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++) 453 rtex->stencil->offset[i] += stencil_offset; 454 455 rtex->size = stencil_offset + rtex->stencil->size; 456 } 457 458 resource->size = rtex->size; 459 460 /* Now create the backing buffer. */ 461 if (!resource->bo && alloc_bo) { 462 struct pipe_resource *ptex = &rtex->resource.b.b.b; 463 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); 464 465 resource->bo = r600_bo(radeon, rtex->size, base_align, base->bind, base->usage); 466 if (!resource->bo) { 467 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); 468 FREE(rtex); 469 return NULL; 470 } 471 } 472 473 if (rtex->stencil) 474 rtex->stencil->resource.bo = rtex->resource.bo; 475 return rtex; 476} 477 478DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE); 479 480struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 481 const struct pipe_resource *templ) 482{ 483 struct radeon *radeon = ((struct r600_screen*)screen)->radeon; 484 unsigned array_mode = 0; 485 486 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && 487 !(templ->bind & PIPE_BIND_SCANOUT)) { 488 if (util_format_is_compressed(templ->format)) { 489 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 490 } 491 else if (debug_get_option_tiling_enabled() && 492 r600_get_minor_version(radeon) >= 9 && 493 permit_hardware_blit(screen, templ)) { 494 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 495 } 496 } 497 498 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 499 0, 0, NULL, TRUE); 500} 501 502static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 503 struct pipe_resource *texture, 504 const struct pipe_surface *surf_tmpl) 505{ 506 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 507 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 508 unsigned level = surf_tmpl->u.tex.level; 509 510 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 511 if (surface == NULL) 512 return NULL; 513 /* XXX no offset */ 514/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ 515 pipe_reference_init(&surface->base.reference, 1); 516 pipe_resource_reference(&surface->base.texture, texture); 517 surface->base.context = pipe; 518 surface->base.format = surf_tmpl->format; 519 surface->base.width = mip_minify(texture->width0, level); 520 surface->base.height = mip_minify(texture->height0, level); 521 surface->base.usage = surf_tmpl->usage; 522 surface->base.texture = texture; 523 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 524 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 525 surface->base.u.tex.level = level; 526 527 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, 528 rtex, level); 529 return &surface->base; 530} 531 532static void r600_surface_destroy(struct pipe_context *pipe, 533 struct pipe_surface *surface) 534{ 535 pipe_resource_reference(&surface->texture, NULL); 536 FREE(surface); 537} 538 539 540struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 541 const struct pipe_resource *templ, 542 struct winsys_handle *whandle) 543{ 544 struct radeon *rw = ((struct r600_screen*)screen)->radeon; 545 struct r600_bo *bo = NULL; 546 unsigned stride = 0; 547 unsigned array_mode = 0; 548 549 /* Support only 2D textures without mipmaps */ 550 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 551 templ->depth0 != 1 || templ->last_level != 0) 552 return NULL; 553 554 bo = r600_bo_handle(rw, whandle, &stride, &array_mode); 555 if (bo == NULL) { 556 return NULL; 557 } 558 559 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 560 stride, 0, bo, FALSE); 561} 562 563int r600_texture_depth_flush(struct pipe_context *ctx, 564 struct pipe_resource *texture, boolean just_create) 565{ 566 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 567 struct pipe_resource resource; 568 569 if (rtex->flushed_depth_texture) 570 goto out; 571 572 resource.target = PIPE_TEXTURE_2D; 573 resource.format = texture->format; 574 resource.width0 = texture->width0; 575 resource.height0 = texture->height0; 576 resource.depth0 = 1; 577 resource.array_size = 1; 578 resource.last_level = texture->last_level; 579 resource.nr_samples = 0; 580 resource.usage = PIPE_USAGE_DYNAMIC; 581 resource.bind = 0; 582 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 583 584 resource.bind |= PIPE_BIND_DEPTH_STENCIL; 585 586 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 587 if (rtex->flushed_depth_texture == NULL) { 588 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 589 return -ENOMEM; 590 } 591 592 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE; 593out: 594 if (just_create) 595 return 0; 596 597 /* XXX: only do this if the depth texture has actually changed: 598 */ 599 r600_blit_uncompress_depth(ctx, rtex); 600 return 0; 601} 602 603/* Needs adjustment for pixelformat: 604 */ 605static INLINE unsigned u_box_volume( const struct pipe_box *box ) 606{ 607 return box->width * box->depth * box->height; 608}; 609 610struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 611 struct pipe_resource *texture, 612 unsigned level, 613 unsigned usage, 614 const struct pipe_box *box) 615{ 616 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 617 struct pipe_resource resource; 618 struct r600_transfer *trans; 619 int r; 620 boolean use_staging_texture = FALSE; 621 622 /* We cannot map a tiled texture directly because the data is 623 * in a different order, therefore we do detiling using a blit. 624 * 625 * Also, use a temporary in GTT memory for read transfers, as 626 * the CPU is much happier reading out of cached system memory 627 * than uncached VRAM. 628 */ 629 if (R600_TEX_IS_TILED(rtex, level)) 630 use_staging_texture = TRUE; 631 632 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 633 use_staging_texture = TRUE; 634 635 /* XXX: Use a staging texture for uploads if the underlying BO 636 * is busy. No interface for checking that currently? so do 637 * it eagerly whenever the transfer doesn't require a readback 638 * and might block. 639 */ 640 if ((usage & PIPE_TRANSFER_WRITE) && 641 !(usage & (PIPE_TRANSFER_READ | 642 PIPE_TRANSFER_DONTBLOCK | 643 PIPE_TRANSFER_UNSYNCHRONIZED))) 644 use_staging_texture = TRUE; 645 646 if (!permit_hardware_blit(ctx->screen, texture) || 647 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) 648 use_staging_texture = FALSE; 649 650 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) 651 return NULL; 652 653 trans = CALLOC_STRUCT(r600_transfer); 654 if (trans == NULL) 655 return NULL; 656 pipe_resource_reference(&trans->transfer.resource, texture); 657 trans->transfer.level = level; 658 trans->transfer.usage = usage; 659 trans->transfer.box = *box; 660 if (rtex->depth) { 661 /* XXX: only readback the rectangle which is being mapped? 662 */ 663 /* XXX: when discard is true, no need to read back from depth texture 664 */ 665 r = r600_texture_depth_flush(ctx, texture, FALSE); 666 if (r < 0) { 667 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 668 pipe_resource_reference(&trans->transfer.resource, NULL); 669 FREE(trans); 670 return NULL; 671 } 672 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level]; 673 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); 674 return &trans->transfer; 675 } else if (use_staging_texture) { 676 resource.target = PIPE_TEXTURE_2D; 677 resource.format = texture->format; 678 resource.width0 = box->width; 679 resource.height0 = box->height; 680 resource.depth0 = 1; 681 resource.array_size = 1; 682 resource.last_level = 0; 683 resource.nr_samples = 0; 684 resource.usage = PIPE_USAGE_STAGING; 685 resource.bind = 0; 686 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 687 /* For texture reading, the temporary (detiled) texture is used as 688 * a render target when blitting from a tiled texture. */ 689 if (usage & PIPE_TRANSFER_READ) { 690 resource.bind |= PIPE_BIND_RENDER_TARGET; 691 } 692 /* For texture writing, the temporary texture is used as a sampler 693 * when blitting into a tiled texture. */ 694 if (usage & PIPE_TRANSFER_WRITE) { 695 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 696 } 697 /* Create the temporary texture. */ 698 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource); 699 if (trans->staging_texture == NULL) { 700 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 701 pipe_resource_reference(&trans->transfer.resource, NULL); 702 FREE(trans); 703 return NULL; 704 } 705 706 trans->transfer.stride = 707 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0]; 708 if (usage & PIPE_TRANSFER_READ) { 709 r600_copy_to_staging_texture(ctx, trans); 710 /* Always referenced in the blit. */ 711 r600_flush(ctx, NULL, 0); 712 } 713 return &trans->transfer; 714 } 715 trans->transfer.stride = rtex->pitch_in_bytes[level]; 716 trans->transfer.layer_stride = rtex->layer_size[level]; 717 trans->offset = r600_texture_get_offset(rtex, level, box->z); 718 return &trans->transfer; 719} 720 721void r600_texture_transfer_destroy(struct pipe_context *ctx, 722 struct pipe_transfer *transfer) 723{ 724 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 725 struct pipe_resource *texture = transfer->resource; 726 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 727 728 if (rtransfer->staging_texture) { 729 if (transfer->usage & PIPE_TRANSFER_WRITE) { 730 r600_copy_from_staging_texture(ctx, rtransfer); 731 } 732 pipe_resource_reference(&rtransfer->staging_texture, NULL); 733 } 734 735 if (rtex->depth && !rtex->is_flushing_texture) { 736 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) 737 r600_blit_push_depth(ctx, rtex); 738 } 739 740 pipe_resource_reference(&transfer->resource, NULL); 741 FREE(transfer); 742} 743 744void* r600_texture_transfer_map(struct pipe_context *ctx, 745 struct pipe_transfer* transfer) 746{ 747 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 748 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 749 struct r600_bo *bo; 750 enum pipe_format format = transfer->resource->format; 751 struct radeon *radeon = rctx->screen->radeon; 752 unsigned offset = 0; 753 char *map; 754 755 if (rtransfer->staging_texture) { 756 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo; 757 } else { 758 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 759 760 if (rtex->flushed_depth_texture) 761 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo; 762 else 763 bo = ((struct r600_resource *)transfer->resource)->bo; 764 765 offset = rtransfer->offset + 766 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 767 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 768 } 769 770 if (!(map = r600_bo_map(radeon, bo, rctx->ctx.cs, transfer->usage))) { 771 return NULL; 772 } 773 774 return map + offset; 775} 776 777void r600_texture_transfer_unmap(struct pipe_context *ctx, 778 struct pipe_transfer* transfer) 779{ 780 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 781 struct radeon *radeon = ((struct r600_screen*)ctx->screen)->radeon; 782 struct r600_bo *bo; 783 784 if (rtransfer->staging_texture) { 785 bo = ((struct r600_resource *)rtransfer->staging_texture)->bo; 786 } else { 787 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 788 789 if (rtex->flushed_depth_texture) { 790 bo = ((struct r600_resource *)rtex->flushed_depth_texture)->bo; 791 } else { 792 bo = ((struct r600_resource *)transfer->resource)->bo; 793 } 794 } 795 r600_bo_unmap(radeon, bo); 796} 797 798void r600_init_surface_functions(struct r600_pipe_context *r600) 799{ 800 r600->context.create_surface = r600_create_surface; 801 r600->context.surface_destroy = r600_surface_destroy; 802} 803 804static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 805 const unsigned char *swizzle_view) 806{ 807 unsigned i; 808 unsigned char swizzle[4]; 809 unsigned result = 0; 810 const uint32_t swizzle_shift[4] = { 811 16, 19, 22, 25, 812 }; 813 const uint32_t swizzle_bit[4] = { 814 0, 1, 2, 3, 815 }; 816 817 if (swizzle_view) { 818 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 819 } else { 820 memcpy(swizzle, swizzle_format, 4); 821 } 822 823 /* Get swizzle. */ 824 for (i = 0; i < 4; i++) { 825 switch (swizzle[i]) { 826 case UTIL_FORMAT_SWIZZLE_Y: 827 result |= swizzle_bit[1] << swizzle_shift[i]; 828 break; 829 case UTIL_FORMAT_SWIZZLE_Z: 830 result |= swizzle_bit[2] << swizzle_shift[i]; 831 break; 832 case UTIL_FORMAT_SWIZZLE_W: 833 result |= swizzle_bit[3] << swizzle_shift[i]; 834 break; 835 case UTIL_FORMAT_SWIZZLE_0: 836 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 837 break; 838 case UTIL_FORMAT_SWIZZLE_1: 839 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 840 break; 841 default: /* UTIL_FORMAT_SWIZZLE_X */ 842 result |= swizzle_bit[0] << swizzle_shift[i]; 843 } 844 } 845 return result; 846} 847 848/* texture format translate */ 849uint32_t r600_translate_texformat(struct pipe_screen *screen, 850 enum pipe_format format, 851 const unsigned char *swizzle_view, 852 uint32_t *word4_p, uint32_t *yuv_format_p) 853{ 854 uint32_t result = 0, word4 = 0, yuv_format = 0; 855 const struct util_format_description *desc; 856 boolean uniform = TRUE; 857 static int r600_enable_s3tc = -1; 858 859 int i; 860 const uint32_t sign_bit[4] = { 861 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 862 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 863 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 864 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 865 }; 866 desc = util_format_description(format); 867 868 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 869 870 /* Colorspace (return non-RGB formats directly). */ 871 switch (desc->colorspace) { 872 /* Depth stencil formats */ 873 case UTIL_FORMAT_COLORSPACE_ZS: 874 switch (format) { 875 case PIPE_FORMAT_Z16_UNORM: 876 result = FMT_16; 877 goto out_word4; 878 case PIPE_FORMAT_X24S8_USCALED: 879 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 880 case PIPE_FORMAT_Z24X8_UNORM: 881 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 882 result = FMT_8_24; 883 goto out_word4; 884 case PIPE_FORMAT_S8X24_USCALED: 885 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 886 case PIPE_FORMAT_X8Z24_UNORM: 887 case PIPE_FORMAT_S8_USCALED_Z24_UNORM: 888 result = FMT_24_8; 889 goto out_word4; 890 case PIPE_FORMAT_S8_USCALED: 891 result = FMT_8; 892 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 893 goto out_word4; 894 case PIPE_FORMAT_Z32_FLOAT: 895 result = FMT_32_FLOAT; 896 goto out_word4; 897 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED: 898 result = FMT_X24_8_32_FLOAT; 899 goto out_word4; 900 default: 901 goto out_unknown; 902 } 903 904 case UTIL_FORMAT_COLORSPACE_YUV: 905 yuv_format |= (1 << 30); 906 switch (format) { 907 case PIPE_FORMAT_UYVY: 908 case PIPE_FORMAT_YUYV: 909 default: 910 break; 911 } 912 goto out_unknown; /* TODO */ 913 914 case UTIL_FORMAT_COLORSPACE_SRGB: 915 word4 |= S_038010_FORCE_DEGAMMA(1); 916 break; 917 918 default: 919 break; 920 } 921 922 if (r600_enable_s3tc == -1) { 923 struct r600_screen *rscreen = (struct r600_screen *)screen; 924 if (r600_get_minor_version(rscreen->radeon) >= 9) 925 r600_enable_s3tc = 1; 926 else 927 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 928 } 929 930 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 931 if (!r600_enable_s3tc) 932 goto out_unknown; 933 934 switch (format) { 935 case PIPE_FORMAT_RGTC1_SNORM: 936 case PIPE_FORMAT_LATC1_SNORM: 937 word4 |= sign_bit[0]; 938 case PIPE_FORMAT_RGTC1_UNORM: 939 case PIPE_FORMAT_LATC1_UNORM: 940 result = FMT_BC4; 941 goto out_word4; 942 case PIPE_FORMAT_RGTC2_SNORM: 943 case PIPE_FORMAT_LATC2_SNORM: 944 word4 |= sign_bit[0] | sign_bit[1]; 945 case PIPE_FORMAT_RGTC2_UNORM: 946 case PIPE_FORMAT_LATC2_UNORM: 947 result = FMT_BC5; 948 goto out_word4; 949 default: 950 goto out_unknown; 951 } 952 } 953 954 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 955 956 if (!r600_enable_s3tc) 957 goto out_unknown; 958 959 if (!util_format_s3tc_enabled) { 960 goto out_unknown; 961 } 962 963 switch (format) { 964 case PIPE_FORMAT_DXT1_RGB: 965 case PIPE_FORMAT_DXT1_RGBA: 966 case PIPE_FORMAT_DXT1_SRGB: 967 case PIPE_FORMAT_DXT1_SRGBA: 968 result = FMT_BC1; 969 goto out_word4; 970 case PIPE_FORMAT_DXT3_RGBA: 971 case PIPE_FORMAT_DXT3_SRGBA: 972 result = FMT_BC2; 973 goto out_word4; 974 case PIPE_FORMAT_DXT5_RGBA: 975 case PIPE_FORMAT_DXT5_SRGBA: 976 result = FMT_BC3; 977 goto out_word4; 978 default: 979 goto out_unknown; 980 } 981 } 982 983 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 984 result = FMT_5_9_9_9_SHAREDEXP; 985 goto out_word4; 986 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 987 result = FMT_10_11_11_FLOAT; 988 goto out_word4; 989 } 990 991 992 for (i = 0; i < desc->nr_channels; i++) { 993 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 994 word4 |= sign_bit[i]; 995 } 996 } 997 998 /* R8G8Bx_SNORM - TODO CxV8U8 */ 999 1000 /* See whether the components are of the same size. */ 1001 for (i = 1; i < desc->nr_channels; i++) { 1002 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1003 } 1004 1005 /* Non-uniform formats. */ 1006 if (!uniform) { 1007 switch(desc->nr_channels) { 1008 case 3: 1009 if (desc->channel[0].size == 5 && 1010 desc->channel[1].size == 6 && 1011 desc->channel[2].size == 5) { 1012 result = FMT_5_6_5; 1013 goto out_word4; 1014 } 1015 goto out_unknown; 1016 case 4: 1017 if (desc->channel[0].size == 5 && 1018 desc->channel[1].size == 5 && 1019 desc->channel[2].size == 5 && 1020 desc->channel[3].size == 1) { 1021 result = FMT_1_5_5_5; 1022 goto out_word4; 1023 } 1024 if (desc->channel[0].size == 10 && 1025 desc->channel[1].size == 10 && 1026 desc->channel[2].size == 10 && 1027 desc->channel[3].size == 2) { 1028 result = FMT_2_10_10_10; 1029 goto out_word4; 1030 } 1031 goto out_unknown; 1032 } 1033 goto out_unknown; 1034 } 1035 1036 /* Find the first non-VOID channel. */ 1037 for (i = 0; i < 4; i++) { 1038 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1039 break; 1040 } 1041 } 1042 1043 if (i == 4) 1044 goto out_unknown; 1045 1046 /* uniform formats */ 1047 switch (desc->channel[i].type) { 1048 case UTIL_FORMAT_TYPE_UNSIGNED: 1049 case UTIL_FORMAT_TYPE_SIGNED: 1050 if (!desc->channel[i].normalized && 1051 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 1052 goto out_unknown; 1053 } 1054 1055 switch (desc->channel[i].size) { 1056 case 4: 1057 switch (desc->nr_channels) { 1058 case 2: 1059 result = FMT_4_4; 1060 goto out_word4; 1061 case 4: 1062 result = FMT_4_4_4_4; 1063 goto out_word4; 1064 } 1065 goto out_unknown; 1066 case 8: 1067 switch (desc->nr_channels) { 1068 case 1: 1069 result = FMT_8; 1070 goto out_word4; 1071 case 2: 1072 result = FMT_8_8; 1073 goto out_word4; 1074 case 4: 1075 result = FMT_8_8_8_8; 1076 goto out_word4; 1077 } 1078 goto out_unknown; 1079 case 16: 1080 switch (desc->nr_channels) { 1081 case 1: 1082 result = FMT_16; 1083 goto out_word4; 1084 case 2: 1085 result = FMT_16_16; 1086 goto out_word4; 1087 case 4: 1088 result = FMT_16_16_16_16; 1089 goto out_word4; 1090 } 1091 goto out_unknown; 1092 case 32: 1093 switch (desc->nr_channels) { 1094 case 1: 1095 result = FMT_32; 1096 goto out_word4; 1097 case 2: 1098 result = FMT_32_32; 1099 goto out_word4; 1100 case 4: 1101 result = FMT_32_32_32_32; 1102 goto out_word4; 1103 } 1104 } 1105 goto out_unknown; 1106 1107 case UTIL_FORMAT_TYPE_FLOAT: 1108 switch (desc->channel[i].size) { 1109 case 16: 1110 switch (desc->nr_channels) { 1111 case 1: 1112 result = FMT_16_FLOAT; 1113 goto out_word4; 1114 case 2: 1115 result = FMT_16_16_FLOAT; 1116 goto out_word4; 1117 case 4: 1118 result = FMT_16_16_16_16_FLOAT; 1119 goto out_word4; 1120 } 1121 goto out_unknown; 1122 case 32: 1123 switch (desc->nr_channels) { 1124 case 1: 1125 result = FMT_32_FLOAT; 1126 goto out_word4; 1127 case 2: 1128 result = FMT_32_32_FLOAT; 1129 goto out_word4; 1130 case 4: 1131 result = FMT_32_32_32_32_FLOAT; 1132 goto out_word4; 1133 } 1134 } 1135 goto out_unknown; 1136 } 1137 1138out_word4: 1139 if (word4_p) 1140 *word4_p = word4; 1141 if (yuv_format_p) 1142 *yuv_format_p = yuv_format; 1143 return result; 1144out_unknown: 1145 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1146 return ~0; 1147} 1148