r600_texture.c revision 897af1d499ed91ed3629432424eb1ac62bff2c5f
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include <errno.h> 28#include "pipe/p_screen.h" 29#include "util/u_format.h" 30#include "util/u_format_s3tc.h" 31#include "util/u_math.h" 32#include "util/u_inlines.h" 33#include "util/u_memory.h" 34#include "pipebuffer/pb_buffer.h" 35#include "r600_pipe.h" 36#include "r600_resource.h" 37#include "r600d.h" 38#include "r600_formats.h" 39 40/* Copy from a full GPU texture to a transfer's staging one. */ 41static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 42{ 43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 44 struct pipe_resource *texture = transfer->resource; 45 46 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b.b, 47 0, 0, 0, 0, texture, transfer->level, 48 &transfer->box); 49} 50 51 52/* Copy from a transfer's staging texture to a full GPU one. */ 53static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 54{ 55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 56 struct pipe_resource *texture = transfer->resource; 57 struct pipe_box sbox; 58 59 sbox.x = sbox.y = sbox.z = 0; 60 sbox.width = transfer->box.width; 61 sbox.height = transfer->box.height; 62 /* XXX that might be wrong */ 63 sbox.depth = 1; 64 ctx->resource_copy_region(ctx, texture, transfer->level, 65 transfer->box.x, transfer->box.y, transfer->box.z, 66 &rtransfer->staging->b.b.b, 67 0, &sbox); 68} 69 70unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 71 unsigned level, unsigned layer) 72{ 73 unsigned offset = rtex->offset[level]; 74 75 switch (rtex->resource.b.b.b.target) { 76 case PIPE_TEXTURE_3D: 77 case PIPE_TEXTURE_CUBE: 78 default: 79 return offset + layer * rtex->layer_size[level]; 80 } 81} 82 83static unsigned r600_get_block_alignment(struct pipe_screen *screen, 84 enum pipe_format format, 85 unsigned array_mode) 86{ 87 struct r600_screen* rscreen = (struct r600_screen *)screen; 88 unsigned pixsize = util_format_get_blocksize(format); 89 int p_align; 90 91 switch(array_mode) { 92 case V_038000_ARRAY_1D_TILED_THIN1: 93 p_align = MAX2(8, 94 ((rscreen->tiling_info.group_bytes / 8 / pixsize))); 95 break; 96 case V_038000_ARRAY_2D_TILED_THIN1: 97 p_align = MAX2(rscreen->tiling_info.num_banks, 98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) * 99 rscreen->tiling_info.num_banks)) * 8; 100 break; 101 case V_038000_ARRAY_LINEAR_ALIGNED: 102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize); 103 break; 104 case V_038000_ARRAY_LINEAR_GENERAL: 105 default: 106 p_align = rscreen->tiling_info.group_bytes / pixsize; 107 break; 108 } 109 return p_align; 110} 111 112static unsigned r600_get_height_alignment(struct pipe_screen *screen, 113 unsigned array_mode) 114{ 115 struct r600_screen* rscreen = (struct r600_screen *)screen; 116 int h_align; 117 118 switch (array_mode) { 119 case V_038000_ARRAY_2D_TILED_THIN1: 120 h_align = rscreen->tiling_info.num_channels * 8; 121 break; 122 case V_038000_ARRAY_1D_TILED_THIN1: 123 case V_038000_ARRAY_LINEAR_ALIGNED: 124 h_align = 8; 125 break; 126 case V_038000_ARRAY_LINEAR_GENERAL: 127 default: 128 h_align = 1; 129 break; 130 } 131 return h_align; 132} 133 134static unsigned r600_get_base_alignment(struct pipe_screen *screen, 135 enum pipe_format format, 136 unsigned array_mode) 137{ 138 struct r600_screen* rscreen = (struct r600_screen *)screen; 139 unsigned pixsize = util_format_get_blocksize(format); 140 int p_align = r600_get_block_alignment(screen, format, array_mode); 141 int h_align = r600_get_height_alignment(screen, array_mode); 142 int b_align; 143 144 switch (array_mode) { 145 case V_038000_ARRAY_2D_TILED_THIN1: 146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize, 147 p_align * pixsize * h_align); 148 break; 149 case V_038000_ARRAY_1D_TILED_THIN1: 150 case V_038000_ARRAY_LINEAR_ALIGNED: 151 case V_038000_ARRAY_LINEAR_GENERAL: 152 default: 153 b_align = rscreen->tiling_info.group_bytes; 154 break; 155 } 156 return b_align; 157} 158 159static unsigned mip_minify(unsigned size, unsigned level) 160{ 161 unsigned val; 162 val = u_minify(size, level); 163 if (level > 0) 164 val = util_next_power_of_two(val); 165 return val; 166} 167 168static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, 169 struct r600_resource_texture *rtex, 170 unsigned level) 171{ 172 struct pipe_resource *ptex = &rtex->resource.b.b.b; 173 unsigned nblocksx, block_align, width; 174 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 175 176 if (rtex->pitch_override) 177 return rtex->pitch_override / blocksize; 178 179 width = mip_minify(ptex->width0, level); 180 nblocksx = util_format_get_nblocksx(rtex->real_format, width); 181 182 block_align = r600_get_block_alignment(screen, rtex->real_format, 183 rtex->array_mode[level]); 184 nblocksx = align(nblocksx, block_align); 185 return nblocksx; 186} 187 188static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, 189 struct r600_resource_texture *rtex, 190 unsigned level) 191{ 192 struct pipe_resource *ptex = &rtex->resource.b.b.b; 193 unsigned height, tile_height; 194 195 height = mip_minify(ptex->height0, level); 196 height = util_format_get_nblocksy(rtex->real_format, height); 197 tile_height = r600_get_height_alignment(screen, 198 rtex->array_mode[level]); 199 200 /* XXX Hack around an alignment issue. Less tests fail with this. 201 * 202 * The thing is depth-stencil buffers should be tiled, i.e. 203 * the alignment should be >=8. If I make them tiled, stencil starts 204 * working because it no longer overlaps with the depth buffer 205 * in memory, but texturing like drawpix-stencil breaks. */ 206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) 207 tile_height = 8; 208 209 height = align(height, tile_height); 210 return height; 211} 212 213static void r600_texture_set_array_mode(struct pipe_screen *screen, 214 struct r600_resource_texture *rtex, 215 unsigned level, unsigned array_mode) 216{ 217 struct pipe_resource *ptex = &rtex->resource.b.b.b; 218 219 switch (array_mode) { 220 case V_0280A0_ARRAY_LINEAR_GENERAL: 221 case V_0280A0_ARRAY_LINEAR_ALIGNED: 222 case V_0280A0_ARRAY_1D_TILED_THIN1: 223 default: 224 rtex->array_mode[level] = array_mode; 225 break; 226 case V_0280A0_ARRAY_2D_TILED_THIN1: 227 { 228 unsigned w, h, tile_height, tile_width; 229 230 tile_height = r600_get_height_alignment(screen, array_mode); 231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); 232 233 w = mip_minify(ptex->width0, level); 234 h = mip_minify(ptex->height0, level); 235 if (w <= tile_width || h <= tile_height) 236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; 237 else 238 rtex->array_mode[level] = array_mode; 239 } 240 break; 241 } 242} 243 244static int r600_init_surface(struct radeon_surface *surface, 245 const struct pipe_resource *ptex, 246 unsigned array_mode) 247{ 248 surface->npix_x = ptex->width0; 249 surface->npix_y = ptex->height0; 250 surface->npix_z = ptex->depth0; 251 surface->blk_w = util_format_get_blockwidth(ptex->format); 252 surface->blk_h = util_format_get_blockheight(ptex->format); 253 surface->blk_d = 1; 254 surface->array_size = 1; 255 surface->last_level = ptex->last_level; 256 surface->bpe = util_format_get_blocksize(ptex->format); 257 /* align byte per element on dword */ 258 if (surface->bpe == 3) { 259 surface->bpe = 4; 260 } 261 surface->nsamples = 1; 262 surface->flags = 0; 263 switch (array_mode) { 264 case V_038000_ARRAY_1D_TILED_THIN1: 265 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 266 break; 267 case V_038000_ARRAY_2D_TILED_THIN1: 268 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 269 break; 270 case V_038000_ARRAY_LINEAR_ALIGNED: 271 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 272 break; 273 case V_038000_ARRAY_LINEAR_GENERAL: 274 default: 275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 276 break; 277 } 278 switch (ptex->target) { 279 case PIPE_TEXTURE_1D: 280 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 281 break; 282 case PIPE_TEXTURE_RECT: 283 case PIPE_TEXTURE_2D: 284 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 285 break; 286 case PIPE_TEXTURE_3D: 287 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 288 break; 289 case PIPE_TEXTURE_1D_ARRAY: 290 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 291 surface->array_size = ptex->array_size; 292 break; 293 case PIPE_TEXTURE_2D_ARRAY: 294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 295 surface->array_size = ptex->array_size; 296 break; 297 case PIPE_TEXTURE_CUBE: 298 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 299 break; 300 case PIPE_BUFFER: 301 default: 302 return -EINVAL; 303 } 304 if (ptex->bind & PIPE_BIND_SCANOUT) { 305 surface->flags |= RADEON_SURF_SCANOUT; 306 } 307 if (util_format_is_depth_and_stencil(ptex->format)) { 308 surface->flags |= RADEON_SURF_ZBUFFER; 309 surface->flags |= RADEON_SURF_SBUFFER; 310 } 311 312 return 0; 313} 314 315static int r600_setup_surface(struct pipe_screen *screen, 316 struct r600_resource_texture *rtex, 317 unsigned array_mode, 318 unsigned pitch_in_bytes_override) 319{ 320 struct pipe_resource *ptex = &rtex->resource.b.b.b; 321 struct r600_screen *rscreen = (struct r600_screen*)screen; 322 unsigned i; 323 int r; 324 325 if (util_format_is_depth_or_stencil(rtex->real_format)) { 326 rtex->surface.flags |= RADEON_SURF_ZBUFFER; 327 rtex->surface.flags |= RADEON_SURF_SBUFFER; 328 } 329 330 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 331 if (r) { 332 return r; 333 } 334 rtex->size = rtex->surface.bo_size; 335 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 336 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 337 * for those 338 */ 339 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 340 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 341 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 342 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 343 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 344 } 345 } 346 for (i = 0; i <= ptex->last_level; i++) { 347 rtex->offset[i] = rtex->surface.level[i].offset; 348 rtex->layer_size[i] = rtex->surface.level[i].slice_size; 349 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes; 350 switch (rtex->surface.level[i].mode) { 351 case RADEON_SURF_MODE_LINEAR_ALIGNED: 352 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 353 break; 354 case RADEON_SURF_MODE_1D: 355 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 356 break; 357 case RADEON_SURF_MODE_2D: 358 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 359 break; 360 default: 361 case RADEON_SURF_MODE_LINEAR: 362 rtex->array_mode[i] = 0; 363 break; 364 } 365 } 366 return 0; 367} 368 369static void r600_setup_miptree(struct pipe_screen *screen, 370 struct r600_resource_texture *rtex, 371 unsigned array_mode) 372{ 373 struct pipe_resource *ptex = &rtex->resource.b.b.b; 374 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class; 375 unsigned size, layer_size, i, offset; 376 unsigned nblocksx, nblocksy; 377 378 for (i = 0, offset = 0; i <= ptex->last_level; i++) { 379 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 380 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); 381 382 r600_texture_set_array_mode(screen, rtex, i, array_mode); 383 384 nblocksx = r600_texture_get_nblocksx(screen, rtex, i); 385 nblocksy = r600_texture_get_nblocksy(screen, rtex, i); 386 387 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL) 388 layer_size = align(nblocksx, 64) * nblocksy * blocksize; 389 else 390 layer_size = nblocksx * nblocksy * blocksize; 391 392 if (ptex->target == PIPE_TEXTURE_CUBE) { 393 if (chipc >= R700) 394 size = layer_size * 8; 395 else 396 size = layer_size * 6; 397 } 398 else if (ptex->target == PIPE_TEXTURE_3D) 399 size = layer_size * u_minify(ptex->depth0, i); 400 else 401 size = layer_size * ptex->array_size; 402 403 /* align base image and start of miptree */ 404 if ((i == 0) || (i == 1)) 405 offset = align(offset, base_align); 406 rtex->offset[i] = offset; 407 rtex->layer_size[i] = layer_size; 408 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ 409 rtex->pitch_in_bytes[i] = nblocksx * blocksize; 410 411 offset += size; 412 } 413 rtex->size = offset; 414} 415 416/* Figure out whether u_blitter will fallback to a transfer operation. 417 * If so, don't use a staging resource. 418 */ 419static boolean permit_hardware_blit(struct pipe_screen *screen, 420 const struct pipe_resource *res) 421{ 422 unsigned bind; 423 424 if (util_format_is_depth_or_stencil(res->format)) 425 bind = PIPE_BIND_DEPTH_STENCIL; 426 else 427 bind = PIPE_BIND_RENDER_TARGET; 428 429 /* hackaround for S3TC */ 430 if (util_format_is_compressed(res->format)) 431 return TRUE; 432 433 if (!screen->is_format_supported(screen, 434 res->format, 435 res->target, 436 res->nr_samples, 437 bind)) 438 return FALSE; 439 440 if (!screen->is_format_supported(screen, 441 res->format, 442 res->target, 443 res->nr_samples, 444 PIPE_BIND_SAMPLER_VIEW)) 445 return FALSE; 446 447 switch (res->usage) { 448 case PIPE_USAGE_STREAM: 449 case PIPE_USAGE_STAGING: 450 return FALSE; 451 452 default: 453 return TRUE; 454 } 455} 456 457static boolean r600_texture_get_handle(struct pipe_screen* screen, 458 struct pipe_resource *ptex, 459 struct winsys_handle *whandle) 460{ 461 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 462 struct r600_resource *resource = &rtex->resource; 463 struct r600_screen *rscreen = (struct r600_screen*)screen; 464 465 return rscreen->ws->buffer_get_handle(resource->buf, 466 rtex->pitch_in_bytes[0], whandle); 467} 468 469static void r600_texture_destroy(struct pipe_screen *screen, 470 struct pipe_resource *ptex) 471{ 472 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 473 struct r600_resource *resource = &rtex->resource; 474 475 if (rtex->flushed_depth_texture) 476 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 477 478 if (rtex->stencil) 479 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL); 480 481 pb_reference(&resource->buf, NULL); 482 FREE(rtex); 483} 484 485static const struct u_resource_vtbl r600_texture_vtbl = 486{ 487 r600_texture_get_handle, /* get_handle */ 488 r600_texture_destroy, /* resource_destroy */ 489 r600_texture_get_transfer, /* get_transfer */ 490 r600_texture_transfer_destroy, /* transfer_destroy */ 491 r600_texture_transfer_map, /* transfer_map */ 492 u_default_transfer_flush_region,/* transfer_flush_region */ 493 r600_texture_transfer_unmap, /* transfer_unmap */ 494 u_default_transfer_inline_write /* transfer_inline_write */ 495}; 496 497static struct r600_resource_texture * 498r600_texture_create_object(struct pipe_screen *screen, 499 const struct pipe_resource *base, 500 unsigned array_mode, 501 unsigned pitch_in_bytes_override, 502 unsigned max_buffer_size, 503 struct pb_buffer *buf, 504 boolean alloc_bo, 505 struct radeon_surface *surface) 506{ 507 struct r600_resource_texture *rtex; 508 struct r600_resource *resource; 509 struct r600_screen *rscreen = (struct r600_screen*)screen; 510 int r; 511 512 rtex = CALLOC_STRUCT(r600_resource_texture); 513 if (rtex == NULL) 514 return NULL; 515 516 resource = &rtex->resource; 517 resource->b.b.b = *base; 518 resource->b.b.vtbl = &r600_texture_vtbl; 519 pipe_reference_init(&resource->b.b.b.reference, 1); 520 resource->b.b.b.screen = screen; 521 rtex->pitch_override = pitch_in_bytes_override; 522 rtex->real_format = base->format; 523 524 /* We must split depth and stencil into two separate buffers on Evergreen. */ 525 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) && 526 ((struct r600_screen*)screen)->chip_class >= EVERGREEN && 527 util_format_is_depth_and_stencil(base->format) && 528 !rscreen->use_surface_alloc) { 529 struct pipe_resource stencil; 530 unsigned stencil_pitch_override = 0; 531 532 switch (base->format) { 533 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 534 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; 535 break; 536 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 537 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; 538 break; 539 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 540 rtex->real_format = PIPE_FORMAT_Z32_FLOAT; 541 break; 542 default: 543 assert(0); 544 FREE(rtex); 545 return NULL; 546 } 547 548 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ 549 if (pitch_in_bytes_override) { 550 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT || 551 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM); 552 stencil_pitch_override = pitch_in_bytes_override / 4; 553 } 554 555 /* Allocate the stencil buffer. */ 556 stencil = *base; 557 stencil.format = PIPE_FORMAT_S8_UINT; 558 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, 559 stencil_pitch_override, 560 max_buffer_size, NULL, FALSE, surface); 561 if (!rtex->stencil) { 562 FREE(rtex); 563 return NULL; 564 } 565 /* Proceed in creating the depth buffer. */ 566 } 567 568 /* only mark depth textures the HW can hit as depth textures */ 569 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base)) 570 rtex->is_depth = true; 571 572 r600_setup_miptree(screen, rtex, array_mode); 573 if (rscreen->use_surface_alloc) { 574 rtex->surface = *surface; 575 r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override); 576 if (r) { 577 FREE(rtex); 578 return NULL; 579 } 580 } 581 582 /* If we initialized separate stencil for Evergreen. place it after depth. */ 583 if (rtex->stencil) { 584 unsigned stencil_align, stencil_offset; 585 586 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); 587 stencil_offset = align(rtex->size, stencil_align); 588 589 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++) 590 rtex->stencil->offset[i] += stencil_offset; 591 592 rtex->size = stencil_offset + rtex->stencil->size; 593 } 594 595 /* Now create the backing buffer. */ 596 if (!buf && alloc_bo) { 597 struct pipe_resource *ptex = &rtex->resource.b.b.b; 598 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); 599 600 if (rscreen->use_surface_alloc) { 601 base_align = rtex->surface.bo_alignment; 602 } else if (util_format_is_depth_or_stencil(rtex->real_format)) { 603 /* ugly work around depth buffer need stencil room at end of bo */ 604 rtex->size += ptex->width0 * ptex->height0; 605 } 606 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 607 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); 608 FREE(rtex); 609 return NULL; 610 } 611 } else if (buf) { 612 resource->buf = buf; 613 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 614 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 615 } 616 617 if (rtex->stencil) { 618 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf); 619 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf; 620 rtex->stencil->resource.domains = rtex->resource.domains; 621 } 622 return rtex; 623} 624 625struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 626 const struct pipe_resource *templ) 627{ 628 struct r600_screen *rscreen = (struct r600_screen*)screen; 629 struct radeon_surface surface; 630 unsigned array_mode = 0; 631 int r; 632 633 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && 634 !(templ->bind & PIPE_BIND_SCANOUT)) { 635 if (rscreen->use_surface_alloc) { 636 if (permit_hardware_blit(screen, templ)) { 637 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 638 } 639 } else if (util_format_is_compressed(templ->format)) { 640 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 641 } 642 } 643 644 r = r600_init_surface(&surface, templ, array_mode); 645 if (r) { 646 return NULL; 647 } 648 r = rscreen->ws->surface_best(rscreen->ws, &surface); 649 if (r) { 650 return NULL; 651 } 652 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 653 0, 0, NULL, TRUE, &surface); 654} 655 656static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 657 struct pipe_resource *texture, 658 const struct pipe_surface *surf_tmpl) 659{ 660 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 661 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 662 unsigned level = surf_tmpl->u.tex.level; 663 664 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 665 if (surface == NULL) 666 return NULL; 667 /* XXX no offset */ 668/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ 669 pipe_reference_init(&surface->base.reference, 1); 670 pipe_resource_reference(&surface->base.texture, texture); 671 surface->base.context = pipe; 672 surface->base.format = surf_tmpl->format; 673 surface->base.width = mip_minify(texture->width0, level); 674 surface->base.height = mip_minify(texture->height0, level); 675 surface->base.usage = surf_tmpl->usage; 676 surface->base.texture = texture; 677 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 678 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 679 surface->base.u.tex.level = level; 680 681 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, 682 rtex, level); 683 return &surface->base; 684} 685 686static void r600_surface_destroy(struct pipe_context *pipe, 687 struct pipe_surface *surface) 688{ 689 pipe_resource_reference(&surface->texture, NULL); 690 FREE(surface); 691} 692 693struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 694 const struct pipe_resource *templ, 695 struct winsys_handle *whandle) 696{ 697 struct r600_screen *rscreen = (struct r600_screen*)screen; 698 struct pb_buffer *buf = NULL; 699 unsigned stride = 0; 700 unsigned array_mode = 0; 701 enum radeon_bo_layout micro, macro; 702 struct radeon_surface surface; 703 int r; 704 705 /* Support only 2D textures without mipmaps */ 706 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 707 templ->depth0 != 1 || templ->last_level != 0) 708 return NULL; 709 710 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 711 if (!buf) 712 return NULL; 713 714 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 715 &surface.bankw, &surface.bankh, 716 &surface.tile_split, 717 &surface.stencil_tile_split, 718 &surface.mtilea); 719 720 if (macro == RADEON_LAYOUT_TILED) 721 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 722 else if (micro == RADEON_LAYOUT_TILED) 723 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 724 else 725 array_mode = 0; 726 727 r = r600_init_surface(&surface, templ, array_mode); 728 if (r) { 729 return NULL; 730 } 731 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 732 stride, 0, buf, FALSE, &surface); 733} 734 735int r600_texture_depth_flush(struct pipe_context *ctx, 736 struct pipe_resource *texture, boolean just_create) 737{ 738 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 739 struct pipe_resource resource; 740 741 if (rtex->flushed_depth_texture) 742 goto out; 743 744 resource.target = texture->target; 745 resource.format = texture->format; 746 resource.width0 = texture->width0; 747 resource.height0 = texture->height0; 748 resource.depth0 = texture->depth0; 749 resource.array_size = texture->array_size; 750 resource.last_level = texture->last_level; 751 resource.nr_samples = texture->nr_samples; 752 resource.usage = PIPE_USAGE_DYNAMIC; 753 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL; 754 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags; 755 756 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 757 if (rtex->flushed_depth_texture == NULL) { 758 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 759 return -ENOMEM; 760 } 761 762 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE; 763out: 764 if (just_create) 765 return 0; 766 767 /* XXX: only do this if the depth texture has actually changed: 768 */ 769 r600_blit_uncompress_depth(ctx, rtex); 770 return 0; 771} 772 773/* Needs adjustment for pixelformat: 774 */ 775static INLINE unsigned u_box_volume( const struct pipe_box *box ) 776{ 777 return box->width * box->depth * box->height; 778}; 779 780struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 781 struct pipe_resource *texture, 782 unsigned level, 783 unsigned usage, 784 const struct pipe_box *box) 785{ 786 struct r600_context *rctx = (struct r600_context*)ctx; 787 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 788 struct pipe_resource resource; 789 struct r600_transfer *trans; 790 int r; 791 boolean use_staging_texture = FALSE; 792 793 if (usage & PIPE_TRANSFER_MAP_PERMANENTLY) { 794 return NULL; 795 } 796 797 /* We cannot map a tiled texture directly because the data is 798 * in a different order, therefore we do detiling using a blit. 799 * 800 * Also, use a temporary in GTT memory for read transfers, as 801 * the CPU is much happier reading out of cached system memory 802 * than uncached VRAM. 803 */ 804 if (R600_TEX_IS_TILED(rtex, level)) 805 use_staging_texture = TRUE; 806 807 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 808 use_staging_texture = TRUE; 809 810 /* Use a staging texture for uploads if the underlying BO is busy. */ 811 if (!(usage & PIPE_TRANSFER_READ) && 812 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf) || 813 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) 814 use_staging_texture = TRUE; 815 816 if (!permit_hardware_blit(ctx->screen, texture) || 817 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) 818 use_staging_texture = FALSE; 819 820 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) 821 return NULL; 822 823 trans = CALLOC_STRUCT(r600_transfer); 824 if (trans == NULL) 825 return NULL; 826 pipe_resource_reference(&trans->transfer.resource, texture); 827 trans->transfer.level = level; 828 trans->transfer.usage = usage; 829 trans->transfer.box = *box; 830 if (rtex->is_depth) { 831 /* XXX: only readback the rectangle which is being mapped? 832 */ 833 /* XXX: when discard is true, no need to read back from depth texture 834 */ 835 r = r600_texture_depth_flush(ctx, texture, FALSE); 836 if (r < 0) { 837 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 838 pipe_resource_reference(&trans->transfer.resource, NULL); 839 FREE(trans); 840 return NULL; 841 } 842 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level]; 843 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); 844 return &trans->transfer; 845 } else if (use_staging_texture) { 846 resource.target = PIPE_TEXTURE_2D; 847 resource.format = texture->format; 848 resource.width0 = box->width; 849 resource.height0 = box->height; 850 resource.depth0 = 1; 851 resource.array_size = 1; 852 resource.last_level = 0; 853 resource.nr_samples = 0; 854 resource.usage = PIPE_USAGE_STAGING; 855 resource.bind = 0; 856 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 857 /* For texture reading, the temporary (detiled) texture is used as 858 * a render target when blitting from a tiled texture. */ 859 if (usage & PIPE_TRANSFER_READ) { 860 resource.bind |= PIPE_BIND_RENDER_TARGET; 861 } 862 /* For texture writing, the temporary texture is used as a sampler 863 * when blitting into a tiled texture. */ 864 if (usage & PIPE_TRANSFER_WRITE) { 865 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 866 } 867 /* Create the temporary texture. */ 868 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 869 if (trans->staging == NULL) { 870 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 871 pipe_resource_reference(&trans->transfer.resource, NULL); 872 FREE(trans); 873 return NULL; 874 } 875 876 trans->transfer.stride = 877 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0]; 878 if (usage & PIPE_TRANSFER_READ) { 879 r600_copy_to_staging_texture(ctx, trans); 880 /* Always referenced in the blit. */ 881 r600_flush(ctx, NULL, 0); 882 } 883 return &trans->transfer; 884 } 885 trans->transfer.stride = rtex->pitch_in_bytes[level]; 886 trans->transfer.layer_stride = rtex->layer_size[level]; 887 trans->offset = r600_texture_get_offset(rtex, level, box->z); 888 return &trans->transfer; 889} 890 891void r600_texture_transfer_destroy(struct pipe_context *ctx, 892 struct pipe_transfer *transfer) 893{ 894 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 895 struct pipe_resource *texture = transfer->resource; 896 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 897 898 if (rtransfer->staging) { 899 if (transfer->usage & PIPE_TRANSFER_WRITE) { 900 r600_copy_from_staging_texture(ctx, rtransfer); 901 } 902 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 903 } 904 905 if (rtex->is_depth && !rtex->is_flushing_texture) { 906 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) 907 r600_blit_push_depth(ctx, rtex); 908 } 909 910 pipe_resource_reference(&transfer->resource, NULL); 911 FREE(transfer); 912} 913 914void* r600_texture_transfer_map(struct pipe_context *ctx, 915 struct pipe_transfer* transfer) 916{ 917 struct r600_context *rctx = (struct r600_context *)ctx; 918 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 919 struct pb_buffer *buf; 920 enum pipe_format format = transfer->resource->format; 921 unsigned offset = 0; 922 char *map; 923 924 if (rtransfer->staging) { 925 buf = ((struct r600_resource *)rtransfer->staging)->buf; 926 } else { 927 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 928 929 if (rtex->flushed_depth_texture) 930 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 931 else 932 buf = ((struct r600_resource *)transfer->resource)->buf; 933 934 offset = rtransfer->offset + 935 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 936 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 937 } 938 939 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 940 return NULL; 941 } 942 943 return map + offset; 944} 945 946void r600_texture_transfer_unmap(struct pipe_context *ctx, 947 struct pipe_transfer* transfer) 948{ 949 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 950 struct r600_context *rctx = (struct r600_context*)ctx; 951 struct pb_buffer *buf; 952 953 if (rtransfer->staging) { 954 buf = ((struct r600_resource *)rtransfer->staging)->buf; 955 } else { 956 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 957 958 if (rtex->flushed_depth_texture) { 959 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 960 } else { 961 buf = ((struct r600_resource *)transfer->resource)->buf; 962 } 963 } 964 rctx->ws->buffer_unmap(buf); 965} 966 967void r600_init_surface_functions(struct r600_context *r600) 968{ 969 r600->context.create_surface = r600_create_surface; 970 r600->context.surface_destroy = r600_surface_destroy; 971} 972 973static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 974 const unsigned char *swizzle_view) 975{ 976 unsigned i; 977 unsigned char swizzle[4]; 978 unsigned result = 0; 979 const uint32_t swizzle_shift[4] = { 980 16, 19, 22, 25, 981 }; 982 const uint32_t swizzle_bit[4] = { 983 0, 1, 2, 3, 984 }; 985 986 if (swizzle_view) { 987 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 988 } else { 989 memcpy(swizzle, swizzle_format, 4); 990 } 991 992 /* Get swizzle. */ 993 for (i = 0; i < 4; i++) { 994 switch (swizzle[i]) { 995 case UTIL_FORMAT_SWIZZLE_Y: 996 result |= swizzle_bit[1] << swizzle_shift[i]; 997 break; 998 case UTIL_FORMAT_SWIZZLE_Z: 999 result |= swizzle_bit[2] << swizzle_shift[i]; 1000 break; 1001 case UTIL_FORMAT_SWIZZLE_W: 1002 result |= swizzle_bit[3] << swizzle_shift[i]; 1003 break; 1004 case UTIL_FORMAT_SWIZZLE_0: 1005 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 1006 break; 1007 case UTIL_FORMAT_SWIZZLE_1: 1008 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 1009 break; 1010 default: /* UTIL_FORMAT_SWIZZLE_X */ 1011 result |= swizzle_bit[0] << swizzle_shift[i]; 1012 } 1013 } 1014 return result; 1015} 1016 1017/* texture format translate */ 1018uint32_t r600_translate_texformat(struct pipe_screen *screen, 1019 enum pipe_format format, 1020 const unsigned char *swizzle_view, 1021 uint32_t *word4_p, uint32_t *yuv_format_p) 1022{ 1023 uint32_t result = 0, word4 = 0, yuv_format = 0; 1024 const struct util_format_description *desc; 1025 boolean uniform = TRUE; 1026 static int r600_enable_s3tc = -1; 1027 bool is_srgb_valid = FALSE; 1028 1029 int i; 1030 const uint32_t sign_bit[4] = { 1031 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 1032 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 1033 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 1034 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 1035 }; 1036 desc = util_format_description(format); 1037 1038 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 1039 1040 /* Colorspace (return non-RGB formats directly). */ 1041 switch (desc->colorspace) { 1042 /* Depth stencil formats */ 1043 case UTIL_FORMAT_COLORSPACE_ZS: 1044 switch (format) { 1045 case PIPE_FORMAT_Z16_UNORM: 1046 result = FMT_16; 1047 goto out_word4; 1048 case PIPE_FORMAT_X24S8_UINT: 1049 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1050 case PIPE_FORMAT_Z24X8_UNORM: 1051 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1052 result = FMT_8_24; 1053 goto out_word4; 1054 case PIPE_FORMAT_S8X24_UINT: 1055 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1056 case PIPE_FORMAT_X8Z24_UNORM: 1057 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1058 result = FMT_24_8; 1059 goto out_word4; 1060 case PIPE_FORMAT_S8_UINT: 1061 result = FMT_8; 1062 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1063 goto out_word4; 1064 case PIPE_FORMAT_Z32_FLOAT: 1065 result = FMT_32_FLOAT; 1066 goto out_word4; 1067 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1068 result = FMT_X24_8_32_FLOAT; 1069 goto out_word4; 1070 default: 1071 goto out_unknown; 1072 } 1073 1074 case UTIL_FORMAT_COLORSPACE_YUV: 1075 yuv_format |= (1 << 30); 1076 switch (format) { 1077 case PIPE_FORMAT_UYVY: 1078 case PIPE_FORMAT_YUYV: 1079 default: 1080 break; 1081 } 1082 goto out_unknown; /* TODO */ 1083 1084 case UTIL_FORMAT_COLORSPACE_SRGB: 1085 word4 |= S_038010_FORCE_DEGAMMA(1); 1086 break; 1087 1088 default: 1089 break; 1090 } 1091 1092 if (r600_enable_s3tc == -1) { 1093 struct r600_screen *rscreen = (struct r600_screen *)screen; 1094 if (rscreen->info.drm_minor >= 9) 1095 r600_enable_s3tc = 1; 1096 else 1097 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 1098 } 1099 1100 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1101 if (!r600_enable_s3tc) 1102 goto out_unknown; 1103 1104 switch (format) { 1105 case PIPE_FORMAT_RGTC1_SNORM: 1106 case PIPE_FORMAT_LATC1_SNORM: 1107 word4 |= sign_bit[0]; 1108 case PIPE_FORMAT_RGTC1_UNORM: 1109 case PIPE_FORMAT_LATC1_UNORM: 1110 result = FMT_BC4; 1111 goto out_word4; 1112 case PIPE_FORMAT_RGTC2_SNORM: 1113 case PIPE_FORMAT_LATC2_SNORM: 1114 word4 |= sign_bit[0] | sign_bit[1]; 1115 case PIPE_FORMAT_RGTC2_UNORM: 1116 case PIPE_FORMAT_LATC2_UNORM: 1117 result = FMT_BC5; 1118 goto out_word4; 1119 default: 1120 goto out_unknown; 1121 } 1122 } 1123 1124 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1125 1126 if (!r600_enable_s3tc) 1127 goto out_unknown; 1128 1129 if (!util_format_s3tc_enabled) { 1130 goto out_unknown; 1131 } 1132 1133 switch (format) { 1134 case PIPE_FORMAT_DXT1_RGB: 1135 case PIPE_FORMAT_DXT1_RGBA: 1136 case PIPE_FORMAT_DXT1_SRGB: 1137 case PIPE_FORMAT_DXT1_SRGBA: 1138 result = FMT_BC1; 1139 is_srgb_valid = TRUE; 1140 goto out_word4; 1141 case PIPE_FORMAT_DXT3_RGBA: 1142 case PIPE_FORMAT_DXT3_SRGBA: 1143 result = FMT_BC2; 1144 is_srgb_valid = TRUE; 1145 goto out_word4; 1146 case PIPE_FORMAT_DXT5_RGBA: 1147 case PIPE_FORMAT_DXT5_SRGBA: 1148 result = FMT_BC3; 1149 is_srgb_valid = TRUE; 1150 goto out_word4; 1151 default: 1152 goto out_unknown; 1153 } 1154 } 1155 1156 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1157 result = FMT_5_9_9_9_SHAREDEXP; 1158 goto out_word4; 1159 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1160 result = FMT_10_11_11_FLOAT; 1161 goto out_word4; 1162 } 1163 1164 1165 for (i = 0; i < desc->nr_channels; i++) { 1166 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1167 word4 |= sign_bit[i]; 1168 } 1169 } 1170 1171 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1172 1173 /* See whether the components are of the same size. */ 1174 for (i = 1; i < desc->nr_channels; i++) { 1175 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1176 } 1177 1178 /* Non-uniform formats. */ 1179 if (!uniform) { 1180 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1181 desc->channel[0].pure_integer) 1182 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1183 switch(desc->nr_channels) { 1184 case 3: 1185 if (desc->channel[0].size == 5 && 1186 desc->channel[1].size == 6 && 1187 desc->channel[2].size == 5) { 1188 result = FMT_5_6_5; 1189 goto out_word4; 1190 } 1191 goto out_unknown; 1192 case 4: 1193 if (desc->channel[0].size == 5 && 1194 desc->channel[1].size == 5 && 1195 desc->channel[2].size == 5 && 1196 desc->channel[3].size == 1) { 1197 result = FMT_1_5_5_5; 1198 goto out_word4; 1199 } 1200 if (desc->channel[0].size == 10 && 1201 desc->channel[1].size == 10 && 1202 desc->channel[2].size == 10 && 1203 desc->channel[3].size == 2) { 1204 result = FMT_2_10_10_10; 1205 goto out_word4; 1206 } 1207 goto out_unknown; 1208 } 1209 goto out_unknown; 1210 } 1211 1212 /* Find the first non-VOID channel. */ 1213 for (i = 0; i < 4; i++) { 1214 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1215 break; 1216 } 1217 } 1218 1219 if (i == 4) 1220 goto out_unknown; 1221 1222 /* uniform formats */ 1223 switch (desc->channel[i].type) { 1224 case UTIL_FORMAT_TYPE_UNSIGNED: 1225 case UTIL_FORMAT_TYPE_SIGNED: 1226#if 0 1227 if (!desc->channel[i].normalized && 1228 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 1229 goto out_unknown; 1230 } 1231#endif 1232 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1233 desc->channel[i].pure_integer) 1234 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1235 1236 switch (desc->channel[i].size) { 1237 case 4: 1238 switch (desc->nr_channels) { 1239 case 2: 1240 result = FMT_4_4; 1241 goto out_word4; 1242 case 4: 1243 result = FMT_4_4_4_4; 1244 goto out_word4; 1245 } 1246 goto out_unknown; 1247 case 8: 1248 switch (desc->nr_channels) { 1249 case 1: 1250 result = FMT_8; 1251 goto out_word4; 1252 case 2: 1253 result = FMT_8_8; 1254 goto out_word4; 1255 case 4: 1256 result = FMT_8_8_8_8; 1257 is_srgb_valid = TRUE; 1258 goto out_word4; 1259 } 1260 goto out_unknown; 1261 case 16: 1262 switch (desc->nr_channels) { 1263 case 1: 1264 result = FMT_16; 1265 goto out_word4; 1266 case 2: 1267 result = FMT_16_16; 1268 goto out_word4; 1269 case 4: 1270 result = FMT_16_16_16_16; 1271 goto out_word4; 1272 } 1273 goto out_unknown; 1274 case 32: 1275 switch (desc->nr_channels) { 1276 case 1: 1277 result = FMT_32; 1278 goto out_word4; 1279 case 2: 1280 result = FMT_32_32; 1281 goto out_word4; 1282 case 4: 1283 result = FMT_32_32_32_32; 1284 goto out_word4; 1285 } 1286 } 1287 goto out_unknown; 1288 1289 case UTIL_FORMAT_TYPE_FLOAT: 1290 switch (desc->channel[i].size) { 1291 case 16: 1292 switch (desc->nr_channels) { 1293 case 1: 1294 result = FMT_16_FLOAT; 1295 goto out_word4; 1296 case 2: 1297 result = FMT_16_16_FLOAT; 1298 goto out_word4; 1299 case 4: 1300 result = FMT_16_16_16_16_FLOAT; 1301 goto out_word4; 1302 } 1303 goto out_unknown; 1304 case 32: 1305 switch (desc->nr_channels) { 1306 case 1: 1307 result = FMT_32_FLOAT; 1308 goto out_word4; 1309 case 2: 1310 result = FMT_32_32_FLOAT; 1311 goto out_word4; 1312 case 4: 1313 result = FMT_32_32_32_32_FLOAT; 1314 goto out_word4; 1315 } 1316 } 1317 goto out_unknown; 1318 } 1319 1320out_word4: 1321 1322 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1323 return ~0; 1324 if (word4_p) 1325 *word4_p = word4; 1326 if (yuv_format_p) 1327 *yuv_format_p = yuv_format; 1328 return result; 1329out_unknown: 1330 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1331 return ~0; 1332} 1333