r600_texture.c revision 951ac46a6a0a901b53a518c8dcde734578cbf228
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include <errno.h> 31#include "util/u_format_s3tc.h" 32#include "util/u_memory.h" 33 34/* Copy from a full GPU texture to a transfer's staging one. */ 35static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 36{ 37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 38 struct pipe_resource *texture = transfer->resource; 39 40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b, 41 0, 0, 0, 0, texture, transfer->level, 42 &transfer->box); 43} 44 45 46/* Copy from a transfer's staging texture to a full GPU one. */ 47static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 48{ 49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 50 struct pipe_resource *texture = transfer->resource; 51 struct pipe_box sbox; 52 53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox); 54 55 ctx->resource_copy_region(ctx, texture, transfer->level, 56 transfer->box.x, transfer->box.y, transfer->box.z, 57 &rtransfer->staging->b.b, 58 0, &sbox); 59} 60 61unsigned r600_texture_get_offset(struct r600_texture *rtex, 62 unsigned level, unsigned layer) 63{ 64 return rtex->surface.level[level].offset + 65 layer * rtex->surface.level[level].slice_size; 66} 67 68static int r600_init_surface(struct r600_screen *rscreen, 69 struct radeon_surface *surface, 70 const struct pipe_resource *ptex, 71 unsigned array_mode, 72 bool is_transfer, bool is_flushed_depth) 73{ 74 const struct util_format_description *desc = 75 util_format_description(ptex->format); 76 bool is_depth, is_stencil; 77 78 is_depth = util_format_has_depth(desc); 79 is_stencil = util_format_has_stencil(desc); 80 81 surface->npix_x = ptex->width0; 82 surface->npix_y = ptex->height0; 83 surface->npix_z = ptex->depth0; 84 surface->blk_w = util_format_get_blockwidth(ptex->format); 85 surface->blk_h = util_format_get_blockheight(ptex->format); 86 surface->blk_d = 1; 87 surface->array_size = 1; 88 surface->last_level = ptex->last_level; 89 90 if (rscreen->chip_class >= EVERGREEN && 91 !is_transfer && !is_flushed_depth && 92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { 93 surface->bpe = 4; /* stencil is allocated separately on evergreen */ 94 } else { 95 surface->bpe = util_format_get_blocksize(ptex->format); 96 /* align byte per element on dword */ 97 if (surface->bpe == 3) { 98 surface->bpe = 4; 99 } 100 } 101 102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1; 103 surface->flags = 0; 104 105 switch (array_mode) { 106 case V_038000_ARRAY_1D_TILED_THIN1: 107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 108 break; 109 case V_038000_ARRAY_2D_TILED_THIN1: 110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 111 break; 112 case V_038000_ARRAY_LINEAR_ALIGNED: 113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 114 break; 115 case V_038000_ARRAY_LINEAR_GENERAL: 116 default: 117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 118 break; 119 } 120 switch (ptex->target) { 121 case PIPE_TEXTURE_1D: 122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 123 break; 124 case PIPE_TEXTURE_RECT: 125 case PIPE_TEXTURE_2D: 126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 127 break; 128 case PIPE_TEXTURE_3D: 129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 130 break; 131 case PIPE_TEXTURE_1D_ARRAY: 132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 133 surface->array_size = ptex->array_size; 134 break; 135 case PIPE_TEXTURE_2D_ARRAY: 136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 137 surface->array_size = ptex->array_size; 138 break; 139 case PIPE_TEXTURE_CUBE: 140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 141 break; 142 case PIPE_BUFFER: 143 default: 144 return -EINVAL; 145 } 146 if (ptex->bind & PIPE_BIND_SCANOUT) { 147 surface->flags |= RADEON_SURF_SCANOUT; 148 } 149 150 if (!is_transfer && !is_flushed_depth && is_depth) { 151 surface->flags |= RADEON_SURF_ZBUFFER; 152 153 if (is_stencil) { 154 surface->flags |= RADEON_SURF_SBUFFER; 155 } 156 } 157 return 0; 158} 159 160static int r600_setup_surface(struct pipe_screen *screen, 161 struct r600_texture *rtex, 162 unsigned pitch_in_bytes_override) 163{ 164 struct pipe_resource *ptex = &rtex->resource.b.b; 165 struct r600_screen *rscreen = (struct r600_screen*)screen; 166 unsigned i; 167 int r; 168 169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 170 if (r) { 171 return r; 172 } 173 rtex->size = rtex->surface.bo_size; 174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 176 * for those 177 */ 178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 183 } 184 } 185 for (i = 0; i <= ptex->last_level; i++) { 186 switch (rtex->surface.level[i].mode) { 187 case RADEON_SURF_MODE_LINEAR_ALIGNED: 188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 189 break; 190 case RADEON_SURF_MODE_1D: 191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 192 break; 193 case RADEON_SURF_MODE_2D: 194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 195 break; 196 default: 197 case RADEON_SURF_MODE_LINEAR: 198 rtex->array_mode[i] = 0; 199 break; 200 } 201 } 202 return 0; 203} 204 205static boolean r600_texture_get_handle(struct pipe_screen* screen, 206 struct pipe_resource *ptex, 207 struct winsys_handle *whandle) 208{ 209 struct r600_texture *rtex = (struct r600_texture*)ptex; 210 struct r600_resource *resource = &rtex->resource; 211 struct radeon_surface *surface = &rtex->surface; 212 struct r600_screen *rscreen = (struct r600_screen*)screen; 213 214 rscreen->ws->buffer_set_tiling(resource->buf, 215 NULL, 216 surface->level[0].mode >= RADEON_SURF_MODE_1D ? 217 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 218 surface->level[0].mode >= RADEON_SURF_MODE_2D ? 219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 220 surface->bankw, surface->bankh, 221 surface->tile_split, 222 surface->stencil_tile_split, 223 surface->mtilea, 224 rtex->surface.level[0].pitch_bytes); 225 226 return rscreen->ws->buffer_get_handle(resource->buf, 227 rtex->surface.level[0].pitch_bytes, whandle); 228} 229 230static void r600_texture_destroy(struct pipe_screen *screen, 231 struct pipe_resource *ptex) 232{ 233 struct r600_texture *rtex = (struct r600_texture*)ptex; 234 struct r600_resource *resource = &rtex->resource; 235 236 if (rtex->flushed_depth_texture) 237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 238 239 pb_reference(&resource->buf, NULL); 240 FREE(rtex); 241} 242 243static const struct u_resource_vtbl r600_texture_vtbl = 244{ 245 r600_texture_get_handle, /* get_handle */ 246 r600_texture_destroy, /* resource_destroy */ 247 r600_texture_get_transfer, /* get_transfer */ 248 r600_texture_transfer_destroy, /* transfer_destroy */ 249 r600_texture_transfer_map, /* transfer_map */ 250 NULL, /* transfer_flush_region */ 251 r600_texture_transfer_unmap, /* transfer_unmap */ 252 NULL /* transfer_inline_write */ 253}; 254 255static struct r600_texture * 256r600_texture_create_object(struct pipe_screen *screen, 257 const struct pipe_resource *base, 258 unsigned pitch_in_bytes_override, 259 struct pb_buffer *buf, 260 boolean alloc_bo, 261 struct radeon_surface *surface) 262{ 263 struct r600_texture *rtex; 264 struct r600_resource *resource; 265 struct r600_screen *rscreen = (struct r600_screen*)screen; 266 int r; 267 268 rtex = CALLOC_STRUCT(r600_texture); 269 if (rtex == NULL) 270 return NULL; 271 272 resource = &rtex->resource; 273 resource->b.b = *base; 274 resource->b.vtbl = &r600_texture_vtbl; 275 pipe_reference_init(&resource->b.b.reference, 1); 276 resource->b.b.screen = screen; 277 rtex->pitch_override = pitch_in_bytes_override; 278 279 /* don't include stencil-only formats which we don't support for rendering */ 280 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); 281 282 rtex->surface = *surface; 283 r = r600_setup_surface(screen, rtex, 284 pitch_in_bytes_override); 285 if (r) { 286 FREE(rtex); 287 return NULL; 288 } 289 290 /* Now create the backing buffer. */ 291 if (!buf && alloc_bo) { 292 unsigned base_align = rtex->surface.bo_alignment; 293 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage; 294 295 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) { 296 FREE(rtex); 297 return NULL; 298 } 299 } else if (buf) { 300 resource->buf = buf; 301 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 302 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 303 } 304 return rtex; 305} 306 307struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 308 const struct pipe_resource *templ) 309{ 310 struct r600_screen *rscreen = (struct r600_screen*)screen; 311 struct radeon_surface surface; 312 unsigned array_mode = 0; 313 int r; 314 315 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 316 if (!(templ->bind & PIPE_BIND_SCANOUT) && 317 templ->usage != PIPE_USAGE_STAGING && 318 templ->usage != PIPE_USAGE_STREAM) { 319 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 320 } else if (util_format_is_compressed(templ->format)) { 321 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 322 } 323 } 324 325 r = r600_init_surface(rscreen, &surface, templ, array_mode, 326 templ->flags & R600_RESOURCE_FLAG_TRANSFER, 327 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); 328 if (r) { 329 return NULL; 330 } 331 r = rscreen->ws->surface_best(rscreen->ws, &surface); 332 if (r) { 333 return NULL; 334 } 335 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 336 0, NULL, TRUE, &surface); 337} 338 339static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 340 struct pipe_resource *texture, 341 const struct pipe_surface *templ) 342{ 343 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 344 unsigned level = templ->u.tex.level; 345 346 assert(templ->u.tex.first_layer == templ->u.tex.last_layer); 347 if (surface == NULL) 348 return NULL; 349 pipe_reference_init(&surface->base.reference, 1); 350 pipe_resource_reference(&surface->base.texture, texture); 351 surface->base.context = pipe; 352 surface->base.format = templ->format; 353 surface->base.width = u_minify(texture->width0, level); 354 surface->base.height = u_minify(texture->height0, level); 355 surface->base.usage = templ->usage; 356 surface->base.u = templ->u; 357 return &surface->base; 358} 359 360static void r600_surface_destroy(struct pipe_context *pipe, 361 struct pipe_surface *surface) 362{ 363 pipe_resource_reference(&surface->texture, NULL); 364 FREE(surface); 365} 366 367struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 368 const struct pipe_resource *templ, 369 struct winsys_handle *whandle) 370{ 371 struct r600_screen *rscreen = (struct r600_screen*)screen; 372 struct pb_buffer *buf = NULL; 373 unsigned stride = 0; 374 unsigned array_mode = 0; 375 enum radeon_bo_layout micro, macro; 376 struct radeon_surface surface; 377 int r; 378 379 /* Support only 2D textures without mipmaps */ 380 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 381 templ->depth0 != 1 || templ->last_level != 0) 382 return NULL; 383 384 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 385 if (!buf) 386 return NULL; 387 388 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 389 &surface.bankw, &surface.bankh, 390 &surface.tile_split, 391 &surface.stencil_tile_split, 392 &surface.mtilea); 393 394 if (macro == RADEON_LAYOUT_TILED) 395 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 396 else if (micro == RADEON_LAYOUT_TILED) 397 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 398 else 399 array_mode = 0; 400 401 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false); 402 if (r) { 403 return NULL; 404 } 405 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 406 stride, buf, FALSE, &surface); 407} 408 409bool r600_init_flushed_depth_texture(struct pipe_context *ctx, 410 struct pipe_resource *texture, 411 struct r600_texture **staging) 412{ 413 struct r600_texture *rtex = (struct r600_texture*)texture; 414 struct pipe_resource resource; 415 struct r600_texture **flushed_depth_texture = staging ? 416 staging : &rtex->flushed_depth_texture; 417 418 if (!staging && rtex->flushed_depth_texture) 419 return true; /* it's ready */ 420 421 resource.target = texture->target; 422 resource.format = texture->format; 423 resource.width0 = texture->width0; 424 resource.height0 = texture->height0; 425 resource.depth0 = texture->depth0; 426 resource.array_size = texture->array_size; 427 resource.last_level = texture->last_level; 428 resource.nr_samples = texture->nr_samples; 429 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC; 430 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; 431 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; 432 433 if (staging) 434 resource.flags |= R600_RESOURCE_FLAG_TRANSFER; 435 436 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource); 437 if (*flushed_depth_texture == NULL) { 438 R600_ERR("failed to create temporary texture to hold flushed depth\n"); 439 return false; 440 } 441 442 (*flushed_depth_texture)->is_flushing_texture = TRUE; 443 return true; 444} 445 446/* Needs adjustment for pixelformat: 447 */ 448static INLINE unsigned u_box_volume( const struct pipe_box *box ) 449{ 450 return box->width * box->depth * box->height; 451} 452 453struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 454 struct pipe_resource *texture, 455 unsigned level, 456 unsigned usage, 457 const struct pipe_box *box) 458{ 459 struct r600_context *rctx = (struct r600_context*)ctx; 460 struct r600_texture *rtex = (struct r600_texture*)texture; 461 struct pipe_resource resource; 462 struct r600_transfer *trans; 463 boolean use_staging_texture = FALSE; 464 465 /* We cannot map a tiled texture directly because the data is 466 * in a different order, therefore we do detiling using a blit. 467 * 468 * Also, use a temporary in GTT memory for read transfers, as 469 * the CPU is much happier reading out of cached system memory 470 * than uncached VRAM. 471 */ 472 if (R600_TEX_IS_TILED(rtex, level)) { 473 use_staging_texture = TRUE; 474 } 475 476 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 477 use_staging_texture = TRUE; 478 479 /* Use a staging texture for uploads if the underlying BO is busy. */ 480 if (!(usage & PIPE_TRANSFER_READ) && 481 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 482 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { 483 use_staging_texture = TRUE; 484 } 485 486 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) { 487 use_staging_texture = FALSE; 488 } 489 490 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) { 491 return NULL; 492 } 493 494 trans = CALLOC_STRUCT(r600_transfer); 495 if (trans == NULL) 496 return NULL; 497 pipe_resource_reference(&trans->transfer.resource, texture); 498 trans->transfer.level = level; 499 trans->transfer.usage = usage; 500 trans->transfer.box = *box; 501 if (rtex->is_depth) { 502 /* XXX: only readback the rectangle which is being mapped? 503 */ 504 /* XXX: when discard is true, no need to read back from depth texture 505 */ 506 struct r600_texture *staging_depth; 507 508 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { 509 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 510 pipe_resource_reference(&trans->transfer.resource, NULL); 511 FREE(trans); 512 return NULL; 513 } 514 515 r600_blit_uncompress_depth(ctx, rtex, staging_depth, 516 level, level, 517 box->z, box->z + box->depth - 1, 518 0, 0); 519 520 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; 521 trans->offset = r600_texture_get_offset(staging_depth, level, box->z); 522 trans->staging = (struct r600_resource*)staging_depth; 523 return &trans->transfer; 524 } else if (use_staging_texture) { 525 resource.target = PIPE_TEXTURE_2D; 526 resource.format = texture->format; 527 resource.width0 = box->width; 528 resource.height0 = box->height; 529 resource.depth0 = 1; 530 resource.array_size = 1; 531 resource.last_level = 0; 532 resource.nr_samples = 0; 533 resource.usage = PIPE_USAGE_STAGING; 534 resource.bind = 0; 535 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 536 /* For texture reading, the temporary (detiled) texture is used as 537 * a render target when blitting from a tiled texture. */ 538 if (usage & PIPE_TRANSFER_READ) { 539 resource.bind |= PIPE_BIND_RENDER_TARGET; 540 } 541 /* For texture writing, the temporary texture is used as a sampler 542 * when blitting into a tiled texture. */ 543 if (usage & PIPE_TRANSFER_WRITE) { 544 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 545 } 546 /* Create the temporary texture. */ 547 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 548 if (trans->staging == NULL) { 549 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 550 pipe_resource_reference(&trans->transfer.resource, NULL); 551 FREE(trans); 552 return NULL; 553 } 554 555 trans->transfer.stride = 556 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes; 557 if (usage & PIPE_TRANSFER_READ) { 558 r600_copy_to_staging_texture(ctx, trans); 559 /* Always referenced in the blit. */ 560 r600_flush(ctx, NULL, 0); 561 } 562 return &trans->transfer; 563 } 564 trans->transfer.stride = rtex->surface.level[level].pitch_bytes; 565 trans->transfer.layer_stride = rtex->surface.level[level].slice_size; 566 trans->offset = r600_texture_get_offset(rtex, level, box->z); 567 return &trans->transfer; 568} 569 570void r600_texture_transfer_destroy(struct pipe_context *ctx, 571 struct pipe_transfer *transfer) 572{ 573 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 574 struct pipe_resource *texture = transfer->resource; 575 struct r600_texture *rtex = (struct r600_texture*)texture; 576 577 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { 578 if (rtex->is_depth) { 579 ctx->resource_copy_region(ctx, texture, transfer->level, 580 transfer->box.x, transfer->box.y, transfer->box.z, 581 &rtransfer->staging->b.b, transfer->level, 582 &transfer->box); 583 } else { 584 r600_copy_from_staging_texture(ctx, rtransfer); 585 } 586 } 587 588 if (rtransfer->staging) 589 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 590 591 pipe_resource_reference(&transfer->resource, NULL); 592 FREE(transfer); 593} 594 595void* r600_texture_transfer_map(struct pipe_context *ctx, 596 struct pipe_transfer* transfer) 597{ 598 struct r600_context *rctx = (struct r600_context *)ctx; 599 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 600 struct radeon_winsys_cs_handle *buf; 601 struct r600_texture *rtex = 602 (struct r600_texture*)transfer->resource; 603 enum pipe_format format = transfer->resource->format; 604 unsigned offset = 0; 605 char *map; 606 607 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 608 return r600_compute_global_transfer_map(ctx, transfer); 609 } 610 611 if (rtransfer->staging) { 612 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 613 } else { 614 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 615 } 616 617 if (rtex->is_depth || !rtransfer->staging) 618 offset = rtransfer->offset + 619 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 620 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 621 622 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 623 return NULL; 624 } 625 626 return map + offset; 627} 628 629void r600_texture_transfer_unmap(struct pipe_context *ctx, 630 struct pipe_transfer* transfer) 631{ 632 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 633 struct r600_context *rctx = (struct r600_context*)ctx; 634 struct radeon_winsys_cs_handle *buf; 635 636 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 637 return r600_compute_global_transfer_unmap(ctx, transfer); 638 } 639 640 if (rtransfer->staging) { 641 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 642 } else { 643 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 644 } 645 rctx->ws->buffer_unmap(buf); 646} 647 648void r600_init_surface_functions(struct r600_context *r600) 649{ 650 r600->context.create_surface = r600_create_surface; 651 r600->context.surface_destroy = r600_surface_destroy; 652} 653 654static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 655 const unsigned char *swizzle_view) 656{ 657 unsigned i; 658 unsigned char swizzle[4]; 659 unsigned result = 0; 660 const uint32_t swizzle_shift[4] = { 661 16, 19, 22, 25, 662 }; 663 const uint32_t swizzle_bit[4] = { 664 0, 1, 2, 3, 665 }; 666 667 if (swizzle_view) { 668 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 669 } else { 670 memcpy(swizzle, swizzle_format, 4); 671 } 672 673 /* Get swizzle. */ 674 for (i = 0; i < 4; i++) { 675 switch (swizzle[i]) { 676 case UTIL_FORMAT_SWIZZLE_Y: 677 result |= swizzle_bit[1] << swizzle_shift[i]; 678 break; 679 case UTIL_FORMAT_SWIZZLE_Z: 680 result |= swizzle_bit[2] << swizzle_shift[i]; 681 break; 682 case UTIL_FORMAT_SWIZZLE_W: 683 result |= swizzle_bit[3] << swizzle_shift[i]; 684 break; 685 case UTIL_FORMAT_SWIZZLE_0: 686 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 687 break; 688 case UTIL_FORMAT_SWIZZLE_1: 689 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 690 break; 691 default: /* UTIL_FORMAT_SWIZZLE_X */ 692 result |= swizzle_bit[0] << swizzle_shift[i]; 693 } 694 } 695 return result; 696} 697 698/* texture format translate */ 699uint32_t r600_translate_texformat(struct pipe_screen *screen, 700 enum pipe_format format, 701 const unsigned char *swizzle_view, 702 uint32_t *word4_p, uint32_t *yuv_format_p) 703{ 704 uint32_t result = 0, word4 = 0, yuv_format = 0; 705 const struct util_format_description *desc; 706 boolean uniform = TRUE; 707 static int r600_enable_s3tc = -1; 708 bool is_srgb_valid = FALSE; 709 710 int i; 711 const uint32_t sign_bit[4] = { 712 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 713 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 714 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 715 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 716 }; 717 desc = util_format_description(format); 718 719 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 720 721 /* Colorspace (return non-RGB formats directly). */ 722 switch (desc->colorspace) { 723 /* Depth stencil formats */ 724 case UTIL_FORMAT_COLORSPACE_ZS: 725 switch (format) { 726 case PIPE_FORMAT_Z16_UNORM: 727 result = FMT_16; 728 goto out_word4; 729 case PIPE_FORMAT_X24S8_UINT: 730 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 731 case PIPE_FORMAT_Z24X8_UNORM: 732 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 733 result = FMT_8_24; 734 goto out_word4; 735 case PIPE_FORMAT_S8X24_UINT: 736 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 737 case PIPE_FORMAT_X8Z24_UNORM: 738 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 739 result = FMT_24_8; 740 goto out_word4; 741 case PIPE_FORMAT_S8_UINT: 742 result = FMT_8; 743 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 744 goto out_word4; 745 case PIPE_FORMAT_Z32_FLOAT: 746 result = FMT_32_FLOAT; 747 goto out_word4; 748 case PIPE_FORMAT_X32_S8X24_UINT: 749 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 750 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 751 result = FMT_X24_8_32_FLOAT; 752 goto out_word4; 753 default: 754 goto out_unknown; 755 } 756 757 case UTIL_FORMAT_COLORSPACE_YUV: 758 yuv_format |= (1 << 30); 759 switch (format) { 760 case PIPE_FORMAT_UYVY: 761 case PIPE_FORMAT_YUYV: 762 default: 763 break; 764 } 765 goto out_unknown; /* XXX */ 766 767 case UTIL_FORMAT_COLORSPACE_SRGB: 768 word4 |= S_038010_FORCE_DEGAMMA(1); 769 break; 770 771 default: 772 break; 773 } 774 775 if (r600_enable_s3tc == -1) { 776 struct r600_screen *rscreen = (struct r600_screen *)screen; 777 if (rscreen->info.drm_minor >= 9) 778 r600_enable_s3tc = 1; 779 else 780 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 781 } 782 783 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 784 if (!r600_enable_s3tc) 785 goto out_unknown; 786 787 switch (format) { 788 case PIPE_FORMAT_RGTC1_SNORM: 789 case PIPE_FORMAT_LATC1_SNORM: 790 word4 |= sign_bit[0]; 791 case PIPE_FORMAT_RGTC1_UNORM: 792 case PIPE_FORMAT_LATC1_UNORM: 793 result = FMT_BC4; 794 goto out_word4; 795 case PIPE_FORMAT_RGTC2_SNORM: 796 case PIPE_FORMAT_LATC2_SNORM: 797 word4 |= sign_bit[0] | sign_bit[1]; 798 case PIPE_FORMAT_RGTC2_UNORM: 799 case PIPE_FORMAT_LATC2_UNORM: 800 result = FMT_BC5; 801 goto out_word4; 802 default: 803 goto out_unknown; 804 } 805 } 806 807 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 808 809 if (!r600_enable_s3tc) 810 goto out_unknown; 811 812 if (!util_format_s3tc_enabled) { 813 goto out_unknown; 814 } 815 816 switch (format) { 817 case PIPE_FORMAT_DXT1_RGB: 818 case PIPE_FORMAT_DXT1_RGBA: 819 case PIPE_FORMAT_DXT1_SRGB: 820 case PIPE_FORMAT_DXT1_SRGBA: 821 result = FMT_BC1; 822 is_srgb_valid = TRUE; 823 goto out_word4; 824 case PIPE_FORMAT_DXT3_RGBA: 825 case PIPE_FORMAT_DXT3_SRGBA: 826 result = FMT_BC2; 827 is_srgb_valid = TRUE; 828 goto out_word4; 829 case PIPE_FORMAT_DXT5_RGBA: 830 case PIPE_FORMAT_DXT5_SRGBA: 831 result = FMT_BC3; 832 is_srgb_valid = TRUE; 833 goto out_word4; 834 default: 835 goto out_unknown; 836 } 837 } 838 839 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 840 switch (format) { 841 case PIPE_FORMAT_R8G8_B8G8_UNORM: 842 case PIPE_FORMAT_G8R8_B8R8_UNORM: 843 result = FMT_GB_GR; 844 goto out_word4; 845 case PIPE_FORMAT_G8R8_G8B8_UNORM: 846 case PIPE_FORMAT_R8G8_R8B8_UNORM: 847 result = FMT_BG_RG; 848 goto out_word4; 849 default: 850 goto out_unknown; 851 } 852 } 853 854 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 855 result = FMT_5_9_9_9_SHAREDEXP; 856 goto out_word4; 857 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 858 result = FMT_10_11_11_FLOAT; 859 goto out_word4; 860 } 861 862 863 for (i = 0; i < desc->nr_channels; i++) { 864 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 865 word4 |= sign_bit[i]; 866 } 867 } 868 869 /* R8G8Bx_SNORM - XXX CxV8U8 */ 870 871 /* See whether the components are of the same size. */ 872 for (i = 1; i < desc->nr_channels; i++) { 873 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 874 } 875 876 /* Non-uniform formats. */ 877 if (!uniform) { 878 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 879 desc->channel[0].pure_integer) 880 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 881 switch(desc->nr_channels) { 882 case 3: 883 if (desc->channel[0].size == 5 && 884 desc->channel[1].size == 6 && 885 desc->channel[2].size == 5) { 886 result = FMT_5_6_5; 887 goto out_word4; 888 } 889 goto out_unknown; 890 case 4: 891 if (desc->channel[0].size == 5 && 892 desc->channel[1].size == 5 && 893 desc->channel[2].size == 5 && 894 desc->channel[3].size == 1) { 895 result = FMT_1_5_5_5; 896 goto out_word4; 897 } 898 if (desc->channel[0].size == 10 && 899 desc->channel[1].size == 10 && 900 desc->channel[2].size == 10 && 901 desc->channel[3].size == 2) { 902 result = FMT_2_10_10_10; 903 goto out_word4; 904 } 905 goto out_unknown; 906 } 907 goto out_unknown; 908 } 909 910 /* Find the first non-VOID channel. */ 911 for (i = 0; i < 4; i++) { 912 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 913 break; 914 } 915 } 916 917 if (i == 4) 918 goto out_unknown; 919 920 /* uniform formats */ 921 switch (desc->channel[i].type) { 922 case UTIL_FORMAT_TYPE_UNSIGNED: 923 case UTIL_FORMAT_TYPE_SIGNED: 924#if 0 925 if (!desc->channel[i].normalized && 926 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 927 goto out_unknown; 928 } 929#endif 930 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 931 desc->channel[i].pure_integer) 932 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 933 934 switch (desc->channel[i].size) { 935 case 4: 936 switch (desc->nr_channels) { 937 case 2: 938 result = FMT_4_4; 939 goto out_word4; 940 case 4: 941 result = FMT_4_4_4_4; 942 goto out_word4; 943 } 944 goto out_unknown; 945 case 8: 946 switch (desc->nr_channels) { 947 case 1: 948 result = FMT_8; 949 goto out_word4; 950 case 2: 951 result = FMT_8_8; 952 goto out_word4; 953 case 4: 954 result = FMT_8_8_8_8; 955 is_srgb_valid = TRUE; 956 goto out_word4; 957 } 958 goto out_unknown; 959 case 16: 960 switch (desc->nr_channels) { 961 case 1: 962 result = FMT_16; 963 goto out_word4; 964 case 2: 965 result = FMT_16_16; 966 goto out_word4; 967 case 4: 968 result = FMT_16_16_16_16; 969 goto out_word4; 970 } 971 goto out_unknown; 972 case 32: 973 switch (desc->nr_channels) { 974 case 1: 975 result = FMT_32; 976 goto out_word4; 977 case 2: 978 result = FMT_32_32; 979 goto out_word4; 980 case 4: 981 result = FMT_32_32_32_32; 982 goto out_word4; 983 } 984 } 985 goto out_unknown; 986 987 case UTIL_FORMAT_TYPE_FLOAT: 988 switch (desc->channel[i].size) { 989 case 16: 990 switch (desc->nr_channels) { 991 case 1: 992 result = FMT_16_FLOAT; 993 goto out_word4; 994 case 2: 995 result = FMT_16_16_FLOAT; 996 goto out_word4; 997 case 4: 998 result = FMT_16_16_16_16_FLOAT; 999 goto out_word4; 1000 } 1001 goto out_unknown; 1002 case 32: 1003 switch (desc->nr_channels) { 1004 case 1: 1005 result = FMT_32_FLOAT; 1006 goto out_word4; 1007 case 2: 1008 result = FMT_32_32_FLOAT; 1009 goto out_word4; 1010 case 4: 1011 result = FMT_32_32_32_32_FLOAT; 1012 goto out_word4; 1013 } 1014 } 1015 goto out_unknown; 1016 } 1017 1018out_word4: 1019 1020 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1021 return ~0; 1022 if (word4_p) 1023 *word4_p = word4; 1024 if (yuv_format_p) 1025 *yuv_format_p = yuv_format; 1026 return result; 1027out_unknown: 1028 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1029 return ~0; 1030} 1031