r600_texture.c revision d5e91a2364a497efb75aefe6538e64d4e5ada51a
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include <errno.h> 28#include "pipe/p_screen.h" 29#include "util/u_format.h" 30#include "util/u_format_s3tc.h" 31#include "util/u_math.h" 32#include "util/u_inlines.h" 33#include "util/u_memory.h" 34#include "pipebuffer/pb_buffer.h" 35#include "r600_pipe.h" 36#include "r600_resource.h" 37#include "r600d.h" 38#include "r600_formats.h" 39 40/* Copy from a full GPU texture to a transfer's staging one. */ 41static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 42{ 43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 44 struct pipe_resource *texture = transfer->resource; 45 46 ctx->resource_copy_region(ctx, rtransfer->staging_texture, 47 0, 0, 0, 0, texture, transfer->level, 48 &transfer->box); 49} 50 51 52/* Copy from a transfer's staging texture to a full GPU one. */ 53static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 54{ 55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 56 struct pipe_resource *texture = transfer->resource; 57 struct pipe_box sbox; 58 59 sbox.x = sbox.y = sbox.z = 0; 60 sbox.width = transfer->box.width; 61 sbox.height = transfer->box.height; 62 /* XXX that might be wrong */ 63 sbox.depth = 1; 64 ctx->resource_copy_region(ctx, texture, transfer->level, 65 transfer->box.x, transfer->box.y, transfer->box.z, 66 rtransfer->staging_texture, 67 0, &sbox); 68} 69 70unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 71 unsigned level, unsigned layer) 72{ 73 unsigned offset = rtex->offset[level]; 74 75 switch (rtex->resource.b.b.b.target) { 76 case PIPE_TEXTURE_3D: 77 case PIPE_TEXTURE_CUBE: 78 default: 79 return offset + layer * rtex->layer_size[level]; 80 } 81} 82 83static unsigned r600_get_block_alignment(struct pipe_screen *screen, 84 enum pipe_format format, 85 unsigned array_mode) 86{ 87 struct r600_screen* rscreen = (struct r600_screen *)screen; 88 unsigned pixsize = util_format_get_blocksize(format); 89 int p_align; 90 91 switch(array_mode) { 92 case V_038000_ARRAY_1D_TILED_THIN1: 93 p_align = MAX2(8, 94 ((rscreen->tiling_info.group_bytes / 8 / pixsize))); 95 break; 96 case V_038000_ARRAY_2D_TILED_THIN1: 97 p_align = MAX2(rscreen->tiling_info.num_banks, 98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) * 99 rscreen->tiling_info.num_banks)) * 8; 100 break; 101 case V_038000_ARRAY_LINEAR_ALIGNED: 102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize); 103 break; 104 case V_038000_ARRAY_LINEAR_GENERAL: 105 default: 106 p_align = rscreen->tiling_info.group_bytes / pixsize; 107 break; 108 } 109 return p_align; 110} 111 112static unsigned r600_get_height_alignment(struct pipe_screen *screen, 113 unsigned array_mode) 114{ 115 struct r600_screen* rscreen = (struct r600_screen *)screen; 116 int h_align; 117 118 switch (array_mode) { 119 case V_038000_ARRAY_2D_TILED_THIN1: 120 h_align = rscreen->tiling_info.num_channels * 8; 121 break; 122 case V_038000_ARRAY_1D_TILED_THIN1: 123 case V_038000_ARRAY_LINEAR_ALIGNED: 124 h_align = 8; 125 break; 126 case V_038000_ARRAY_LINEAR_GENERAL: 127 default: 128 h_align = 1; 129 break; 130 } 131 return h_align; 132} 133 134static unsigned r600_get_base_alignment(struct pipe_screen *screen, 135 enum pipe_format format, 136 unsigned array_mode) 137{ 138 struct r600_screen* rscreen = (struct r600_screen *)screen; 139 unsigned pixsize = util_format_get_blocksize(format); 140 int p_align = r600_get_block_alignment(screen, format, array_mode); 141 int h_align = r600_get_height_alignment(screen, array_mode); 142 int b_align; 143 144 switch (array_mode) { 145 case V_038000_ARRAY_2D_TILED_THIN1: 146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize, 147 p_align * pixsize * h_align); 148 break; 149 case V_038000_ARRAY_1D_TILED_THIN1: 150 case V_038000_ARRAY_LINEAR_ALIGNED: 151 case V_038000_ARRAY_LINEAR_GENERAL: 152 default: 153 b_align = rscreen->tiling_info.group_bytes; 154 break; 155 } 156 return b_align; 157} 158 159static unsigned mip_minify(unsigned size, unsigned level) 160{ 161 unsigned val; 162 val = u_minify(size, level); 163 if (level > 0) 164 val = util_next_power_of_two(val); 165 return val; 166} 167 168static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, 169 struct r600_resource_texture *rtex, 170 unsigned level) 171{ 172 struct pipe_resource *ptex = &rtex->resource.b.b.b; 173 unsigned nblocksx, block_align, width; 174 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 175 176 if (rtex->pitch_override) 177 return rtex->pitch_override / blocksize; 178 179 width = mip_minify(ptex->width0, level); 180 nblocksx = util_format_get_nblocksx(rtex->real_format, width); 181 182 block_align = r600_get_block_alignment(screen, rtex->real_format, 183 rtex->array_mode[level]); 184 nblocksx = align(nblocksx, block_align); 185 return nblocksx; 186} 187 188static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, 189 struct r600_resource_texture *rtex, 190 unsigned level) 191{ 192 struct pipe_resource *ptex = &rtex->resource.b.b.b; 193 unsigned height, tile_height; 194 195 height = mip_minify(ptex->height0, level); 196 height = util_format_get_nblocksy(rtex->real_format, height); 197 tile_height = r600_get_height_alignment(screen, 198 rtex->array_mode[level]); 199 200 /* XXX Hack around an alignment issue. Less tests fail with this. 201 * 202 * The thing is depth-stencil buffers should be tiled, i.e. 203 * the alignment should be >=8. If I make them tiled, stencil starts 204 * working because it no longer overlaps with the depth buffer 205 * in memory, but texturing like drawpix-stencil breaks. */ 206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) 207 tile_height = 8; 208 209 height = align(height, tile_height); 210 return height; 211} 212 213static void r600_texture_set_array_mode(struct pipe_screen *screen, 214 struct r600_resource_texture *rtex, 215 unsigned level, unsigned array_mode) 216{ 217 struct pipe_resource *ptex = &rtex->resource.b.b.b; 218 219 switch (array_mode) { 220 case V_0280A0_ARRAY_LINEAR_GENERAL: 221 case V_0280A0_ARRAY_LINEAR_ALIGNED: 222 case V_0280A0_ARRAY_1D_TILED_THIN1: 223 default: 224 rtex->array_mode[level] = array_mode; 225 break; 226 case V_0280A0_ARRAY_2D_TILED_THIN1: 227 { 228 unsigned w, h, tile_height, tile_width; 229 230 tile_height = r600_get_height_alignment(screen, array_mode); 231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); 232 233 w = mip_minify(ptex->width0, level); 234 h = mip_minify(ptex->height0, level); 235 if (w <= tile_width || h <= tile_height) 236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; 237 else 238 rtex->array_mode[level] = array_mode; 239 } 240 break; 241 } 242} 243 244static void r600_setup_miptree(struct pipe_screen *screen, 245 struct r600_resource_texture *rtex, 246 unsigned array_mode) 247{ 248 struct pipe_resource *ptex = &rtex->resource.b.b.b; 249 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class; 250 unsigned size, layer_size, i, offset; 251 unsigned nblocksx, nblocksy; 252 253 for (i = 0, offset = 0; i <= ptex->last_level; i++) { 254 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 255 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); 256 257 r600_texture_set_array_mode(screen, rtex, i, array_mode); 258 259 nblocksx = r600_texture_get_nblocksx(screen, rtex, i); 260 nblocksy = r600_texture_get_nblocksy(screen, rtex, i); 261 262 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL) 263 layer_size = align(nblocksx, 64) * nblocksy * blocksize; 264 else 265 layer_size = nblocksx * nblocksy * blocksize; 266 267 if (ptex->target == PIPE_TEXTURE_CUBE) { 268 if (chipc >= R700) 269 size = layer_size * 8; 270 else 271 size = layer_size * 6; 272 } 273 else if (ptex->target == PIPE_TEXTURE_3D) 274 size = layer_size * u_minify(ptex->depth0, i); 275 else 276 size = layer_size * ptex->array_size; 277 278 /* align base image and start of miptree */ 279 if ((i == 0) || (i == 1)) 280 offset = align(offset, base_align); 281 rtex->offset[i] = offset; 282 rtex->layer_size[i] = layer_size; 283 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ 284 rtex->pitch_in_bytes[i] = nblocksx * blocksize; 285 286 offset += size; 287 } 288 rtex->size = offset; 289} 290 291/* Figure out whether u_blitter will fallback to a transfer operation. 292 * If so, don't use a staging resource. 293 */ 294static boolean permit_hardware_blit(struct pipe_screen *screen, 295 const struct pipe_resource *res) 296{ 297 unsigned bind; 298 299 if (util_format_is_depth_or_stencil(res->format)) 300 bind = PIPE_BIND_DEPTH_STENCIL; 301 else 302 bind = PIPE_BIND_RENDER_TARGET; 303 304 /* hackaround for S3TC */ 305 if (util_format_is_compressed(res->format)) 306 return TRUE; 307 308 if (!screen->is_format_supported(screen, 309 res->format, 310 res->target, 311 res->nr_samples, 312 bind)) 313 return FALSE; 314 315 if (!screen->is_format_supported(screen, 316 res->format, 317 res->target, 318 res->nr_samples, 319 PIPE_BIND_SAMPLER_VIEW)) 320 return FALSE; 321 322 switch (res->usage) { 323 case PIPE_USAGE_STREAM: 324 case PIPE_USAGE_STAGING: 325 return FALSE; 326 327 default: 328 return TRUE; 329 } 330} 331 332static boolean r600_texture_get_handle(struct pipe_screen* screen, 333 struct pipe_resource *ptex, 334 struct winsys_handle *whandle) 335{ 336 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 337 struct r600_resource *resource = &rtex->resource; 338 struct r600_screen *rscreen = (struct r600_screen*)screen; 339 340 return rscreen->ws->buffer_get_handle(resource->buf, 341 rtex->pitch_in_bytes[0], whandle); 342} 343 344static void r600_texture_destroy(struct pipe_screen *screen, 345 struct pipe_resource *ptex) 346{ 347 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 348 struct r600_resource *resource = &rtex->resource; 349 350 if (rtex->flushed_depth_texture) 351 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 352 353 if (rtex->stencil) 354 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL); 355 356 pb_reference(&resource->buf, NULL); 357 FREE(rtex); 358} 359 360static const struct u_resource_vtbl r600_texture_vtbl = 361{ 362 r600_texture_get_handle, /* get_handle */ 363 r600_texture_destroy, /* resource_destroy */ 364 r600_texture_get_transfer, /* get_transfer */ 365 r600_texture_transfer_destroy, /* transfer_destroy */ 366 r600_texture_transfer_map, /* transfer_map */ 367 u_default_transfer_flush_region,/* transfer_flush_region */ 368 r600_texture_transfer_unmap, /* transfer_unmap */ 369 u_default_transfer_inline_write /* transfer_inline_write */ 370}; 371 372static struct r600_resource_texture * 373r600_texture_create_object(struct pipe_screen *screen, 374 const struct pipe_resource *base, 375 unsigned array_mode, 376 unsigned pitch_in_bytes_override, 377 unsigned max_buffer_size, 378 struct pb_buffer *buf, 379 boolean alloc_bo) 380{ 381 struct r600_resource_texture *rtex; 382 struct r600_resource *resource; 383 struct r600_screen *rscreen = (struct r600_screen*)screen; 384 385 rtex = CALLOC_STRUCT(r600_resource_texture); 386 if (rtex == NULL) 387 return NULL; 388 389 resource = &rtex->resource; 390 resource->b.b.b = *base; 391 resource->b.b.vtbl = &r600_texture_vtbl; 392 pipe_reference_init(&resource->b.b.b.reference, 1); 393 resource->b.b.b.screen = screen; 394 rtex->pitch_override = pitch_in_bytes_override; 395 rtex->real_format = base->format; 396 397 /* We must split depth and stencil into two separate buffers on Evergreen. */ 398 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) && 399 ((struct r600_screen*)screen)->chip_class >= EVERGREEN && 400 util_format_is_depth_and_stencil(base->format)) { 401 struct pipe_resource stencil; 402 unsigned stencil_pitch_override = 0; 403 404 switch (base->format) { 405 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 406 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; 407 break; 408 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 409 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; 410 break; 411 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 412 rtex->real_format = PIPE_FORMAT_Z32_FLOAT; 413 break; 414 default: 415 assert(0); 416 FREE(rtex); 417 return NULL; 418 } 419 420 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ 421 if (pitch_in_bytes_override) { 422 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT || 423 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM); 424 stencil_pitch_override = pitch_in_bytes_override / 4; 425 } 426 427 /* Allocate the stencil buffer. */ 428 stencil = *base; 429 stencil.format = PIPE_FORMAT_S8_UINT; 430 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, 431 stencil_pitch_override, 432 max_buffer_size, NULL, FALSE); 433 if (!rtex->stencil) { 434 FREE(rtex); 435 return NULL; 436 } 437 /* Proceed in creating the depth buffer. */ 438 } 439 440 /* only mark depth textures the HW can hit as depth textures */ 441 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base)) 442 rtex->depth = 1; 443 444 r600_setup_miptree(screen, rtex, array_mode); 445 446 /* If we initialized separate stencil for Evergreen. place it after depth. */ 447 if (rtex->stencil) { 448 unsigned stencil_align, stencil_offset; 449 450 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); 451 stencil_offset = align(rtex->size, stencil_align); 452 453 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++) 454 rtex->stencil->offset[i] += stencil_offset; 455 456 rtex->size = stencil_offset + rtex->stencil->size; 457 } 458 459 /* Now create the backing buffer. */ 460 if (!buf && alloc_bo) { 461 struct pipe_resource *ptex = &rtex->resource.b.b.b; 462 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); 463 464 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 465 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); 466 FREE(rtex); 467 return NULL; 468 } 469 } else if (buf) { 470 resource->buf = buf; 471 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 472 } 473 474 if (rtex->stencil) { 475 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf); 476 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf; 477 } 478 return rtex; 479} 480 481DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE); 482 483struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 484 const struct pipe_resource *templ) 485{ 486 struct r600_screen *rscreen = (struct r600_screen*)screen; 487 unsigned array_mode = 0; 488 489 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && 490 !(templ->bind & PIPE_BIND_SCANOUT)) { 491 if (util_format_is_compressed(templ->format)) { 492 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 493 } 494 else if (debug_get_option_tiling_enabled() && 495 rscreen->info.drm_minor >= 9 && 496 permit_hardware_blit(screen, templ)) { 497 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 498 } 499 } 500 501 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 502 0, 0, NULL, TRUE); 503} 504 505static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 506 struct pipe_resource *texture, 507 const struct pipe_surface *surf_tmpl) 508{ 509 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 510 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 511 unsigned level = surf_tmpl->u.tex.level; 512 513 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 514 if (surface == NULL) 515 return NULL; 516 /* XXX no offset */ 517/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ 518 pipe_reference_init(&surface->base.reference, 1); 519 pipe_resource_reference(&surface->base.texture, texture); 520 surface->base.context = pipe; 521 surface->base.format = surf_tmpl->format; 522 surface->base.width = mip_minify(texture->width0, level); 523 surface->base.height = mip_minify(texture->height0, level); 524 surface->base.usage = surf_tmpl->usage; 525 surface->base.texture = texture; 526 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 527 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 528 surface->base.u.tex.level = level; 529 530 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, 531 rtex, level); 532 return &surface->base; 533} 534 535static void r600_surface_destroy(struct pipe_context *pipe, 536 struct pipe_surface *surface) 537{ 538 pipe_resource_reference(&surface->texture, NULL); 539 FREE(surface); 540} 541 542struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 543 const struct pipe_resource *templ, 544 struct winsys_handle *whandle) 545{ 546 struct r600_screen *rscreen = (struct r600_screen*)screen; 547 struct pb_buffer *buf = NULL; 548 unsigned stride = 0; 549 unsigned array_mode = 0; 550 enum radeon_bo_layout micro, macro; 551 552 /* Support only 2D textures without mipmaps */ 553 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 554 templ->depth0 != 1 || templ->last_level != 0) 555 return NULL; 556 557 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 558 if (!buf) 559 return NULL; 560 561 rscreen->ws->buffer_get_tiling(buf, µ, ¯o); 562 563 if (macro == RADEON_LAYOUT_TILED) 564 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 565 else if (micro == RADEON_LAYOUT_TILED) 566 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 567 else 568 array_mode = 0; 569 570 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 571 stride, 0, buf, FALSE); 572} 573 574int r600_texture_depth_flush(struct pipe_context *ctx, 575 struct pipe_resource *texture, boolean just_create) 576{ 577 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 578 struct pipe_resource resource; 579 580 if (rtex->flushed_depth_texture) 581 goto out; 582 583 resource.target = texture->target; 584 resource.format = texture->format; 585 resource.width0 = texture->width0; 586 resource.height0 = texture->height0; 587 resource.depth0 = texture->depth0; 588 resource.array_size = texture->array_size; 589 resource.last_level = texture->last_level; 590 resource.nr_samples = texture->nr_samples; 591 resource.usage = PIPE_USAGE_DYNAMIC; 592 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL; 593 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags; 594 595 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 596 if (rtex->flushed_depth_texture == NULL) { 597 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 598 return -ENOMEM; 599 } 600 601 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE; 602out: 603 if (just_create) 604 return 0; 605 606 /* XXX: only do this if the depth texture has actually changed: 607 */ 608 r600_blit_uncompress_depth(ctx, rtex); 609 return 0; 610} 611 612/* Needs adjustment for pixelformat: 613 */ 614static INLINE unsigned u_box_volume( const struct pipe_box *box ) 615{ 616 return box->width * box->depth * box->height; 617}; 618 619struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 620 struct pipe_resource *texture, 621 unsigned level, 622 unsigned usage, 623 const struct pipe_box *box) 624{ 625 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 626 struct pipe_resource resource; 627 struct r600_transfer *trans; 628 int r; 629 boolean use_staging_texture = FALSE; 630 631 /* We cannot map a tiled texture directly because the data is 632 * in a different order, therefore we do detiling using a blit. 633 * 634 * Also, use a temporary in GTT memory for read transfers, as 635 * the CPU is much happier reading out of cached system memory 636 * than uncached VRAM. 637 */ 638 if (R600_TEX_IS_TILED(rtex, level)) 639 use_staging_texture = TRUE; 640 641 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 642 use_staging_texture = TRUE; 643 644 /* XXX: Use a staging texture for uploads if the underlying BO 645 * is busy. No interface for checking that currently? so do 646 * it eagerly whenever the transfer doesn't require a readback 647 * and might block. 648 */ 649 if ((usage & PIPE_TRANSFER_WRITE) && 650 !(usage & (PIPE_TRANSFER_READ | 651 PIPE_TRANSFER_DONTBLOCK | 652 PIPE_TRANSFER_UNSYNCHRONIZED))) 653 use_staging_texture = TRUE; 654 655 if (!permit_hardware_blit(ctx->screen, texture) || 656 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) 657 use_staging_texture = FALSE; 658 659 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) 660 return NULL; 661 662 trans = CALLOC_STRUCT(r600_transfer); 663 if (trans == NULL) 664 return NULL; 665 pipe_resource_reference(&trans->transfer.resource, texture); 666 trans->transfer.level = level; 667 trans->transfer.usage = usage; 668 trans->transfer.box = *box; 669 if (rtex->depth) { 670 /* XXX: only readback the rectangle which is being mapped? 671 */ 672 /* XXX: when discard is true, no need to read back from depth texture 673 */ 674 r = r600_texture_depth_flush(ctx, texture, FALSE); 675 if (r < 0) { 676 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 677 pipe_resource_reference(&trans->transfer.resource, NULL); 678 FREE(trans); 679 return NULL; 680 } 681 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level]; 682 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); 683 return &trans->transfer; 684 } else if (use_staging_texture) { 685 resource.target = PIPE_TEXTURE_2D; 686 resource.format = texture->format; 687 resource.width0 = box->width; 688 resource.height0 = box->height; 689 resource.depth0 = 1; 690 resource.array_size = 1; 691 resource.last_level = 0; 692 resource.nr_samples = 0; 693 resource.usage = PIPE_USAGE_STAGING; 694 resource.bind = 0; 695 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 696 /* For texture reading, the temporary (detiled) texture is used as 697 * a render target when blitting from a tiled texture. */ 698 if (usage & PIPE_TRANSFER_READ) { 699 resource.bind |= PIPE_BIND_RENDER_TARGET; 700 } 701 /* For texture writing, the temporary texture is used as a sampler 702 * when blitting into a tiled texture. */ 703 if (usage & PIPE_TRANSFER_WRITE) { 704 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 705 } 706 /* Create the temporary texture. */ 707 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource); 708 if (trans->staging_texture == NULL) { 709 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 710 pipe_resource_reference(&trans->transfer.resource, NULL); 711 FREE(trans); 712 return NULL; 713 } 714 715 trans->transfer.stride = 716 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0]; 717 if (usage & PIPE_TRANSFER_READ) { 718 r600_copy_to_staging_texture(ctx, trans); 719 /* Always referenced in the blit. */ 720 r600_flush(ctx, NULL, 0); 721 } 722 return &trans->transfer; 723 } 724 trans->transfer.stride = rtex->pitch_in_bytes[level]; 725 trans->transfer.layer_stride = rtex->layer_size[level]; 726 trans->offset = r600_texture_get_offset(rtex, level, box->z); 727 return &trans->transfer; 728} 729 730void r600_texture_transfer_destroy(struct pipe_context *ctx, 731 struct pipe_transfer *transfer) 732{ 733 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 734 struct pipe_resource *texture = transfer->resource; 735 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 736 737 if (rtransfer->staging_texture) { 738 if (transfer->usage & PIPE_TRANSFER_WRITE) { 739 r600_copy_from_staging_texture(ctx, rtransfer); 740 } 741 pipe_resource_reference(&rtransfer->staging_texture, NULL); 742 } 743 744 if (rtex->depth && !rtex->is_flushing_texture) { 745 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) 746 r600_blit_push_depth(ctx, rtex); 747 } 748 749 pipe_resource_reference(&transfer->resource, NULL); 750 FREE(transfer); 751} 752 753void* r600_texture_transfer_map(struct pipe_context *ctx, 754 struct pipe_transfer* transfer) 755{ 756 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 757 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 758 struct pb_buffer *buf; 759 enum pipe_format format = transfer->resource->format; 760 unsigned offset = 0; 761 char *map; 762 763 if (rtransfer->staging_texture) { 764 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf; 765 } else { 766 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 767 768 if (rtex->flushed_depth_texture) 769 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 770 else 771 buf = ((struct r600_resource *)transfer->resource)->buf; 772 773 offset = rtransfer->offset + 774 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 775 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 776 } 777 778 if (!(map = rctx->ws->buffer_map(buf, rctx->ctx.cs, transfer->usage))) { 779 return NULL; 780 } 781 782 return map + offset; 783} 784 785void r600_texture_transfer_unmap(struct pipe_context *ctx, 786 struct pipe_transfer* transfer) 787{ 788 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 789 struct r600_pipe_context *rctx = (struct r600_pipe_context*)ctx; 790 struct pb_buffer *buf; 791 792 if (rtransfer->staging_texture) { 793 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf; 794 } else { 795 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 796 797 if (rtex->flushed_depth_texture) { 798 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 799 } else { 800 buf = ((struct r600_resource *)transfer->resource)->buf; 801 } 802 } 803 rctx->ws->buffer_unmap(buf); 804} 805 806void r600_init_surface_functions(struct r600_pipe_context *r600) 807{ 808 r600->context.create_surface = r600_create_surface; 809 r600->context.surface_destroy = r600_surface_destroy; 810} 811 812static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 813 const unsigned char *swizzle_view) 814{ 815 unsigned i; 816 unsigned char swizzle[4]; 817 unsigned result = 0; 818 const uint32_t swizzle_shift[4] = { 819 16, 19, 22, 25, 820 }; 821 const uint32_t swizzle_bit[4] = { 822 0, 1, 2, 3, 823 }; 824 825 if (swizzle_view) { 826 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 827 } else { 828 memcpy(swizzle, swizzle_format, 4); 829 } 830 831 /* Get swizzle. */ 832 for (i = 0; i < 4; i++) { 833 switch (swizzle[i]) { 834 case UTIL_FORMAT_SWIZZLE_Y: 835 result |= swizzle_bit[1] << swizzle_shift[i]; 836 break; 837 case UTIL_FORMAT_SWIZZLE_Z: 838 result |= swizzle_bit[2] << swizzle_shift[i]; 839 break; 840 case UTIL_FORMAT_SWIZZLE_W: 841 result |= swizzle_bit[3] << swizzle_shift[i]; 842 break; 843 case UTIL_FORMAT_SWIZZLE_0: 844 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 845 break; 846 case UTIL_FORMAT_SWIZZLE_1: 847 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 848 break; 849 default: /* UTIL_FORMAT_SWIZZLE_X */ 850 result |= swizzle_bit[0] << swizzle_shift[i]; 851 } 852 } 853 return result; 854} 855 856/* texture format translate */ 857uint32_t r600_translate_texformat(struct pipe_screen *screen, 858 enum pipe_format format, 859 const unsigned char *swizzle_view, 860 uint32_t *word4_p, uint32_t *yuv_format_p) 861{ 862 uint32_t result = 0, word4 = 0, yuv_format = 0; 863 const struct util_format_description *desc; 864 boolean uniform = TRUE; 865 static int r600_enable_s3tc = -1; 866 867 int i; 868 const uint32_t sign_bit[4] = { 869 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 870 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 871 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 872 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 873 }; 874 desc = util_format_description(format); 875 876 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 877 878 /* Colorspace (return non-RGB formats directly). */ 879 switch (desc->colorspace) { 880 /* Depth stencil formats */ 881 case UTIL_FORMAT_COLORSPACE_ZS: 882 switch (format) { 883 case PIPE_FORMAT_Z16_UNORM: 884 result = FMT_16; 885 goto out_word4; 886 case PIPE_FORMAT_X24S8_UINT: 887 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 888 case PIPE_FORMAT_Z24X8_UNORM: 889 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 890 result = FMT_8_24; 891 goto out_word4; 892 case PIPE_FORMAT_S8X24_UINT: 893 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 894 case PIPE_FORMAT_X8Z24_UNORM: 895 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 896 result = FMT_24_8; 897 goto out_word4; 898 case PIPE_FORMAT_S8_UINT: 899 result = FMT_8; 900 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 901 goto out_word4; 902 case PIPE_FORMAT_Z32_FLOAT: 903 result = FMT_32_FLOAT; 904 goto out_word4; 905 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 906 result = FMT_X24_8_32_FLOAT; 907 goto out_word4; 908 default: 909 goto out_unknown; 910 } 911 912 case UTIL_FORMAT_COLORSPACE_YUV: 913 yuv_format |= (1 << 30); 914 switch (format) { 915 case PIPE_FORMAT_UYVY: 916 case PIPE_FORMAT_YUYV: 917 default: 918 break; 919 } 920 goto out_unknown; /* TODO */ 921 922 case UTIL_FORMAT_COLORSPACE_SRGB: 923 word4 |= S_038010_FORCE_DEGAMMA(1); 924 break; 925 926 default: 927 break; 928 } 929 930 if (r600_enable_s3tc == -1) { 931 struct r600_screen *rscreen = (struct r600_screen *)screen; 932 if (rscreen->info.drm_minor >= 9) 933 r600_enable_s3tc = 1; 934 else 935 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 936 } 937 938 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 939 if (!r600_enable_s3tc) 940 goto out_unknown; 941 942 switch (format) { 943 case PIPE_FORMAT_RGTC1_SNORM: 944 case PIPE_FORMAT_LATC1_SNORM: 945 word4 |= sign_bit[0]; 946 case PIPE_FORMAT_RGTC1_UNORM: 947 case PIPE_FORMAT_LATC1_UNORM: 948 result = FMT_BC4; 949 goto out_word4; 950 case PIPE_FORMAT_RGTC2_SNORM: 951 case PIPE_FORMAT_LATC2_SNORM: 952 word4 |= sign_bit[0] | sign_bit[1]; 953 case PIPE_FORMAT_RGTC2_UNORM: 954 case PIPE_FORMAT_LATC2_UNORM: 955 result = FMT_BC5; 956 goto out_word4; 957 default: 958 goto out_unknown; 959 } 960 } 961 962 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 963 964 if (!r600_enable_s3tc) 965 goto out_unknown; 966 967 if (!util_format_s3tc_enabled) { 968 goto out_unknown; 969 } 970 971 switch (format) { 972 case PIPE_FORMAT_DXT1_RGB: 973 case PIPE_FORMAT_DXT1_RGBA: 974 case PIPE_FORMAT_DXT1_SRGB: 975 case PIPE_FORMAT_DXT1_SRGBA: 976 result = FMT_BC1; 977 goto out_word4; 978 case PIPE_FORMAT_DXT3_RGBA: 979 case PIPE_FORMAT_DXT3_SRGBA: 980 result = FMT_BC2; 981 goto out_word4; 982 case PIPE_FORMAT_DXT5_RGBA: 983 case PIPE_FORMAT_DXT5_SRGBA: 984 result = FMT_BC3; 985 goto out_word4; 986 default: 987 goto out_unknown; 988 } 989 } 990 991 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 992 result = FMT_5_9_9_9_SHAREDEXP; 993 goto out_word4; 994 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 995 result = FMT_10_11_11_FLOAT; 996 goto out_word4; 997 } 998 999 1000 for (i = 0; i < desc->nr_channels; i++) { 1001 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1002 word4 |= sign_bit[i]; 1003 } 1004 } 1005 1006 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1007 1008 /* See whether the components are of the same size. */ 1009 for (i = 1; i < desc->nr_channels; i++) { 1010 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1011 } 1012 1013 /* Non-uniform formats. */ 1014 if (!uniform) { 1015 switch(desc->nr_channels) { 1016 case 3: 1017 if (desc->channel[0].size == 5 && 1018 desc->channel[1].size == 6 && 1019 desc->channel[2].size == 5) { 1020 result = FMT_5_6_5; 1021 goto out_word4; 1022 } 1023 goto out_unknown; 1024 case 4: 1025 if (desc->channel[0].size == 5 && 1026 desc->channel[1].size == 5 && 1027 desc->channel[2].size == 5 && 1028 desc->channel[3].size == 1) { 1029 result = FMT_1_5_5_5; 1030 goto out_word4; 1031 } 1032 if (desc->channel[0].size == 10 && 1033 desc->channel[1].size == 10 && 1034 desc->channel[2].size == 10 && 1035 desc->channel[3].size == 2) { 1036 result = FMT_2_10_10_10; 1037 goto out_word4; 1038 } 1039 goto out_unknown; 1040 } 1041 goto out_unknown; 1042 } 1043 1044 /* Find the first non-VOID channel. */ 1045 for (i = 0; i < 4; i++) { 1046 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1047 break; 1048 } 1049 } 1050 1051 if (i == 4) 1052 goto out_unknown; 1053 1054 /* uniform formats */ 1055 switch (desc->channel[i].type) { 1056 case UTIL_FORMAT_TYPE_UNSIGNED: 1057 case UTIL_FORMAT_TYPE_SIGNED: 1058#if 0 1059 if (!desc->channel[i].normalized && 1060 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 1061 goto out_unknown; 1062 } 1063#endif 1064 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1065 desc->channel[i].pure_integer) 1066 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1067 1068 switch (desc->channel[i].size) { 1069 case 4: 1070 switch (desc->nr_channels) { 1071 case 2: 1072 result = FMT_4_4; 1073 goto out_word4; 1074 case 4: 1075 result = FMT_4_4_4_4; 1076 goto out_word4; 1077 } 1078 goto out_unknown; 1079 case 8: 1080 switch (desc->nr_channels) { 1081 case 1: 1082 result = FMT_8; 1083 goto out_word4; 1084 case 2: 1085 result = FMT_8_8; 1086 goto out_word4; 1087 case 4: 1088 result = FMT_8_8_8_8; 1089 goto out_word4; 1090 } 1091 goto out_unknown; 1092 case 16: 1093 switch (desc->nr_channels) { 1094 case 1: 1095 result = FMT_16; 1096 goto out_word4; 1097 case 2: 1098 result = FMT_16_16; 1099 goto out_word4; 1100 case 4: 1101 result = FMT_16_16_16_16; 1102 goto out_word4; 1103 } 1104 goto out_unknown; 1105 case 32: 1106 switch (desc->nr_channels) { 1107 case 1: 1108 result = FMT_32; 1109 goto out_word4; 1110 case 2: 1111 result = FMT_32_32; 1112 goto out_word4; 1113 case 4: 1114 result = FMT_32_32_32_32; 1115 goto out_word4; 1116 } 1117 } 1118 goto out_unknown; 1119 1120 case UTIL_FORMAT_TYPE_FLOAT: 1121 switch (desc->channel[i].size) { 1122 case 16: 1123 switch (desc->nr_channels) { 1124 case 1: 1125 result = FMT_16_FLOAT; 1126 goto out_word4; 1127 case 2: 1128 result = FMT_16_16_FLOAT; 1129 goto out_word4; 1130 case 4: 1131 result = FMT_16_16_16_16_FLOAT; 1132 goto out_word4; 1133 } 1134 goto out_unknown; 1135 case 32: 1136 switch (desc->nr_channels) { 1137 case 1: 1138 result = FMT_32_FLOAT; 1139 goto out_word4; 1140 case 2: 1141 result = FMT_32_32_FLOAT; 1142 goto out_word4; 1143 case 4: 1144 result = FMT_32_32_32_32_FLOAT; 1145 goto out_word4; 1146 } 1147 } 1148 goto out_unknown; 1149 } 1150 1151out_word4: 1152 if (word4_p) 1153 *word4_p = word4; 1154 if (yuv_format_p) 1155 *yuv_format_p = yuv_format; 1156 return result; 1157out_unknown: 1158 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1159 return ~0; 1160} 1161