r600_texture.c revision e4340c1908a6a3b09e1a15d5195f6da7d00494d0
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include <errno.h> 28#include "pipe/p_screen.h" 29#include "util/u_format.h" 30#include "util/u_format_s3tc.h" 31#include "util/u_math.h" 32#include "util/u_inlines.h" 33#include "util/u_memory.h" 34#include "pipebuffer/pb_buffer.h" 35#include "r600_pipe.h" 36#include "r600_resource.h" 37#include "r600d.h" 38#include "r600_formats.h" 39 40/* Copy from a full GPU texture to a transfer's staging one. */ 41static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 42{ 43 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 44 struct pipe_resource *texture = transfer->resource; 45 46 ctx->resource_copy_region(ctx, rtransfer->staging_texture, 47 0, 0, 0, 0, texture, transfer->level, 48 &transfer->box); 49} 50 51 52/* Copy from a transfer's staging texture to a full GPU one. */ 53static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 54{ 55 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 56 struct pipe_resource *texture = transfer->resource; 57 struct pipe_box sbox; 58 59 sbox.x = sbox.y = sbox.z = 0; 60 sbox.width = transfer->box.width; 61 sbox.height = transfer->box.height; 62 /* XXX that might be wrong */ 63 sbox.depth = 1; 64 ctx->resource_copy_region(ctx, texture, transfer->level, 65 transfer->box.x, transfer->box.y, transfer->box.z, 66 rtransfer->staging_texture, 67 0, &sbox); 68} 69 70unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 71 unsigned level, unsigned layer) 72{ 73 unsigned offset = rtex->offset[level]; 74 75 switch (rtex->resource.b.b.b.target) { 76 case PIPE_TEXTURE_3D: 77 case PIPE_TEXTURE_CUBE: 78 default: 79 return offset + layer * rtex->layer_size[level]; 80 } 81} 82 83static unsigned r600_get_block_alignment(struct pipe_screen *screen, 84 enum pipe_format format, 85 unsigned array_mode) 86{ 87 struct r600_screen* rscreen = (struct r600_screen *)screen; 88 unsigned pixsize = util_format_get_blocksize(format); 89 int p_align; 90 91 switch(array_mode) { 92 case V_038000_ARRAY_1D_TILED_THIN1: 93 p_align = MAX2(8, 94 ((rscreen->tiling_info.group_bytes / 8 / pixsize))); 95 break; 96 case V_038000_ARRAY_2D_TILED_THIN1: 97 p_align = MAX2(rscreen->tiling_info.num_banks, 98 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) * 99 rscreen->tiling_info.num_banks)) * 8; 100 break; 101 case V_038000_ARRAY_LINEAR_ALIGNED: 102 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize); 103 break; 104 case V_038000_ARRAY_LINEAR_GENERAL: 105 default: 106 p_align = rscreen->tiling_info.group_bytes / pixsize; 107 break; 108 } 109 return p_align; 110} 111 112static unsigned r600_get_height_alignment(struct pipe_screen *screen, 113 unsigned array_mode) 114{ 115 struct r600_screen* rscreen = (struct r600_screen *)screen; 116 int h_align; 117 118 switch (array_mode) { 119 case V_038000_ARRAY_2D_TILED_THIN1: 120 h_align = rscreen->tiling_info.num_channels * 8; 121 break; 122 case V_038000_ARRAY_1D_TILED_THIN1: 123 case V_038000_ARRAY_LINEAR_ALIGNED: 124 h_align = 8; 125 break; 126 case V_038000_ARRAY_LINEAR_GENERAL: 127 default: 128 h_align = 1; 129 break; 130 } 131 return h_align; 132} 133 134static unsigned r600_get_base_alignment(struct pipe_screen *screen, 135 enum pipe_format format, 136 unsigned array_mode) 137{ 138 struct r600_screen* rscreen = (struct r600_screen *)screen; 139 unsigned pixsize = util_format_get_blocksize(format); 140 int p_align = r600_get_block_alignment(screen, format, array_mode); 141 int h_align = r600_get_height_alignment(screen, array_mode); 142 int b_align; 143 144 switch (array_mode) { 145 case V_038000_ARRAY_2D_TILED_THIN1: 146 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize, 147 p_align * pixsize * h_align); 148 break; 149 case V_038000_ARRAY_1D_TILED_THIN1: 150 case V_038000_ARRAY_LINEAR_ALIGNED: 151 case V_038000_ARRAY_LINEAR_GENERAL: 152 default: 153 b_align = rscreen->tiling_info.group_bytes; 154 break; 155 } 156 return b_align; 157} 158 159static unsigned mip_minify(unsigned size, unsigned level) 160{ 161 unsigned val; 162 val = u_minify(size, level); 163 if (level > 0) 164 val = util_next_power_of_two(val); 165 return val; 166} 167 168static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, 169 struct r600_resource_texture *rtex, 170 unsigned level) 171{ 172 struct pipe_resource *ptex = &rtex->resource.b.b.b; 173 unsigned nblocksx, block_align, width; 174 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 175 176 if (rtex->pitch_override) 177 return rtex->pitch_override / blocksize; 178 179 width = mip_minify(ptex->width0, level); 180 nblocksx = util_format_get_nblocksx(rtex->real_format, width); 181 182 block_align = r600_get_block_alignment(screen, rtex->real_format, 183 rtex->array_mode[level]); 184 nblocksx = align(nblocksx, block_align); 185 return nblocksx; 186} 187 188static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, 189 struct r600_resource_texture *rtex, 190 unsigned level) 191{ 192 struct pipe_resource *ptex = &rtex->resource.b.b.b; 193 unsigned height, tile_height; 194 195 height = mip_minify(ptex->height0, level); 196 height = util_format_get_nblocksy(rtex->real_format, height); 197 tile_height = r600_get_height_alignment(screen, 198 rtex->array_mode[level]); 199 200 /* XXX Hack around an alignment issue. Less tests fail with this. 201 * 202 * The thing is depth-stencil buffers should be tiled, i.e. 203 * the alignment should be >=8. If I make them tiled, stencil starts 204 * working because it no longer overlaps with the depth buffer 205 * in memory, but texturing like drawpix-stencil breaks. */ 206 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) 207 tile_height = 8; 208 209 height = align(height, tile_height); 210 return height; 211} 212 213static void r600_texture_set_array_mode(struct pipe_screen *screen, 214 struct r600_resource_texture *rtex, 215 unsigned level, unsigned array_mode) 216{ 217 struct pipe_resource *ptex = &rtex->resource.b.b.b; 218 219 switch (array_mode) { 220 case V_0280A0_ARRAY_LINEAR_GENERAL: 221 case V_0280A0_ARRAY_LINEAR_ALIGNED: 222 case V_0280A0_ARRAY_1D_TILED_THIN1: 223 default: 224 rtex->array_mode[level] = array_mode; 225 break; 226 case V_0280A0_ARRAY_2D_TILED_THIN1: 227 { 228 unsigned w, h, tile_height, tile_width; 229 230 tile_height = r600_get_height_alignment(screen, array_mode); 231 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); 232 233 w = mip_minify(ptex->width0, level); 234 h = mip_minify(ptex->height0, level); 235 if (w <= tile_width || h <= tile_height) 236 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; 237 else 238 rtex->array_mode[level] = array_mode; 239 } 240 break; 241 } 242} 243 244static void r600_setup_miptree(struct pipe_screen *screen, 245 struct r600_resource_texture *rtex, 246 unsigned array_mode) 247{ 248 struct pipe_resource *ptex = &rtex->resource.b.b.b; 249 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class; 250 unsigned size, layer_size, i, offset; 251 unsigned nblocksx, nblocksy; 252 253 for (i = 0, offset = 0; i <= ptex->last_level; i++) { 254 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 255 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); 256 257 r600_texture_set_array_mode(screen, rtex, i, array_mode); 258 259 nblocksx = r600_texture_get_nblocksx(screen, rtex, i); 260 nblocksy = r600_texture_get_nblocksy(screen, rtex, i); 261 262 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL) 263 layer_size = align(nblocksx, 64) * nblocksy * blocksize; 264 else 265 layer_size = nblocksx * nblocksy * blocksize; 266 267 if (ptex->target == PIPE_TEXTURE_CUBE) { 268 if (chipc >= R700) 269 size = layer_size * 8; 270 else 271 size = layer_size * 6; 272 } 273 else if (ptex->target == PIPE_TEXTURE_3D) 274 size = layer_size * u_minify(ptex->depth0, i); 275 else 276 size = layer_size * ptex->array_size; 277 278 /* align base image and start of miptree */ 279 if ((i == 0) || (i == 1)) 280 offset = align(offset, base_align); 281 rtex->offset[i] = offset; 282 rtex->layer_size[i] = layer_size; 283 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ 284 rtex->pitch_in_bytes[i] = nblocksx * blocksize; 285 286 offset += size; 287 } 288 rtex->size = offset; 289} 290 291/* Figure out whether u_blitter will fallback to a transfer operation. 292 * If so, don't use a staging resource. 293 */ 294static boolean permit_hardware_blit(struct pipe_screen *screen, 295 const struct pipe_resource *res) 296{ 297 unsigned bind; 298 299 if (util_format_is_depth_or_stencil(res->format)) 300 bind = PIPE_BIND_DEPTH_STENCIL; 301 else 302 bind = PIPE_BIND_RENDER_TARGET; 303 304 /* hackaround for S3TC */ 305 if (util_format_is_compressed(res->format)) 306 return TRUE; 307 308 if (!screen->is_format_supported(screen, 309 res->format, 310 res->target, 311 res->nr_samples, 312 bind)) 313 return FALSE; 314 315 if (!screen->is_format_supported(screen, 316 res->format, 317 res->target, 318 res->nr_samples, 319 PIPE_BIND_SAMPLER_VIEW)) 320 return FALSE; 321 322 switch (res->usage) { 323 case PIPE_USAGE_STREAM: 324 case PIPE_USAGE_STAGING: 325 return FALSE; 326 327 default: 328 return TRUE; 329 } 330} 331 332static boolean r600_texture_get_handle(struct pipe_screen* screen, 333 struct pipe_resource *ptex, 334 struct winsys_handle *whandle) 335{ 336 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 337 struct r600_resource *resource = &rtex->resource; 338 struct r600_screen *rscreen = (struct r600_screen*)screen; 339 340 return rscreen->ws->buffer_get_handle(resource->buf, 341 rtex->pitch_in_bytes[0], whandle); 342} 343 344static void r600_texture_destroy(struct pipe_screen *screen, 345 struct pipe_resource *ptex) 346{ 347 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 348 struct r600_resource *resource = &rtex->resource; 349 350 if (rtex->flushed_depth_texture) 351 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 352 353 if (rtex->stencil) 354 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL); 355 356 pb_reference(&resource->buf, NULL); 357 FREE(rtex); 358} 359 360static const struct u_resource_vtbl r600_texture_vtbl = 361{ 362 r600_texture_get_handle, /* get_handle */ 363 r600_texture_destroy, /* resource_destroy */ 364 r600_texture_get_transfer, /* get_transfer */ 365 r600_texture_transfer_destroy, /* transfer_destroy */ 366 r600_texture_transfer_map, /* transfer_map */ 367 u_default_transfer_flush_region,/* transfer_flush_region */ 368 r600_texture_transfer_unmap, /* transfer_unmap */ 369 u_default_transfer_inline_write /* transfer_inline_write */ 370}; 371 372static struct r600_resource_texture * 373r600_texture_create_object(struct pipe_screen *screen, 374 const struct pipe_resource *base, 375 unsigned array_mode, 376 unsigned pitch_in_bytes_override, 377 unsigned max_buffer_size, 378 struct pb_buffer *buf, 379 boolean alloc_bo) 380{ 381 struct r600_resource_texture *rtex; 382 struct r600_resource *resource; 383 struct r600_screen *rscreen = (struct r600_screen*)screen; 384 385 rtex = CALLOC_STRUCT(r600_resource_texture); 386 if (rtex == NULL) 387 return NULL; 388 389 resource = &rtex->resource; 390 resource->b.b.b = *base; 391 resource->b.b.vtbl = &r600_texture_vtbl; 392 pipe_reference_init(&resource->b.b.b.reference, 1); 393 resource->b.b.b.screen = screen; 394 rtex->pitch_override = pitch_in_bytes_override; 395 rtex->real_format = base->format; 396 397 /* We must split depth and stencil into two separate buffers on Evergreen. */ 398 if (!(base->flags & R600_RESOURCE_FLAG_TRANSFER) && 399 ((struct r600_screen*)screen)->chip_class >= EVERGREEN && 400 util_format_is_depth_and_stencil(base->format)) { 401 struct pipe_resource stencil; 402 unsigned stencil_pitch_override = 0; 403 404 switch (base->format) { 405 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 406 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; 407 break; 408 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 409 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; 410 break; 411 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 412 rtex->real_format = PIPE_FORMAT_Z32_FLOAT; 413 break; 414 default: 415 assert(0); 416 FREE(rtex); 417 return NULL; 418 } 419 420 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ 421 if (pitch_in_bytes_override) { 422 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT || 423 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM); 424 stencil_pitch_override = pitch_in_bytes_override / 4; 425 } 426 427 /* Allocate the stencil buffer. */ 428 stencil = *base; 429 stencil.format = PIPE_FORMAT_S8_UINT; 430 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, 431 stencil_pitch_override, 432 max_buffer_size, NULL, FALSE); 433 if (!rtex->stencil) { 434 FREE(rtex); 435 return NULL; 436 } 437 /* Proceed in creating the depth buffer. */ 438 } 439 440 /* only mark depth textures the HW can hit as depth textures */ 441 if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base)) 442 rtex->depth = 1; 443 444 r600_setup_miptree(screen, rtex, array_mode); 445 446 /* If we initialized separate stencil for Evergreen. place it after depth. */ 447 if (rtex->stencil) { 448 unsigned stencil_align, stencil_offset; 449 450 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); 451 stencil_offset = align(rtex->size, stencil_align); 452 453 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.b.last_level; i++) 454 rtex->stencil->offset[i] += stencil_offset; 455 456 rtex->size = stencil_offset + rtex->stencil->size; 457 } 458 459 /* Now create the backing buffer. */ 460 if (!buf && alloc_bo) { 461 struct pipe_resource *ptex = &rtex->resource.b.b.b; 462 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); 463 464 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 465 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); 466 FREE(rtex); 467 return NULL; 468 } 469 } else if (buf) { 470 resource->buf = buf; 471 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 472 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 473 } 474 475 if (rtex->stencil) { 476 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf); 477 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf; 478 rtex->stencil->resource.domains = rtex->resource.domains; 479 } 480 return rtex; 481} 482 483DEBUG_GET_ONCE_BOOL_OPTION(tiling_enabled, "R600_TILING", FALSE); 484 485struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 486 const struct pipe_resource *templ) 487{ 488 struct r600_screen *rscreen = (struct r600_screen*)screen; 489 unsigned array_mode = 0; 490 491 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && 492 !(templ->bind & PIPE_BIND_SCANOUT)) { 493 if (util_format_is_compressed(templ->format)) { 494 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 495 } 496 else if (debug_get_option_tiling_enabled() && 497 rscreen->info.drm_minor >= 9 && 498 permit_hardware_blit(screen, templ)) { 499 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 500 } 501 } 502 503 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 504 0, 0, NULL, TRUE); 505} 506 507static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 508 struct pipe_resource *texture, 509 const struct pipe_surface *surf_tmpl) 510{ 511 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 512 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 513 unsigned level = surf_tmpl->u.tex.level; 514 515 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 516 if (surface == NULL) 517 return NULL; 518 /* XXX no offset */ 519/* offset = r600_texture_get_offset(rtex, level, surf_tmpl->u.tex.first_layer);*/ 520 pipe_reference_init(&surface->base.reference, 1); 521 pipe_resource_reference(&surface->base.texture, texture); 522 surface->base.context = pipe; 523 surface->base.format = surf_tmpl->format; 524 surface->base.width = mip_minify(texture->width0, level); 525 surface->base.height = mip_minify(texture->height0, level); 526 surface->base.usage = surf_tmpl->usage; 527 surface->base.texture = texture; 528 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 529 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 530 surface->base.u.tex.level = level; 531 532 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, 533 rtex, level); 534 return &surface->base; 535} 536 537static void r600_surface_destroy(struct pipe_context *pipe, 538 struct pipe_surface *surface) 539{ 540 pipe_resource_reference(&surface->texture, NULL); 541 FREE(surface); 542} 543 544struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 545 const struct pipe_resource *templ, 546 struct winsys_handle *whandle) 547{ 548 struct r600_screen *rscreen = (struct r600_screen*)screen; 549 struct pb_buffer *buf = NULL; 550 unsigned stride = 0; 551 unsigned array_mode = 0; 552 enum radeon_bo_layout micro, macro; 553 554 /* Support only 2D textures without mipmaps */ 555 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 556 templ->depth0 != 1 || templ->last_level != 0) 557 return NULL; 558 559 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 560 if (!buf) 561 return NULL; 562 563 rscreen->ws->buffer_get_tiling(buf, µ, ¯o); 564 565 if (macro == RADEON_LAYOUT_TILED) 566 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 567 else if (micro == RADEON_LAYOUT_TILED) 568 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 569 else 570 array_mode = 0; 571 572 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 573 stride, 0, buf, FALSE); 574} 575 576int r600_texture_depth_flush(struct pipe_context *ctx, 577 struct pipe_resource *texture, boolean just_create) 578{ 579 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 580 struct pipe_resource resource; 581 582 if (rtex->flushed_depth_texture) 583 goto out; 584 585 resource.target = texture->target; 586 resource.format = texture->format; 587 resource.width0 = texture->width0; 588 resource.height0 = texture->height0; 589 resource.depth0 = texture->depth0; 590 resource.array_size = texture->array_size; 591 resource.last_level = texture->last_level; 592 resource.nr_samples = texture->nr_samples; 593 resource.usage = PIPE_USAGE_DYNAMIC; 594 resource.bind = texture->bind | PIPE_BIND_DEPTH_STENCIL; 595 resource.flags = R600_RESOURCE_FLAG_TRANSFER | texture->flags; 596 597 rtex->flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 598 if (rtex->flushed_depth_texture == NULL) { 599 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 600 return -ENOMEM; 601 } 602 603 ((struct r600_resource_texture *)rtex->flushed_depth_texture)->is_flushing_texture = TRUE; 604out: 605 if (just_create) 606 return 0; 607 608 /* XXX: only do this if the depth texture has actually changed: 609 */ 610 r600_blit_uncompress_depth(ctx, rtex); 611 return 0; 612} 613 614/* Needs adjustment for pixelformat: 615 */ 616static INLINE unsigned u_box_volume( const struct pipe_box *box ) 617{ 618 return box->width * box->depth * box->height; 619}; 620 621struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 622 struct pipe_resource *texture, 623 unsigned level, 624 unsigned usage, 625 const struct pipe_box *box) 626{ 627 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 628 struct pipe_resource resource; 629 struct r600_transfer *trans; 630 int r; 631 boolean use_staging_texture = FALSE; 632 633 if (usage & PIPE_TRANSFER_MAP_PERMANENTLY) { 634 return NULL; 635 } 636 637 /* We cannot map a tiled texture directly because the data is 638 * in a different order, therefore we do detiling using a blit. 639 * 640 * Also, use a temporary in GTT memory for read transfers, as 641 * the CPU is much happier reading out of cached system memory 642 * than uncached VRAM. 643 */ 644 if (R600_TEX_IS_TILED(rtex, level)) 645 use_staging_texture = TRUE; 646 647 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 648 use_staging_texture = TRUE; 649 650 /* XXX: Use a staging texture for uploads if the underlying BO 651 * is busy. No interface for checking that currently? so do 652 * it eagerly whenever the transfer doesn't require a readback 653 * and might block. 654 */ 655 if ((usage & PIPE_TRANSFER_WRITE) && 656 !(usage & (PIPE_TRANSFER_READ | 657 PIPE_TRANSFER_DONTBLOCK | 658 PIPE_TRANSFER_UNSYNCHRONIZED))) 659 use_staging_texture = TRUE; 660 661 if (!permit_hardware_blit(ctx->screen, texture) || 662 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) 663 use_staging_texture = FALSE; 664 665 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) 666 return NULL; 667 668 trans = CALLOC_STRUCT(r600_transfer); 669 if (trans == NULL) 670 return NULL; 671 pipe_resource_reference(&trans->transfer.resource, texture); 672 trans->transfer.level = level; 673 trans->transfer.usage = usage; 674 trans->transfer.box = *box; 675 if (rtex->depth) { 676 /* XXX: only readback the rectangle which is being mapped? 677 */ 678 /* XXX: when discard is true, no need to read back from depth texture 679 */ 680 r = r600_texture_depth_flush(ctx, texture, FALSE); 681 if (r < 0) { 682 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 683 pipe_resource_reference(&trans->transfer.resource, NULL); 684 FREE(trans); 685 return NULL; 686 } 687 trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level]; 688 trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z); 689 return &trans->transfer; 690 } else if (use_staging_texture) { 691 resource.target = PIPE_TEXTURE_2D; 692 resource.format = texture->format; 693 resource.width0 = box->width; 694 resource.height0 = box->height; 695 resource.depth0 = 1; 696 resource.array_size = 1; 697 resource.last_level = 0; 698 resource.nr_samples = 0; 699 resource.usage = PIPE_USAGE_STAGING; 700 resource.bind = 0; 701 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 702 /* For texture reading, the temporary (detiled) texture is used as 703 * a render target when blitting from a tiled texture. */ 704 if (usage & PIPE_TRANSFER_READ) { 705 resource.bind |= PIPE_BIND_RENDER_TARGET; 706 } 707 /* For texture writing, the temporary texture is used as a sampler 708 * when blitting into a tiled texture. */ 709 if (usage & PIPE_TRANSFER_WRITE) { 710 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 711 } 712 /* Create the temporary texture. */ 713 trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource); 714 if (trans->staging_texture == NULL) { 715 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 716 pipe_resource_reference(&trans->transfer.resource, NULL); 717 FREE(trans); 718 return NULL; 719 } 720 721 trans->transfer.stride = 722 ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0]; 723 if (usage & PIPE_TRANSFER_READ) { 724 r600_copy_to_staging_texture(ctx, trans); 725 /* Always referenced in the blit. */ 726 r600_flush(ctx, NULL, 0); 727 } 728 return &trans->transfer; 729 } 730 trans->transfer.stride = rtex->pitch_in_bytes[level]; 731 trans->transfer.layer_stride = rtex->layer_size[level]; 732 trans->offset = r600_texture_get_offset(rtex, level, box->z); 733 return &trans->transfer; 734} 735 736void r600_texture_transfer_destroy(struct pipe_context *ctx, 737 struct pipe_transfer *transfer) 738{ 739 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 740 struct pipe_resource *texture = transfer->resource; 741 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 742 743 if (rtransfer->staging_texture) { 744 if (transfer->usage & PIPE_TRANSFER_WRITE) { 745 r600_copy_from_staging_texture(ctx, rtransfer); 746 } 747 pipe_resource_reference(&rtransfer->staging_texture, NULL); 748 } 749 750 if (rtex->depth && !rtex->is_flushing_texture) { 751 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture) 752 r600_blit_push_depth(ctx, rtex); 753 } 754 755 pipe_resource_reference(&transfer->resource, NULL); 756 FREE(transfer); 757} 758 759void* r600_texture_transfer_map(struct pipe_context *ctx, 760 struct pipe_transfer* transfer) 761{ 762 struct r600_context *rctx = (struct r600_context *)ctx; 763 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 764 struct pb_buffer *buf; 765 enum pipe_format format = transfer->resource->format; 766 unsigned offset = 0; 767 char *map; 768 769 if (rtransfer->staging_texture) { 770 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf; 771 } else { 772 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 773 774 if (rtex->flushed_depth_texture) 775 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 776 else 777 buf = ((struct r600_resource *)transfer->resource)->buf; 778 779 offset = rtransfer->offset + 780 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 781 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 782 } 783 784 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 785 return NULL; 786 } 787 788 return map + offset; 789} 790 791void r600_texture_transfer_unmap(struct pipe_context *ctx, 792 struct pipe_transfer* transfer) 793{ 794 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 795 struct r600_context *rctx = (struct r600_context*)ctx; 796 struct pb_buffer *buf; 797 798 if (rtransfer->staging_texture) { 799 buf = ((struct r600_resource *)rtransfer->staging_texture)->buf; 800 } else { 801 struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource; 802 803 if (rtex->flushed_depth_texture) { 804 buf = ((struct r600_resource *)rtex->flushed_depth_texture)->buf; 805 } else { 806 buf = ((struct r600_resource *)transfer->resource)->buf; 807 } 808 } 809 rctx->ws->buffer_unmap(buf); 810} 811 812void r600_init_surface_functions(struct r600_context *r600) 813{ 814 r600->context.create_surface = r600_create_surface; 815 r600->context.surface_destroy = r600_surface_destroy; 816} 817 818static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 819 const unsigned char *swizzle_view) 820{ 821 unsigned i; 822 unsigned char swizzle[4]; 823 unsigned result = 0; 824 const uint32_t swizzle_shift[4] = { 825 16, 19, 22, 25, 826 }; 827 const uint32_t swizzle_bit[4] = { 828 0, 1, 2, 3, 829 }; 830 831 if (swizzle_view) { 832 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 833 } else { 834 memcpy(swizzle, swizzle_format, 4); 835 } 836 837 /* Get swizzle. */ 838 for (i = 0; i < 4; i++) { 839 switch (swizzle[i]) { 840 case UTIL_FORMAT_SWIZZLE_Y: 841 result |= swizzle_bit[1] << swizzle_shift[i]; 842 break; 843 case UTIL_FORMAT_SWIZZLE_Z: 844 result |= swizzle_bit[2] << swizzle_shift[i]; 845 break; 846 case UTIL_FORMAT_SWIZZLE_W: 847 result |= swizzle_bit[3] << swizzle_shift[i]; 848 break; 849 case UTIL_FORMAT_SWIZZLE_0: 850 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 851 break; 852 case UTIL_FORMAT_SWIZZLE_1: 853 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 854 break; 855 default: /* UTIL_FORMAT_SWIZZLE_X */ 856 result |= swizzle_bit[0] << swizzle_shift[i]; 857 } 858 } 859 return result; 860} 861 862/* texture format translate */ 863uint32_t r600_translate_texformat(struct pipe_screen *screen, 864 enum pipe_format format, 865 const unsigned char *swizzle_view, 866 uint32_t *word4_p, uint32_t *yuv_format_p) 867{ 868 uint32_t result = 0, word4 = 0, yuv_format = 0; 869 const struct util_format_description *desc; 870 boolean uniform = TRUE; 871 static int r600_enable_s3tc = -1; 872 bool is_srgb_valid = FALSE; 873 874 int i; 875 const uint32_t sign_bit[4] = { 876 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 877 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 878 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 879 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 880 }; 881 desc = util_format_description(format); 882 883 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 884 885 /* Colorspace (return non-RGB formats directly). */ 886 switch (desc->colorspace) { 887 /* Depth stencil formats */ 888 case UTIL_FORMAT_COLORSPACE_ZS: 889 switch (format) { 890 case PIPE_FORMAT_Z16_UNORM: 891 result = FMT_16; 892 goto out_word4; 893 case PIPE_FORMAT_X24S8_UINT: 894 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 895 case PIPE_FORMAT_Z24X8_UNORM: 896 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 897 result = FMT_8_24; 898 goto out_word4; 899 case PIPE_FORMAT_S8X24_UINT: 900 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 901 case PIPE_FORMAT_X8Z24_UNORM: 902 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 903 result = FMT_24_8; 904 goto out_word4; 905 case PIPE_FORMAT_S8_UINT: 906 result = FMT_8; 907 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 908 goto out_word4; 909 case PIPE_FORMAT_Z32_FLOAT: 910 result = FMT_32_FLOAT; 911 goto out_word4; 912 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 913 result = FMT_X24_8_32_FLOAT; 914 goto out_word4; 915 default: 916 goto out_unknown; 917 } 918 919 case UTIL_FORMAT_COLORSPACE_YUV: 920 yuv_format |= (1 << 30); 921 switch (format) { 922 case PIPE_FORMAT_UYVY: 923 case PIPE_FORMAT_YUYV: 924 default: 925 break; 926 } 927 goto out_unknown; /* TODO */ 928 929 case UTIL_FORMAT_COLORSPACE_SRGB: 930 word4 |= S_038010_FORCE_DEGAMMA(1); 931 break; 932 933 default: 934 break; 935 } 936 937 if (r600_enable_s3tc == -1) { 938 struct r600_screen *rscreen = (struct r600_screen *)screen; 939 if (rscreen->info.drm_minor >= 9) 940 r600_enable_s3tc = 1; 941 else 942 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 943 } 944 945 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 946 if (!r600_enable_s3tc) 947 goto out_unknown; 948 949 switch (format) { 950 case PIPE_FORMAT_RGTC1_SNORM: 951 case PIPE_FORMAT_LATC1_SNORM: 952 word4 |= sign_bit[0]; 953 case PIPE_FORMAT_RGTC1_UNORM: 954 case PIPE_FORMAT_LATC1_UNORM: 955 result = FMT_BC4; 956 goto out_word4; 957 case PIPE_FORMAT_RGTC2_SNORM: 958 case PIPE_FORMAT_LATC2_SNORM: 959 word4 |= sign_bit[0] | sign_bit[1]; 960 case PIPE_FORMAT_RGTC2_UNORM: 961 case PIPE_FORMAT_LATC2_UNORM: 962 result = FMT_BC5; 963 goto out_word4; 964 default: 965 goto out_unknown; 966 } 967 } 968 969 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 970 971 if (!r600_enable_s3tc) 972 goto out_unknown; 973 974 if (!util_format_s3tc_enabled) { 975 goto out_unknown; 976 } 977 978 switch (format) { 979 case PIPE_FORMAT_DXT1_RGB: 980 case PIPE_FORMAT_DXT1_RGBA: 981 case PIPE_FORMAT_DXT1_SRGB: 982 case PIPE_FORMAT_DXT1_SRGBA: 983 result = FMT_BC1; 984 is_srgb_valid = TRUE; 985 goto out_word4; 986 case PIPE_FORMAT_DXT3_RGBA: 987 case PIPE_FORMAT_DXT3_SRGBA: 988 result = FMT_BC2; 989 is_srgb_valid = TRUE; 990 goto out_word4; 991 case PIPE_FORMAT_DXT5_RGBA: 992 case PIPE_FORMAT_DXT5_SRGBA: 993 result = FMT_BC3; 994 is_srgb_valid = TRUE; 995 goto out_word4; 996 default: 997 goto out_unknown; 998 } 999 } 1000 1001 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1002 result = FMT_5_9_9_9_SHAREDEXP; 1003 goto out_word4; 1004 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1005 result = FMT_10_11_11_FLOAT; 1006 goto out_word4; 1007 } 1008 1009 1010 for (i = 0; i < desc->nr_channels; i++) { 1011 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1012 word4 |= sign_bit[i]; 1013 } 1014 } 1015 1016 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1017 1018 /* See whether the components are of the same size. */ 1019 for (i = 1; i < desc->nr_channels; i++) { 1020 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1021 } 1022 1023 /* Non-uniform formats. */ 1024 if (!uniform) { 1025 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1026 desc->channel[0].pure_integer) 1027 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1028 switch(desc->nr_channels) { 1029 case 3: 1030 if (desc->channel[0].size == 5 && 1031 desc->channel[1].size == 6 && 1032 desc->channel[2].size == 5) { 1033 result = FMT_5_6_5; 1034 goto out_word4; 1035 } 1036 goto out_unknown; 1037 case 4: 1038 if (desc->channel[0].size == 5 && 1039 desc->channel[1].size == 5 && 1040 desc->channel[2].size == 5 && 1041 desc->channel[3].size == 1) { 1042 result = FMT_1_5_5_5; 1043 goto out_word4; 1044 } 1045 if (desc->channel[0].size == 10 && 1046 desc->channel[1].size == 10 && 1047 desc->channel[2].size == 10 && 1048 desc->channel[3].size == 2) { 1049 result = FMT_2_10_10_10; 1050 goto out_word4; 1051 } 1052 goto out_unknown; 1053 } 1054 goto out_unknown; 1055 } 1056 1057 /* Find the first non-VOID channel. */ 1058 for (i = 0; i < 4; i++) { 1059 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1060 break; 1061 } 1062 } 1063 1064 if (i == 4) 1065 goto out_unknown; 1066 1067 /* uniform formats */ 1068 switch (desc->channel[i].type) { 1069 case UTIL_FORMAT_TYPE_UNSIGNED: 1070 case UTIL_FORMAT_TYPE_SIGNED: 1071#if 0 1072 if (!desc->channel[i].normalized && 1073 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 1074 goto out_unknown; 1075 } 1076#endif 1077 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1078 desc->channel[i].pure_integer) 1079 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1080 1081 switch (desc->channel[i].size) { 1082 case 4: 1083 switch (desc->nr_channels) { 1084 case 2: 1085 result = FMT_4_4; 1086 goto out_word4; 1087 case 4: 1088 result = FMT_4_4_4_4; 1089 goto out_word4; 1090 } 1091 goto out_unknown; 1092 case 8: 1093 switch (desc->nr_channels) { 1094 case 1: 1095 result = FMT_8; 1096 goto out_word4; 1097 case 2: 1098 result = FMT_8_8; 1099 goto out_word4; 1100 case 4: 1101 result = FMT_8_8_8_8; 1102 is_srgb_valid = TRUE; 1103 goto out_word4; 1104 } 1105 goto out_unknown; 1106 case 16: 1107 switch (desc->nr_channels) { 1108 case 1: 1109 result = FMT_16; 1110 goto out_word4; 1111 case 2: 1112 result = FMT_16_16; 1113 goto out_word4; 1114 case 4: 1115 result = FMT_16_16_16_16; 1116 goto out_word4; 1117 } 1118 goto out_unknown; 1119 case 32: 1120 switch (desc->nr_channels) { 1121 case 1: 1122 result = FMT_32; 1123 goto out_word4; 1124 case 2: 1125 result = FMT_32_32; 1126 goto out_word4; 1127 case 4: 1128 result = FMT_32_32_32_32; 1129 goto out_word4; 1130 } 1131 } 1132 goto out_unknown; 1133 1134 case UTIL_FORMAT_TYPE_FLOAT: 1135 switch (desc->channel[i].size) { 1136 case 16: 1137 switch (desc->nr_channels) { 1138 case 1: 1139 result = FMT_16_FLOAT; 1140 goto out_word4; 1141 case 2: 1142 result = FMT_16_16_FLOAT; 1143 goto out_word4; 1144 case 4: 1145 result = FMT_16_16_16_16_FLOAT; 1146 goto out_word4; 1147 } 1148 goto out_unknown; 1149 case 32: 1150 switch (desc->nr_channels) { 1151 case 1: 1152 result = FMT_32_FLOAT; 1153 goto out_word4; 1154 case 2: 1155 result = FMT_32_32_FLOAT; 1156 goto out_word4; 1157 case 4: 1158 result = FMT_32_32_32_32_FLOAT; 1159 goto out_word4; 1160 } 1161 } 1162 goto out_unknown; 1163 } 1164 1165out_word4: 1166 1167 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1168 return ~0; 1169 if (word4_p) 1170 *word4_p = word4; 1171 if (yuv_format_p) 1172 *yuv_format_p = yuv_format; 1173 return result; 1174out_unknown: 1175 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1176 return ~0; 1177} 1178