intel_batchbuffer.c revision 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8
1/************************************************************************** 2 * 3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#include "intel_context.h" 29#include "intel_batchbuffer.h" 30#include "intel_decode.h" 31#include "intel_reg.h" 32#include "intel_bufmgr.h" 33#include "intel_buffers.h" 34 35/* Relocations in kernel space: 36 * - pass dma buffer seperately 37 * - memory manager knows how to patch 38 * - pass list of dependent buffers 39 * - pass relocation list 40 * 41 * Either: 42 * - get back an offset for buffer to fire 43 * - memory manager knows how to fire buffer 44 * 45 * Really want the buffer to be AGP and pinned. 46 * 47 */ 48 49/* Cliprect fence: The highest fence protecting a dma buffer 50 * containing explicit cliprect information. Like the old drawable 51 * lock but irq-driven. X server must wait for this fence to expire 52 * before changing cliprects [and then doing sw rendering?]. For 53 * other dma buffers, the scheduler will grab current cliprect info 54 * and mix into buffer. X server must hold the lock while changing 55 * cliprects??? Make per-drawable. Need cliprects in shared memory 56 * -- beats storing them with every cmd buffer in the queue. 57 * 58 * ==> X server must wait for this fence to expire before touching the 59 * framebuffer with new cliprects. 60 * 61 * ==> Cliprect-dependent buffers associated with a 62 * cliprect-timestamp. All of the buffers associated with a timestamp 63 * must go to hardware before any buffer with a newer timestamp. 64 * 65 * ==> Dma should be queued per-drawable for correct X/GL 66 * synchronization. Or can fences be used for this? 67 * 68 * Applies to: Blit operations, metaops, X server operations -- X 69 * server automatically waits on its own dma to complete before 70 * modifying cliprects ??? 71 */ 72 73void 74intel_batchbuffer_reset(struct intel_batchbuffer *batch) 75{ 76 struct intel_context *intel = batch->intel; 77 78 if (batch->buf != NULL) { 79 dri_bo_unreference(batch->buf); 80 batch->buf = NULL; 81 } 82 83 if (!batch->buffer) 84 batch->buffer = malloc (intel->maxBatchSize); 85 86 batch->buf = dri_bo_alloc(intel->bufmgr, "batchbuffer", 87 intel->maxBatchSize, 4096); 88 if (batch->buffer) 89 batch->map = batch->buffer; 90 else { 91 dri_bo_map(batch->buf, GL_TRUE); 92 batch->map = batch->buf->virtual; 93 } 94 batch->size = intel->maxBatchSize; 95 batch->ptr = batch->map; 96 batch->dirty_state = ~0; 97 batch->cliprect_mode = IGNORE_CLIPRECTS; 98} 99 100struct intel_batchbuffer * 101intel_batchbuffer_alloc(struct intel_context *intel) 102{ 103 struct intel_batchbuffer *batch = calloc(sizeof(*batch), 1); 104 105 batch->intel = intel; 106 intel_batchbuffer_reset(batch); 107 108 return batch; 109} 110 111void 112intel_batchbuffer_free(struct intel_batchbuffer *batch) 113{ 114 if (batch->buffer) 115 free (batch->buffer); 116 else { 117 if (batch->map) { 118 dri_bo_unmap(batch->buf); 119 batch->map = NULL; 120 } 121 } 122 dri_bo_unreference(batch->buf); 123 batch->buf = NULL; 124 free(batch); 125} 126 127 128 129/* TODO: Push this whole function into bufmgr. 130 */ 131static void 132do_flush_locked(struct intel_batchbuffer *batch, 133 GLuint used, GLboolean allow_unlock) 134{ 135 struct intel_context *intel = batch->intel; 136 int ret = 0; 137 unsigned int num_cliprects = 0; 138 struct drm_clip_rect *cliprects = NULL; 139 int x_off = 0, y_off = 0; 140 141 if (batch->buffer) 142 dri_bo_subdata (batch->buf, 0, used, batch->buffer); 143 else 144 dri_bo_unmap(batch->buf); 145 146 batch->map = NULL; 147 batch->ptr = NULL; 148 149 150 if (batch->cliprect_mode == LOOP_CLIPRECTS) { 151 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); 152 } 153 /* Dispatch the batchbuffer, if it has some effect (nonzero cliprects). 154 * Can't short-circuit like this once we have hardware contexts, but we 155 * should always be in DRI2 mode by then anyway. 156 */ 157 if ((batch->cliprect_mode != LOOP_CLIPRECTS || 158 num_cliprects != 0) && !intel->no_hw) { 159 dri_bo_exec(batch->buf, used, cliprects, num_cliprects, 160 (x_off & 0xffff) | (y_off << 16)); 161 } 162 163 if (batch->cliprect_mode == LOOP_CLIPRECTS && num_cliprects == 0) { 164 if (allow_unlock) { 165 /* If we are not doing any actual user-visible rendering, 166 * do a sched_yield to keep the app from pegging the cpu while 167 * achieving nothing. 168 */ 169 UNLOCK_HARDWARE(intel); 170 sched_yield(); 171 LOCK_HARDWARE(intel); 172 } 173 } 174 175 if (INTEL_DEBUG & DEBUG_BATCH) { 176 dri_bo_map(batch->buf, GL_FALSE); 177 intel_decode(batch->buf->virtual, used / 4, batch->buf->offset, 178 intel->intelScreen->deviceID); 179 dri_bo_unmap(batch->buf); 180 181 if (intel->vtbl.debug_batch != NULL) 182 intel->vtbl.debug_batch(intel); 183 } 184 185 if (ret != 0) { 186 UNLOCK_HARDWARE(intel); 187 exit(1); 188 } 189 intel->vtbl.new_batch(intel); 190} 191 192void 193_intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, 194 int line) 195{ 196 struct intel_context *intel = batch->intel; 197 GLuint used = batch->ptr - batch->map; 198 199 if (intel->first_post_swapbuffers_batch == NULL) { 200 intel->first_post_swapbuffers_batch = intel->batch->buf; 201 drm_intel_bo_reference(intel->first_post_swapbuffers_batch); 202 } 203 204 if (used == 0) { 205 batch->cliprect_mode = IGNORE_CLIPRECTS; 206 return; 207 } 208 209 if (INTEL_DEBUG & DEBUG_BATCH) 210 fprintf(stderr, "%s:%d: Batchbuffer flush with %db used\n", file, line, 211 used); 212 213 batch->reserved_space = 0; 214 /* Emit a flush if the bufmgr doesn't do it for us. */ 215 if (intel->always_flush_cache) { 216 intel_batchbuffer_emit_mi_flush(batch); 217 used = batch->ptr - batch->map; 218 } 219 220 /* Round batchbuffer usage to 2 DWORDs. */ 221 222 if ((used & 4) == 0) { 223 *(GLuint *) (batch->ptr) = 0; /* noop */ 224 batch->ptr += 4; 225 used = batch->ptr - batch->map; 226 } 227 228 /* Mark the end of the buffer. */ 229 *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */ 230 batch->ptr += 4; 231 used = batch->ptr - batch->map; 232 233 /* Workaround for recursive batchbuffer flushing: If the window is 234 * moved, we can get into a case where we try to flush during a 235 * flush. What happens is that when we try to grab the lock for 236 * the first flush, we detect that the window moved which then 237 * causes another flush (from the intel_draw_buffer() call in 238 * intelUpdatePageFlipping()). To work around this we reset the 239 * batchbuffer tail pointer before trying to get the lock. This 240 * prevent the nested buffer flush, but a better fix would be to 241 * avoid that in the first place. */ 242 batch->ptr = batch->map; 243 244 if (intel->vtbl.finish_batch) 245 intel->vtbl.finish_batch(intel); 246 247 /* Check that we didn't just wrap our batchbuffer at a bad time. */ 248 assert(!intel->no_batch_wrap); 249 250 batch->reserved_space = BATCH_RESERVED; 251 252 /* TODO: Just pass the relocation list and dma buffer up to the 253 * kernel. 254 */ 255 LOCK_HARDWARE(intel); 256 do_flush_locked(batch, used, GL_FALSE); 257 UNLOCK_HARDWARE(intel); 258 259 if (INTEL_DEBUG & DEBUG_SYNC) { 260 fprintf(stderr, "waiting for idle\n"); 261 dri_bo_map(batch->buf, GL_TRUE); 262 dri_bo_unmap(batch->buf); 263 } 264 265 /* Reset the buffer: 266 */ 267 intel_batchbuffer_reset(batch); 268} 269 270 271/* This is the only way buffers get added to the validate list. 272 */ 273GLboolean 274intel_batchbuffer_emit_reloc(struct intel_batchbuffer *batch, 275 dri_bo *buffer, 276 uint32_t read_domains, uint32_t write_domain, 277 uint32_t delta) 278{ 279 int ret; 280 281 if (batch->ptr - batch->map > batch->buf->size) 282 _mesa_printf ("bad relocation ptr %p map %p offset %d size %d\n", 283 batch->ptr, batch->map, batch->ptr - batch->map, batch->buf->size); 284 ret = dri_bo_emit_reloc(batch->buf, read_domains, write_domain, 285 delta, batch->ptr - batch->map, buffer); 286 287 /* 288 * Using the old buffer offset, write in what the right data would be, in case 289 * the buffer doesn't move and we can short-circuit the relocation processing 290 * in the kernel 291 */ 292 intel_batchbuffer_emit_dword (batch, buffer->offset + delta); 293 294 return GL_TRUE; 295} 296 297void 298intel_batchbuffer_data(struct intel_batchbuffer *batch, 299 const void *data, GLuint bytes, 300 enum cliprect_mode cliprect_mode) 301{ 302 assert((bytes & 3) == 0); 303 intel_batchbuffer_require_space(batch, bytes, cliprect_mode); 304 __memcpy(batch->ptr, data, bytes); 305 batch->ptr += bytes; 306} 307 308/* Emit a pipelined flush to either flush render and texture cache for 309 * reading from a FBO-drawn texture, or flush so that frontbuffer 310 * render appears on the screen in DRI1. 311 * 312 * This is also used for the always_flush_cache driconf debug option. 313 */ 314void 315intel_batchbuffer_emit_mi_flush(struct intel_batchbuffer *batch) 316{ 317 struct intel_context *intel = batch->intel; 318 319 if (intel->gen >= 4) { 320 BEGIN_BATCH(4, IGNORE_CLIPRECTS); 321 OUT_BATCH(_3DSTATE_PIPE_CONTROL | 322 PIPE_CONTROL_INSTRUCTION_FLUSH | 323 PIPE_CONTROL_WRITE_FLUSH | 324 PIPE_CONTROL_NO_WRITE); 325 OUT_BATCH(0); /* write address */ 326 OUT_BATCH(0); /* write data */ 327 OUT_BATCH(0); /* write data */ 328 ADVANCE_BATCH(); 329 } else { 330 BEGIN_BATCH(1, IGNORE_CLIPRECTS); 331 OUT_BATCH(MI_FLUSH); 332 ADVANCE_BATCH(); 333 } 334} 335