radeon_screen.c revision 64106d0d9aeefa6974317042b6bc3e5eaabac5a2
1bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */ 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/************************************************************************** 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul VA Linux Systems Inc., Fremont, California. 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulAll Rights Reserved. 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulPermission is hereby granted, free of charge, to any person obtaining 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paula copy of this software and associated documentation files (the 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul"Software"), to deal in the Software without restriction, including 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulwithout limitation the rights to use, copy, modify, merge, publish, 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Pauldistribute, sublicense, and/or sell copies of the Software, and to 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulpermit persons to whom the Software is furnished to do so, subject to 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulthe following conditions: 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulThe above copyright notice and this permission notice (including the 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulnext paragraph) shall be included in all copies or substantial 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulportions of the Software. 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul**************************************************************************/ 305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 318cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger/** 328cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \file radeon_screen.c 338cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * Screen initialization functions for the Radeon driver. 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 358cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \author Kevin E. Martin <martin@valinux.com> 368cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \author Gareth Hughes <gareth@valinux.com> 375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "glheader.h" 405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "imports.h" 41e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "mtypes.h" 42e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "framebuffer.h" 43e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "renderbuffer.h" 445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 45462183fe4cb6df6d90632d9e2cee881c8d26b1cbAlan Hourihane#define STANDALONE_MMIO 463a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_chipset.h" 475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_macros.h" 483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_screen.h" 493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON 503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_context.h" 513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_span.h" 523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r200_context.h" 543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r200_ioctl.h" 553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r200_span.h" 564f96000e294fa0d6ba6f5915ff508017d9c26d50Chris Rankin#include "r200_tex.h" 573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r300_context.h" 59ee5417bca883d82d618e1c0b65011940253555ddRune Peterson#include "r300_fragprog.h" 6059a08923f51d4ed83effbfcd91473c9ee86465f1Michel Dänzer#include "r300_tex.h" 61e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "radeon_span.h" 623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "utils.h" 655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "context.h" 665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "vblank.h" 67e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "drirenderbuffer.h" 685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6974d563cdfbfb07cc666d60dc909e90ddb9949cbbKeith Whitwell#include "GL/internal/dri_interface.h" 705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 71d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul/* Radeon configuration 72d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul */ 73d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul#include "xmlpool.h" 74d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul 753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON /* R100 */ 76d16aa9859c9f5a3a7bf74a13dbbdd20688d3ad84Adam JacksonPUBLIC const char __driConfigOptions[] = 77d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian PaulDRI_CONF_BEGIN 78d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_PERFORMANCE 79d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 80d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 81d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 82f76ff7e4a7b728258606950f182a0a9a8cce791bRoland Scheidegger DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 83b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger DRI_CONF_HYPERZ(false) 84d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_END 85d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_QUALITY 86d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 87effc73931f86c7961b4eb296d2d4c5d91624a9e3Felix Kuehling DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 88effc73931f86c7961b4eb296d2d4c5d91624a9e3Felix Kuehling DRI_CONF_NO_NEG_LOD_BIAS(false) 89d09209f5530e8bba78e4e0ec62b2027c588cc8f3Eric Anholt DRI_CONF_FORCE_S3TC_ENABLE(false) 90d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 91d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 92d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 93f76ff7e4a7b728258606950f182a0a9a8cce791bRoland Scheidegger DRI_CONF_ALLOW_LARGE_TEXTURES(1) 94d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_END 95d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_DEBUG 96d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_NO_RAST(false) 97d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_END 98d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian PaulDRI_CONF_END; 9930daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheideggerstatic const GLuint __driNConfigOptions = 14; 100d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul 1013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtPUBLIC const char __driConfigOptions[] = 1043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_BEGIN 1053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_PERFORMANCE 1063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 1073a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 1083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 109f76ff7e4a7b728258606950f182a0a9a8cce791bRoland Scheidegger DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 1103a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_HYPERZ(false) 1113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_QUALITY 1133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 1143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 1153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_NEG_LOD_BIAS(false) 1163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FORCE_S3TC_ENABLE(false) 1173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 1183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 1193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 120f76ff7e4a7b728258606950f182a0a9a8cce791bRoland Scheidegger DRI_CONF_ALLOW_LARGE_TEXTURES(1) 1213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 1223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_DEBUG 1243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_RAST(false) 1253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_SOFTWARE 1273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NV_VERTEX_PROGRAM(false) 1283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_END; 130bd4c8ec0ec1edcc96fe841ccc7159b7856ade5c1Roland Scheideggerstatic const GLuint __driNConfigOptions = 16; 1313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension blend_extensions[]; 1333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension ARB_vp_extension[]; 1343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension NV_vp_extension[]; 1353a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension ATI_fs_extension[]; 136cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheideggerextern const struct dri_extension point_extensions[]; 1373a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1393a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1403a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt/* TODO: integrate these into xmlpool.h! */ 1413a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 1423a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 1433a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(en,"Number of texture image units") \ 1443a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 1453a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_END 1463a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1473a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 1483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 1493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(en,"Number of texture coordinate units") \ 1503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 1513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_END 1523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 1543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 1553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 1563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 1573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_END 1583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1593cbfef3917451485aab723b81200156a1077a91cRune Petersen#define DRI_CONF_DISABLE_S3TC(def) \ 1603cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 1613cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DESC(en,"Disable S3TC compression") \ 1623cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_END 1633cbfef3917451485aab723b81200156a1077a91cRune Petersen 1643cbfef3917451485aab723b81200156a1077a91cRune Petersen#define DRI_CONF_DISABLE_FALLBACK(def) \ 1653cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 1663cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 1673cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_END 1683cbfef3917451485aab723b81200156a1077a91cRune Petersen 16962efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 17062efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo TahkolaDRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 17162efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 17262efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo TahkolaDRI_CONF_OPT_END 17362efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola 174ee5417bca883d82d618e1c0b65011940253555ddRune Peterson#define DRI_CONF_FP_OPTIMIZATION(def) \ 175ee5417bca883d82d618e1c0b65011940253555ddRune PetersonDRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 176ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 177ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_ENUM(0,"Optimize for Speed") \ 178ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_ENUM(1,"Optimize for Quality") \ 179ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_DESC_END \ 180ee5417bca883d82d618e1c0b65011940253555ddRune PetersonDRI_CONF_OPT_END 1813cbfef3917451485aab723b81200156a1077a91cRune Petersen 1823a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtconst char __driConfigOptions[] = 1833a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_BEGIN 1843a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_PERFORMANCE 1853a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 1863a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 1873a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 188787fd58186cbaffde7bf930f94a1a1bfa90a23b8Aapo Tahkola DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 1893a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 1903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 1913cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DISABLE_FALLBACK(false) 19262efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 1933a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1943a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_QUALITY 1953a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 1963a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 1973a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_NEG_LOD_BIAS(false) 1983a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FORCE_S3TC_ENABLE(false) 1993cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DISABLE_S3TC(false) 2003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 2013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 2023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 203ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 2043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 2053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_DEBUG 2063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_RAST(false) 2073a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 2083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_END; 209ee5417bca883d82d618e1c0b65011940253555ddRune Petersonstatic const GLuint __driNConfigOptions = 18; 2105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#ifndef RADEON_DEBUG 2123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtint RADEON_DEBUG = 0; 2133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 2143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic const struct dri_debug_control debug_control[] = { 2153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"fall", DEBUG_FALLBACKS}, 2163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"tex", DEBUG_TEXTURE}, 2173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"ioctl", DEBUG_IOCTL}, 2183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"prim", DEBUG_PRIMS}, 2193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"vert", DEBUG_VERTS}, 2203a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"state", DEBUG_STATE}, 2213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"code", DEBUG_CODEGEN}, 2223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"vfmt", DEBUG_VFMT}, 2233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"vtxf", DEBUG_VFMT}, 2243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"verb", DEBUG_VERBOSE}, 2253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"dri", DEBUG_DRI}, 2263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"dma", DEBUG_DMA}, 2273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"san", DEBUG_SANITY}, 2283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"sync", DEBUG_SYNC}, 2293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"pix", DEBUG_PIXEL}, 2303a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"mem", DEBUG_MEMORY}, 2313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 2323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {NULL, 0} 2333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt}; 2343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif /* RADEON_DEBUG */ 235de08b0d7ed8af9d56bf8f82762095de3fe094c95Roland Scheidegger 2363a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 2375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension card_extensions[]; 2398cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 2415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2426a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airliestatic int 2436a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave AirlieradeonGetParam(int fd, int param, void *value) 2446a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie{ 2456a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie int ret; 2466a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie drm_radeon_getparam_t gp; 2476a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 2486a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie gp.param = param; 2496a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie gp.value = value; 2506a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 2516a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 2526a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie return ret; 2536a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie} 2546a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 2558cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheideggerstatic __GLcontextModes * 2568cff2ede6eec1dd480bb8a4835b6985955514d87Roland ScheideggerradeonFillInModes( unsigned pixel_bits, unsigned depth_bits, 2578cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger unsigned stencil_bits, GLboolean have_back_buffer ) 2588cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger{ 2598cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger __GLcontextModes * modes; 2608cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger __GLcontextModes * m; 2618cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger unsigned num_modes; 2628cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger unsigned depth_buffer_factor; 2638cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger unsigned back_buffer_factor; 264da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick GLenum fb_format; 265da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick GLenum fb_type; 2668cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2678cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 2688cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * enough to add support. Basically, if a context is created with an 2698cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 2708cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * will never be used. 2718cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger */ 2728cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger static const GLenum back_buffer_modes[] = { 2738cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 2748cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger }; 2758cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 27638b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane u_int8_t depth_bits_array[2]; 27738b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane u_int8_t stencil_bits_array[2]; 2788cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2798cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 280da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick depth_bits_array[0] = depth_bits; 281da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick depth_bits_array[1] = depth_bits; 282da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick 2838cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger /* Just like with the accumulation buffer, always provide some modes 2848cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * with a stencil buffer. It will be a sw fallback, but some apps won't 2858cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * care about that. 2868cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger */ 287da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick stencil_bits_array[0] = 0; 288da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 2898cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2908cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 2918cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger back_buffer_factor = (have_back_buffer) ? 2 : 1; 2928cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2938cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger num_modes = depth_buffer_factor * back_buffer_factor * 4; 2948cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 295da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick if ( pixel_bits == 16 ) { 296da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_format = GL_RGB; 297da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_type = GL_UNSIGNED_SHORT_5_6_5; 298da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick } 299da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick else { 300da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_format = GL_BGRA; 301da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 302da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick } 303da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick 3045f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick modes = (*dri_interface->createContextModes)( num_modes, sizeof( __GLcontextModes ) ); 3058cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger m = modes; 306da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick if ( ! driFillInModes( & m, fb_format, fb_type, 307da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick depth_bits_array, stencil_bits_array, depth_buffer_factor, 3088cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger back_buffer_modes, back_buffer_factor, 309da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick GLX_TRUE_COLOR ) ) { 310da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 311da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick __func__, __LINE__ ); 312da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick return NULL; 3138cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3148cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 315da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick if ( ! driFillInModes( & m, fb_format, fb_type, 316da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick depth_bits_array, stencil_bits_array, depth_buffer_factor, 3178cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger back_buffer_modes, back_buffer_factor, 318da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick GLX_DIRECT_COLOR ) ) { 319da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 320da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick __func__, __LINE__ ); 321da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick return NULL; 3228cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3238cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 3248cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger /* Mark the visual as slow if there are "fake" stencil bits. 3258cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger */ 3268cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger for ( m = modes ; m != NULL ; m = m->next ) { 3278cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger if ( (m->stencilBits != 0) && (m->stencilBits != stencil_bits) ) { 3288cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger m->visualRating = GLX_SLOW_CONFIG; 3298cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3308cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3318cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 3328cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger return modes; 3338cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger} 334c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick 3358cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 3365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Create the device specific screen private data struct. 3375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 33867a8decffeada987d10da616d72c1e6ec473dfa5Brian Paulstatic radeonScreenPtr 33967a8decffeada987d10da616d72c1e6ec473dfa5Brian PaulradeonCreateScreen( __DRIscreenPrivate *sPriv ) 3405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 3415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonScreenPtr screen; 3425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 34399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane unsigned char *RADEONMMIO; 344c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick PFNGLXSCRENABLEEXTENSIONPROC glx_enable_extension = 3455f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick (PFNGLXSCRENABLEEXTENSIONPROC) (*dri_interface->getProcAddress("glxEnableExtension")); 3465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 347dabec11d277e68b6940e741651e61102767240b9Alan Hourihane if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 348dabec11d277e68b6940e741651e61102767240b9Alan Hourihane fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 349dabec11d277e68b6940e741651e61102767240b9Alan Hourihane return GL_FALSE; 350dabec11d277e68b6940e741651e61102767240b9Alan Hourihane } 3515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Allocate the private area */ 3535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 3545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !screen ) { 3555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: Could not allocate memory for screen structure", 3565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__); 3575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 3585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3603a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 3613a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 3623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 3633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 364bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl /* parse information in __driConfigOptions */ 365d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul driParseOptionInfo (&screen->optionCache, 366d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul __driConfigOptions, __driNConfigOptions); 3675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* This is first since which regions we map depends on whether or 3695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * not we are using a PCI card. 3705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3716a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 372bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl { 3735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 3746a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 3756a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie &screen->gart_buffer_offset); 3766a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 3775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (ret) { 378bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl FREE( screen ); 379ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 3805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 3815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 383f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 3846a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie &screen->gart_base); 385f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie if (ret) { 386f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie FREE( screen ); 387f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 388f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie return NULL; 389f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie } 390f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie 391f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 392f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie &screen->irq); 393f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie if (ret) { 394f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie FREE( screen ); 395f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 396f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie return NULL; 3975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 398efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 399efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 400efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 401efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 402efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 403efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 404efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 4055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.handle = dri_priv->registerHandle; 4085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.size = dri_priv->registerSize; 4095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( drmMap( sPriv->fd, 4105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.handle, 4115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.size, 4125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &screen->mmio.map ) ) { 4135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 4145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 4155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 41899ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane RADEONMMIO = screen->mmio.map; 41999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 4205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.handle = dri_priv->statusHandle; 4215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.size = dri_priv->statusSize; 4225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( drmMap( sPriv->fd, 4235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.handle, 4245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.size, 4255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &screen->status.map ) ) { 4265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 4275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 4285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 4295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 43138b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane screen->scratch = (__volatile__ u_int32_t *) 4325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 4335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->buffers = drmMapBufs( sPriv->fd ); 4355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !screen->buffers ) { 4365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->status.map, screen->status.size ); 4375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 4385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 4395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 4405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 443bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 444bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.handle = dri_priv->gartTexHandle; 445bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.size = dri_priv->gartTexMapSize; 4465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( drmMap( sPriv->fd, 447bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.handle, 448bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.size, 449bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl (drmAddressPtr)&screen->gartTextures.map ) ) { 4505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmapBufs( screen->buffers ); 4515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->status.map, screen->status.size ); 4525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 4535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 454bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 4555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4565df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 457bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 458f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 4595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4613a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = 0; 4623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt /* XXX: add more chipsets */ 4635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul switch ( dri_priv->deviceID ) { 4643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_LY: 4653a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_LZ: 4663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_QY: 4673a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_QZ: 4683a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RN50_515E: 4693a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RN50_5969: 4703a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV100; 4713a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4733a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS100_4136: 4743a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS100_4336: 4753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RS100; 4763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4783a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS200_4137: 4793a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS200_4337: 4803a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS250_4237: 4813a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS250_4437: 4823a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RS200; 4833a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4843a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QD: 4865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QE: 4875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QF: 4885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QG: 489de7b071b5534fc423a056abd521de8bf9120f89eRoland Scheidegger /* all original radeons (7200) presumably have a stencil op bug */ 4903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R100; 4913a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 4923a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4933a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RV200_QW: 495de08b0d7ed8af9d56bf8f82762095de3fe094c95Roland Scheidegger case PCI_CHIP_RV200_QX: 4965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_LW: 497de08b0d7ed8af9d56bf8f82762095de3fe094c95Roland Scheidegger case PCI_CHIP_RADEON_LX: 4983a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV200; 4993a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_BB: 5033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_BC: 5043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_QH: 5053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_QL: 5063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_QM: 5073a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R200; 5083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 5103a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_If: 5123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Ig: 5133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Ld: 5143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Lf: 5153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Lg: 5163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV250; 5173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 5183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5203a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5960: 5213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5961: 5223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5962: 5233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5964: 5243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5965: 5253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5C61: 5263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5C63: 5273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV280; 5283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5303a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS300_5834: 5323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS300_5835: 5334e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS350_7834: 5344e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS350_7835: 5353a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RS300; 5363a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5373a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AD: 5393a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AE: 5403a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AF: 5413a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AG: 5423a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_ND: 5433a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_NE: 5443a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_NF: 5453a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_NG: 5463a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R300; 5473a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AP: 5513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AQ: 5523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AR: 5533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AS: 5543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AT: 5553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AV: 5563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AU: 5573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NP: 5583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NQ: 5593a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NR: 5603a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NS: 5613a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NT: 5623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NV: 5633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV350; 5643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5653a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5673a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AH: 5683a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AI: 5693a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AJ: 5703a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AK: 5713a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_NH: 5723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_NI: 5733a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R360_NJ: 5743a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_NK: 5753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R350; 5763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5783a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5793a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5460: 5804e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV370_5462: 5813a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5464: 5823a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B60: 5833a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B62: 5844e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV370_5B63: 5853a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B64: 5863a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B65: 5874e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3150: 5884e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3152: 5894e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3154: 5904e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3E50: 5914e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3E54: 5923a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV380; 5933a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5943a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5953a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5963a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JN: 5973a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JH: 5983a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JI: 5993a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JJ: 6003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JK: 6013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JL: 6023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JM: 6033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JO: 6043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JP: 6054e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R420_JT: 6064e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B49: 6074e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B4A: 6084e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B4B: 6094e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B4C: 6104e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UH: 6114e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UI: 6124e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UJ: 6134e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UK: 6144e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554C: 6154e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554D: 6164e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554E: 6174e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554F: 6184e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_5550: 6194e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UQ: 6204e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UR: 6214e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UT: 6224e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_5D48: 6234e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_5D49: 6244e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_5D4A: 6254e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4C: 6264e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4D: 6274e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4E: 6284e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4F: 6294e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D50: 6304e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D52: 6314e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_5D57: 6323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R420; 6333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 6343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 6353a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 6364e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_564A: 6374e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_564B: 6384e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_564F: 6394e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5652: 6404e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5653: 6414e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E48: 6424e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4A: 6434e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4B: 6444e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4C: 6454e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4D: 6464e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4F: 6474e7766992607db215430ee388751f32692401c0aRoland Scheidegger screen->chip_family = CHIP_FAMILY_RV410; 6484e7766992607db215430ee388751f32692401c0aRoland Scheidegger screen->chip_flags = RADEON_CHIPSET_TCL; 6494e7766992607db215430ee388751f32692401c0aRoland Scheidegger break; 6504e7766992607db215430ee388751f32692401c0aRoland Scheidegger 6514e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS480_5954: 6524e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS480_5955: 6534e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS482_5974: 6544e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS482_5975: 6554e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS400_5A41: 6564e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS400_5A42: 6574e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RC410_5A61: 6584e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RC410_5A62: 6594e7766992607db215430ee388751f32692401c0aRoland Scheidegger screen->chip_family = CHIP_FAMILY_RS400; 6608130a4fe982a7583e439a1fac61c5050f85bdf46Dave Airlie fprintf(stderr, "Warning, xpress200 detected.\n"); 6614e7766992607db215430ee388751f32692401c0aRoland Scheidegger break; 6624e7766992607db215430ee388751f32692401c0aRoland Scheidegger 6633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt default: 6643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 6653a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt dri_priv->deviceID); 6663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return NULL; 6675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6689cb82f7917b11288169146035700b992b86a7ec2Aapo Tahkola if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 669efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg sPriv->ddx_version.minor < 2) { 6709cb82f7917b11288169146035700b992b86a7ec2Aapo Tahkola fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 6719cb82f7917b11288169146035700b992b86a7ec2Aapo Tahkola return NULL; 672fb0175db931e1b1457b9b7ea2faa44f07d549266Aapo Tahkola } 6735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6743a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (screen->chip_family <= CHIP_FAMILY_RS200) 6758bc4dae67e083c6415c07e6ff77e700f7395dc9eRoland Scheidegger screen->chip_flags |= RADEON_CLASS_R100; 6763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt else if (screen->chip_family <= CHIP_FAMILY_RV280) 6773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags |= RADEON_CLASS_R200; 6783a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt else 6793a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags |= RADEON_CLASS_R300; 6803a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 6815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->cpp = dri_priv->bpp / 8; 6825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->AGPMode = dri_priv->AGPMode; 6835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 68499ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16; 68599ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 686efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg if ( sPriv->drm_version.minor >= 10 ) { 687ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_setparam_t sp; 68899ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 68999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane sp.param = RADEON_SETPARAM_FB_LOCATION; 69099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane sp.value = screen->fbLocation; 69199ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 69299ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 69399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane &sp, sizeof( sp ) ); 69499ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane } 69599ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 6965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->frontOffset = dri_priv->frontOffset; 6975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->frontPitch = dri_priv->frontPitch; 6985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->backOffset = dri_priv->backOffset; 6995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->backPitch = dri_priv->backPitch; 7005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->depthOffset = dri_priv->depthOffset; 7015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->depthPitch = dri_priv->depthPitch; 7025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 703a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger /* Check if ddx has set up a surface reg to cover depth buffer */ 704efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->depthHasSurface = ((sPriv->ddx_version.major > 4) && 7053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt (screen->chip_flags & RADEON_CHIPSET_TCL)); 706a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger 7079790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer if ( dri_priv->textureSize == 0 ) { 7089790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 7099790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 7109790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 7119790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer dri_priv->log2GARTTexGran; 7129790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer } else { 7139790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 7149790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer + screen->fbLocation; 7159790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 7169790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 7179790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer dri_priv->log2TexGran; 7189790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer } 7195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7209790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer if ( !screen->gartTextures.map || dri_priv->textureSize == 0 721bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 7225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 723ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 724ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texSize[RADEON_GART_TEX_HEAP] = 0; 725ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 7265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } else { 7275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 728ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 729ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 730ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 731bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl dri_priv->log2GARTTexGran; 7325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 733aaebfc88c08c79cd70f1e0d1d262a25e9ded47d1Jon Smirl 734f7c9eafa856623d5ce72afb8b20b7ccbcc3e671dIan Romanick if ( glx_enable_extension != NULL ) { 735f7c9eafa856623d5ce72afb8b20b7ccbcc3e671dIan Romanick if ( screen->irq != 0 ) { 736aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_SGI_swap_control" ); 737aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_SGI_video_sync" ); 738aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_MESA_swap_control" ); 739f7c9eafa856623d5ce72afb8b20b7ccbcc3e671dIan Romanick } 740aaebfc88c08c79cd70f1e0d1d262a25e9ded47d1Jon Smirl 741aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_MESA_swap_frame_usage" ); 7423a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (IS_R200_CLASS(screen)) 743aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_MESA_allocate_memory" ); 744f2ad1b60c0da11283b399008f491792790cea294Brian Paul 745aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_MESA_copy_sub_buffer" ); 746aac367f48afc62176faf67aa6f329fbeae2004b4Kristian Høgsberg (*glx_enable_extension)( sPriv->psc, "GLX_SGI_make_current_read" ); 747f7c9eafa856623d5ce72afb8b20b7ccbcc3e671dIan Romanick } 748c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick 7493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 7503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (IS_R200_CLASS(screen)) { 7513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt sPriv->psc->allocateMemory = (void *) r200AllocateMemoryMESA; 7523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt sPriv->psc->freeMemory = (void *) r200FreeMemoryMESA; 7533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt sPriv->psc->memoryOffset = (void *) r200GetMemoryOffsetMESA; 7543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt } 7553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 7563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 7575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->driScreen = sPriv; 7585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 7595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return screen; 7605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 7615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Destroy the device specific screen private data struct. 7635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 76467a8decffeada987d10da616d72c1e6ec473dfa5Brian Paulstatic void 76567a8decffeada987d10da616d72c1e6ec473dfa5Brian PaulradeonDestroyScreen( __DRIscreenPrivate *sPriv ) 7665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 7675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 7685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (!screen) 7705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return; 7715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 772bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl if ( screen->gartTextures.map ) { 773bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 7745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 7755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmapBufs( screen->buffers ); 7765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->status.map, screen->status.size ); 7775df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 7785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 779bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl /* free all option information */ 780bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl driDestroyOptionInfo (&screen->optionCache); 781bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 7825df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 7835df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sPriv->private = NULL; 7845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 7855df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Initialize the driver specific screen private data. 7885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 7895df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic GLboolean 7905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulradeonInitDriver( __DRIscreenPrivate *sPriv ) 7915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 7925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sPriv->private = (void *) radeonCreateScreen( sPriv ); 7935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !sPriv->private ) { 7945df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonDestroyScreen( sPriv ); 7955df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return GL_FALSE; 7965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 7975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return GL_TRUE; 7995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8028cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger/** 803e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 8048cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * 8058cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \todo This function (and its interface) will need to be updated to support 8068cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * pbuffers. 8075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic GLboolean 8095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulradeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 8105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIdrawablePrivate *driDrawPriv, 8115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const __GLcontextModes *mesaVis, 8125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean isPixmap ) 8135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 814e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 815e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 8165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (isPixmap) { 8175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return GL_FALSE; /* not implemented */ 8185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else { 8205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swDepth = GL_FALSE; 8215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swAlpha = GL_FALSE; 8225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swAccum = mesaVis->accumRedBits > 0; 8235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swStencil = mesaVis->stencilBits > 0 && 8245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul mesaVis->depthBits != 24; 825e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 826e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 827982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* front color renderbuffer */ 828e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul { 829e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *frontRb 83061ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_RGBA, 83161ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->frontOffset, 83261ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 83361ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->frontOffset, screen->frontPitch, 83461ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 835e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(frontRb, mesaVis); 836e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); 837e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 838e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 839982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* back color renderbuffer */ 840e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if (mesaVis->doubleBufferMode) { 841e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *backRb 84261ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_RGBA, 84361ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->backOffset, 84461ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 84561ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->backOffset, screen->backPitch, 84661ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 847e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(backRb, mesaVis); 848e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); 849e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 850e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 851982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* depth renderbuffer */ 852e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if (mesaVis->depthBits == 16) { 853e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *depthRb 85461ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_DEPTH_COMPONENT16, 85561ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->depthOffset, 85661ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 85761ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->depthOffset, screen->depthPitch, 85861ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 859e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(depthRb, mesaVis); 860e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 861982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul depthRb->depthHasSurface = screen->depthHasSurface; 862e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 863e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul else if (mesaVis->depthBits == 24) { 864e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *depthRb 86561ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_DEPTH_COMPONENT24, 86661ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->depthOffset, 86761ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 86861ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->depthOffset, screen->depthPitch, 86961ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 870e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(depthRb, mesaVis); 871e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 872982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul depthRb->depthHasSurface = screen->depthHasSurface; 873e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 874e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 875982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* stencil renderbuffer */ 876e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if (mesaVis->stencilBits > 0 && !swStencil) { 877e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *stencilRb 87861ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, 87961ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->depthOffset, 88061ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 88161ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->depthOffset, screen->depthPitch, 88261ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 883e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(stencilRb, mesaVis); 884e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); 885350a1676357301f3d103b6d16d01c766644bf872Brian Paul stencilRb->depthHasSurface = screen->depthHasSurface; 886e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 887e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 888e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_soft_renderbuffers(fb, 889e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul GL_FALSE, /* color */ 890e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swDepth, 891e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swStencil, 892e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swAccum, 893e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swAlpha, 894e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul GL_FALSE /* aux */); 895e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driDrawPriv->driverPrivate = (void *) fb; 896982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul 8975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return (driDrawPriv->driverPrivate != NULL); 8985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 9005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void 9035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulradeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 9045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 905a510bc3ee1a696da120c09ee4ec33dc033f671acBrian _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 9065df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 9075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 9093a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt/** 9103a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt * Choose the appropriate CreateContext function based on the chipset. 9113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt * Eventually, all drivers will go through this process. 9123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt */ 9133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 9143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt __DRIcontextPrivate * driContextPriv, 9153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt void *sharedContextPriv) 9163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt{ 9173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 9183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 9193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9203a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (IS_R300_CLASS(screen)) 9213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 9223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return GL_FALSE; 9233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt} 9243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt/** 9263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt * Choose the appropriate DestroyContext function based on the chipset. 9273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt */ 9283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 9293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt{ 9303a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 9313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (IS_R300_CLASS(radeon->radeonScreen)) 9333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return r300DestroyContext(driContextPriv); 9343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt} 9353a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9363a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9373a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 9383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9393a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 9405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic struct __DriverAPIRec radeonAPI = { 9415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .DestroyScreen = radeonDestroyScreen, 9425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .CreateContext = radeonCreateContext, 9435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .DestroyContext = radeonDestroyContext, 9445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .CreateBuffer = radeonCreateBuffer, 9455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .DestroyBuffer = radeonDestroyBuffer, 9465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .SwapBuffers = radeonSwapBuffers, 9475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .MakeCurrent = radeonMakeCurrent, 9485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .UnbindContext = radeonUnbindContext, 9495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .GetSwapInfo = getSwapInfo, 9505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .GetMSC = driGetMSC32, 9515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .WaitForMSC = driWaitForMSC32, 9525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul .WaitForSBC = NULL, 953f2ad1b60c0da11283b399008f491792790cea294Brian Paul .SwapBuffersMSC = NULL, 954f2ad1b60c0da11283b399008f491792790cea294Brian Paul .CopySubBuffer = radeonCopySubBuffer, 95559a08923f51d4ed83effbfcd91473c9ee86465f1Michel Dänzer#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 95659a08923f51d4ed83effbfcd91473c9ee86465f1Michel Dänzer .setTexOffset = r300SetTexOffset, 95759a08923f51d4ed83effbfcd91473c9ee86465f1Michel Dänzer#endif 9585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul}; 9593a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#else 9603a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic const struct __DriverAPIRec r200API = { 9613a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .DestroyScreen = radeonDestroyScreen, 9623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .CreateContext = r200CreateContext, 9633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .DestroyContext = r200DestroyContext, 9643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .CreateBuffer = radeonCreateBuffer, 9653a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .DestroyBuffer = radeonDestroyBuffer, 9663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .SwapBuffers = r200SwapBuffers, 9673a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .MakeCurrent = r200MakeCurrent, 9683a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .UnbindContext = r200UnbindContext, 9693a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .GetSwapInfo = getSwapInfo, 9703a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .GetMSC = driGetMSC32, 9713a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .WaitForMSC = driWaitForMSC32, 9723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt .WaitForSBC = NULL, 973f2ad1b60c0da11283b399008f491792790cea294Brian Paul .SwapBuffersMSC = NULL, 9744f96000e294fa0d6ba6f5915ff508017d9c26d50Chris Rankin .CopySubBuffer = r200CopySubBuffer, 9754f96000e294fa0d6ba6f5915ff508017d9c26d50Chris Rankin .setTexOffset = r200SetTexOffset 9763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt}; 9773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 9785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 97964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg 980bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/** 98164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * This is the driver specific part of the createNewScreen entry point. 98264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * 98364106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * \todo maybe fold this into intelInitDriver 984bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl * 98564106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * \return the __GLcontextModes supported by this driver 9865df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 98764106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg__GLcontextModes *__driDriverInitScreen(__DRIscreenPrivate *psp) 9885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 9893a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON 9903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const char *driver_name = "Radeon"; 991a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 9925b98ada88071a752b6000756949a1951183cdd0bIan Romanick static const __DRIversion dri_expected = { 4, 0, 0 }; 993f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie static const __DRIversion drm_expected = { 1, 6, 0 }; 9943a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 9953a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const char *driver_name = "R200"; 9963a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 9973a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIversion dri_expected = { 4, 0, 0 }; 998f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie static const __DRIversion drm_expected = { 1, 6, 0 }; 9993a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 10003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const char *driver_name = "R300"; 10013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 10023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIversion dri_expected = { 4, 0, 0 }; 1003dba9c0bafd889d30f044d1e2e870b07ed60efd0aAapo Tahkola static const __DRIversion drm_expected = { 1, 24, 0 }; 10043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 100564106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 10065f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick 10073a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if ( ! driCheckDriDdxDrmVersions3( driver_name, 100864106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg &psp->dri_version, & dri_expected, 100964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg &psp->ddx_version, & ddx_expected, 101064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg &psp->drm_version, & drm_expected ) ) { 10115b98ada88071a752b6000756949a1951183cdd0bIan Romanick return NULL; 10125b98ada88071a752b6000756949a1951183cdd0bIan Romanick } 10133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 101464106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg psp->DriverAPI = radeonAPI; 10153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 101664106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg psp->DriverAPI = r200API; 10173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 10183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 101964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg /* Calling driInitExtensions here, with a NULL context pointer, 102064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * does not actually enable the extensions. It just makes sure 102164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * that all the dispatch offsets for all the extensions that 102264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * *might* be enables are known. This is needed because the 102364106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * dispatch offsets need to be known when _mesa_context_create 102464106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * is called, but we can't enable the extensions until we have a 102564106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * context pointer. 102664106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * 102764106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * Hello chicken. Hello egg. How are you two today? 102864106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg */ 102964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitExtensions( NULL, card_extensions, GL_FALSE ); 10303a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 103164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitExtensions( NULL, blend_extensions, GL_FALSE ); 103264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitSingleExtension( NULL, ARB_vp_extension ); 103364106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitSingleExtension( NULL, NV_vp_extension ); 103464106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitSingleExtension( NULL, ATI_fs_extension ); 103564106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitExtensions( NULL, point_extensions, GL_FALSE ); 10363a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 10378cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 103864106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg if (!radeonInitDriver(psp)) 103964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg return NULL; 104064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg 104164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg return radeonFillInModes( dri_priv->bpp, 104264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg (dri_priv->bpp == 16) ? 16 : 24, 104364106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg (dri_priv->bpp == 16) ? 0 : 8, 104464106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg (dri_priv->backOffset != dri_priv->depthOffset) ); 10455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1046c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick 10475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/** 10495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Get information about previous buffer swaps. 10505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 10515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int 10525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulgetSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 10535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 10543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 10555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa; 10563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 10573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt r200ContextPtr rmesa; 10583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 10595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 10615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul || (dPriv->driContextPriv->driverPrivate == NULL) 10625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul || (sInfo == NULL) ) { 10635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return -1; 10645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt rmesa = dPriv->driContextPriv->driverPrivate; 10675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_count = rmesa->swap_count; 10685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_ust = rmesa->swap_ust; 10695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_missed_count = rmesa->swap_missed_count; 10705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 10725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 10735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul : 0.0; 10745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10755df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return 0; 10765df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1077