radeon_screen.c revision acba9c1771d653126fd6f604cb80c050b9e8ffb3
1bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/* $XFree86: xc/lib/GL/mesa/src/drv/radeon/radeon_screen.c,v 1.7 2003/03/26 20:43:51 tsi Exp $ */ 25df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/************************************************************************** 35df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 45df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulCopyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and 55df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul VA Linux Systems Inc., Fremont, California. 65df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 75df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulAll Rights Reserved. 85df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 95df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulPermission is hereby granted, free of charge, to any person obtaining 105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paula copy of this software and associated documentation files (the 115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul"Software"), to deal in the Software without restriction, including 125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulwithout limitation the rights to use, copy, modify, merge, publish, 135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Pauldistribute, sublicense, and/or sell copies of the Software, and to 145df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulpermit persons to whom the Software is furnished to do so, subject to 155df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulthe following conditions: 165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulThe above copyright notice and this permission notice (including the 185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulnext paragraph) shall be included in all copies or substantial 195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulportions of the Software. 205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulTHE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulEXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulMERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulIN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulLIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulOF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulWITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul**************************************************************************/ 305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 318cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger/** 328cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \file radeon_screen.c 338cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * Screen initialization functions for the Radeon driver. 345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * 358cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \author Kevin E. Martin <martin@valinux.com> 368cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \author Gareth Hughes <gareth@valinux.com> 375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "glheader.h" 405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "imports.h" 41e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "mtypes.h" 42e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "framebuffer.h" 43e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "renderbuffer.h" 445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 45462183fe4cb6df6d90632d9e2cee881c8d26b1cbAlan Hourihane#define STANDALONE_MMIO 463a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_chipset.h" 475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "radeon_macros.h" 483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_screen.h" 493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON 503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_context.h" 513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "radeon_span.h" 523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r200_context.h" 543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r200_ioctl.h" 553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r200_span.h" 564f96000e294fa0d6ba6f5915ff508017d9c26d50Chris Rankin#include "r200_tex.h" 573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#include "r300_context.h" 59ee5417bca883d82d618e1c0b65011940253555ddRune Peterson#include "r300_fragprog.h" 6059a08923f51d4ed83effbfcd91473c9ee86465f1Michel Dänzer#include "r300_tex.h" 61e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "radeon_span.h" 623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "utils.h" 655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "context.h" 665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul#include "vblank.h" 67e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul#include "drirenderbuffer.h" 685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 6974d563cdfbfb07cc666d60dc909e90ddb9949cbbKeith Whitwell#include "GL/internal/dri_interface.h" 705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 71d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul/* Radeon configuration 72d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul */ 73d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul#include "xmlpool.h" 74d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul 753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON /* R100 */ 76d16aa9859c9f5a3a7bf74a13dbbdd20688d3ad84Adam JacksonPUBLIC const char __driConfigOptions[] = 77d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian PaulDRI_CONF_BEGIN 78d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_PERFORMANCE 79d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 80d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 81d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 82f76ff7e4a7b728258606950f182a0a9a8cce791bRoland Scheidegger DRI_CONF_MAX_TEXTURE_UNITS(3,2,3) 83b31b7836d6e7abf80dd4feacce333d4b1fe6e4abRoland Scheidegger DRI_CONF_HYPERZ(false) 84d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_END 85d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_QUALITY 86d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 87effc73931f86c7961b4eb296d2d4c5d91624a9e3Felix Kuehling DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 88effc73931f86c7961b4eb296d2d4c5d91624a9e3Felix Kuehling DRI_CONF_NO_NEG_LOD_BIAS(false) 89d09209f5530e8bba78e4e0ec62b2027c588cc8f3Eric Anholt DRI_CONF_FORCE_S3TC_ENABLE(false) 90d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 91d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 92d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 93acba9c1771d653126fd6f604cb80c050b9e8ffb3Michel Dänzer DRI_CONF_ALLOW_LARGE_TEXTURES(2) 94d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_END 95d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_DEBUG 96d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_NO_RAST(false) 97d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul DRI_CONF_SECTION_END 98d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian PaulDRI_CONF_END; 9930daa7529331057ecb470efb500152e9c4aa1ae5Roland Scheideggerstatic const GLuint __driNConfigOptions = 14; 100d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul 1013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 1025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 1033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtPUBLIC const char __driConfigOptions[] = 1043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_BEGIN 1053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_PERFORMANCE 1063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 1073a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 1083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 109f76ff7e4a7b728258606950f182a0a9a8cce791bRoland Scheidegger DRI_CONF_MAX_TEXTURE_UNITS(6,2,6) 1103a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_HYPERZ(false) 1113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_QUALITY 1133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 1143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0") 1153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_NEG_LOD_BIAS(false) 1163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FORCE_S3TC_ENABLE(false) 1173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 1183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 1193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 120acba9c1771d653126fd6f604cb80c050b9e8ffb3Michel Dänzer DRI_CONF_ALLOW_LARGE_TEXTURES(2) 1213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0") 1223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_DEBUG 1243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_RAST(false) 1253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_SOFTWARE 1273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NV_VERTEX_PROGRAM(false) 1283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_END; 130bd4c8ec0ec1edcc96fe841ccc7159b7856ade5c1Roland Scheideggerstatic const GLuint __driNConfigOptions = 16; 1313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension blend_extensions[]; 1333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension ARB_vp_extension[]; 1343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension NV_vp_extension[]; 1353a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension ATI_fs_extension[]; 136cb977ae5f4c9fab5753c04bfdd8736978ad4feeeRoland Scheideggerextern const struct dri_extension point_extensions[]; 1373a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 1393a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1403a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt/* TODO: integrate these into xmlpool.h! */ 1413a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#define DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(def,min,max) \ 1423a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_BEGIN_V(texture_image_units,int,def, # min ":" # max ) \ 1433a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(en,"Number of texture image units") \ 1443a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(de,"Anzahl der Textureinheiten") \ 1453a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_END 1463a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1473a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#define DRI_CONF_MAX_TEXTURE_COORD_UNITS(def,min,max) \ 1483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_BEGIN_V(texture_coord_units,int,def, # min ":" # max ) \ 1493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(en,"Number of texture coordinate units") \ 1503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(de,"Anzahl der Texturkoordinateneinheiten") \ 1513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_END 1523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \ 1543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \ 1553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(en,"Size of command buffer (in KB)") \ 1563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \ 1573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_OPT_END 1583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 1593cbfef3917451485aab723b81200156a1077a91cRune Petersen#define DRI_CONF_DISABLE_S3TC(def) \ 1603cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_BEGIN(disable_s3tc,bool,def) \ 1613cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DESC(en,"Disable S3TC compression") \ 1623cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_END 1633cbfef3917451485aab723b81200156a1077a91cRune Petersen 1643cbfef3917451485aab723b81200156a1077a91cRune Petersen#define DRI_CONF_DISABLE_FALLBACK(def) \ 1653cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_BEGIN(disable_lowimpact_fallback,bool,def) \ 1663cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DESC(en,"Disable Low-impact fallback") \ 1673cbfef3917451485aab723b81200156a1077a91cRune PetersenDRI_CONF_OPT_END 1683cbfef3917451485aab723b81200156a1077a91cRune Petersen 16962efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola#define DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(def) \ 17062efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo TahkolaDRI_CONF_OPT_BEGIN(disable_stencil_two_side,bool,def) \ 17162efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola DRI_CONF_DESC(en,"Disable GL_EXT_stencil_two_side") \ 17262efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo TahkolaDRI_CONF_OPT_END 17362efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola 174ee5417bca883d82d618e1c0b65011940253555ddRune Peterson#define DRI_CONF_FP_OPTIMIZATION(def) \ 175ee5417bca883d82d618e1c0b65011940253555ddRune PetersonDRI_CONF_OPT_BEGIN_V(fp_optimization,enum,def,"0:1") \ 176ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_DESC_BEGIN(en,"Fragment Program optimization") \ 177ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_ENUM(0,"Optimize for Speed") \ 178ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_ENUM(1,"Optimize for Quality") \ 179ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_DESC_END \ 180ee5417bca883d82d618e1c0b65011940253555ddRune PetersonDRI_CONF_OPT_END 1813cbfef3917451485aab723b81200156a1077a91cRune Petersen 182166a828ddfecf7fab110102783faa756081bf28aAdam JacksonPUBLIC const char __driConfigOptions[] = 1833a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_BEGIN 1843a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_PERFORMANCE 1853a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN) 1863a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS) 1873a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0) 188787fd58186cbaffde7bf930f94a1a1bfa90a23b8Aapo Tahkola DRI_CONF_MAX_TEXTURE_IMAGE_UNITS(8, 2, 8) 1893a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_MAX_TEXTURE_COORD_UNITS(8, 2, 8) 1903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32) 1913cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DISABLE_FALLBACK(false) 19262efc4ba3eb53ca75abbe9b52feabe49a5fd56b5Aapo Tahkola DRI_CONF_DISABLE_DOUBLE_SIDE_STENCIL(false) 1933a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 1943a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_QUALITY 1953a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB) 1963a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DEF_MAX_ANISOTROPY(1.0, "1.0,2.0,4.0,8.0,16.0") 1973a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_NEG_LOD_BIAS(false) 1983a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_FORCE_S3TC_ENABLE(false) 1993cbfef3917451485aab723b81200156a1077a91cRune Petersen DRI_CONF_DISABLE_S3TC(false) 2003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER) 2013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC) 2023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF) 203ee5417bca883d82d618e1c0b65011940253555ddRune Peterson DRI_CONF_FP_OPTIMIZATION(DRI_CONF_FP_OPTIMIZATION_SPEED) 2043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 2053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_DEBUG 2063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_NO_RAST(false) 2073a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt DRI_CONF_SECTION_END 2083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric AnholtDRI_CONF_END; 209ee5417bca883d82d618e1c0b65011940253555ddRune Petersonstatic const GLuint __driNConfigOptions = 18; 2105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#ifndef RADEON_DEBUG 2123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtint RADEON_DEBUG = 0; 2133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 2143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic const struct dri_debug_control debug_control[] = { 2153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"fall", DEBUG_FALLBACKS}, 2163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"tex", DEBUG_TEXTURE}, 2173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"ioctl", DEBUG_IOCTL}, 2183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"prim", DEBUG_PRIMS}, 2193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"vert", DEBUG_VERTS}, 2203a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"state", DEBUG_STATE}, 2213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"code", DEBUG_CODEGEN}, 2223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"vfmt", DEBUG_VFMT}, 2233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"vtxf", DEBUG_VFMT}, 2243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"verb", DEBUG_VERBOSE}, 2253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"dri", DEBUG_DRI}, 2263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"dma", DEBUG_DMA}, 2273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"san", DEBUG_SANITY}, 2283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"sync", DEBUG_SYNC}, 2293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"pix", DEBUG_PIXEL}, 2303a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"mem", DEBUG_MEMORY}, 2313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {"allmsg", ~DEBUG_SYNC}, /* avoid the term "sync" because the parser uses strstr */ 2323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt {NULL, 0} 2333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt}; 2343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif /* RADEON_DEBUG */ 235de08b0d7ed8af9d56bf8f82762095de3fe094c95Roland Scheidegger 2363a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif /* RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) */ 2375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtextern const struct dri_extension card_extensions[]; 2398cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int getSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ); 2415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 2426a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airliestatic int 2436a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave AirlieradeonGetParam(int fd, int param, void *value) 2446a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie{ 2456a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie int ret; 2466a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie drm_radeon_getparam_t gp; 2476a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 2486a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie gp.param = param; 2496a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie gp.value = value; 2506a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 2516a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie ret = drmCommandWriteRead( fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp)); 2526a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie return ret; 2536a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie} 2546a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 255e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsbergstatic const __DRIconfig ** 2566cb3f5c4d8618a14bb7ad1d9df10ed7e648a7b2bKristian HøgsbergradeonFillInModes( __DRIscreenPrivate *psp, 2576cb3f5c4d8618a14bb7ad1d9df10ed7e648a7b2bKristian Høgsberg unsigned pixel_bits, unsigned depth_bits, 2586cb3f5c4d8618a14bb7ad1d9df10ed7e648a7b2bKristian Høgsberg unsigned stencil_bits, GLboolean have_back_buffer ) 2598cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger{ 260e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg __DRIconfig **configs; 261e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg __GLcontextModes *m; 2628cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger unsigned depth_buffer_factor; 2638cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger unsigned back_buffer_factor; 264da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick GLenum fb_format; 265da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick GLenum fb_type; 266e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg int i; 2678cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2688cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger /* Right now GLX_SWAP_COPY_OML isn't supported, but it would be easy 2698cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * enough to add support. Basically, if a context is created with an 2708cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * fbconfig where the swap method is GLX_SWAP_COPY_OML, pageflipping 2718cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * will never be used. 2728cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger */ 2738cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger static const GLenum back_buffer_modes[] = { 2748cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger GLX_NONE, GLX_SWAP_UNDEFINED_OML /*, GLX_SWAP_COPY_OML */ 2758cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger }; 2768cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 27738b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane u_int8_t depth_bits_array[2]; 27838b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane u_int8_t stencil_bits_array[2]; 2798cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2808cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 281da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick depth_bits_array[0] = depth_bits; 282da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick depth_bits_array[1] = depth_bits; 283da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick 2848cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger /* Just like with the accumulation buffer, always provide some modes 2858cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * with a stencil buffer. It will be a sw fallback, but some apps won't 2868cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * care about that. 2878cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger */ 288da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick stencil_bits_array[0] = 0; 289da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick stencil_bits_array[1] = (stencil_bits == 0) ? 8 : stencil_bits; 2908cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 2918cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger depth_buffer_factor = ((depth_bits != 0) || (stencil_bits != 0)) ? 2 : 1; 2928cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger back_buffer_factor = (have_back_buffer) ? 2 : 1; 2938cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 294da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick if ( pixel_bits == 16 ) { 295da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_format = GL_RGB; 296da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_type = GL_UNSIGNED_SHORT_5_6_5; 297da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick } 298da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick else { 299da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_format = GL_BGRA; 300da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fb_type = GL_UNSIGNED_INT_8_8_8_8_REV; 301da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick } 302da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick 303e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg configs = driCreateConfigs(fb_format, fb_type, 304e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg depth_bits_array, stencil_bits_array, 305e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg depth_buffer_factor, 306e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg back_buffer_modes, back_buffer_factor); 307e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg if (configs == NULL) { 308da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick fprintf( stderr, "[%s:%u] Error creating FBConfig!\n", 309da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick __func__, __LINE__ ); 310da1766f12f79ae512007ab3457bdd34ec65347abIan Romanick return NULL; 3118cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3128cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 3138cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger /* Mark the visual as slow if there are "fake" stencil bits. 3148cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger */ 315e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg for (i = 0; configs[i]; i++) { 316e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg m = &configs[i]->modes; 317e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg if ((m->stencilBits != 0) && (m->stencilBits != stencil_bits)) { 3188cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger m->visualRating = GLX_SLOW_CONFIG; 3198cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3208cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger } 3218cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 322e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg return (const __DRIconfig **) configs; 3238cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger} 324c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick 32578a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 32678a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsbergstatic const __DRIallocateExtension r200AllocateExtension = { 327ccff0cb26378ce370fc8697a2a2ada138d2e119eKristian Høgsberg { __DRI_ALLOCATE, __DRI_ALLOCATE_VERSION }, 32878a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg r200AllocateMemoryMESA, 32978a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg r200FreeMemoryMESA, 33078a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg r200GetMemoryOffsetMESA 33178a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg}; 332badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzer 333badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzerstatic const __DRItexOffsetExtension r200texOffsetExtension = { 334badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzer { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 335badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzer r200SetTexOffset, 336badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzer}; 337f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg#endif 33878a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg 339f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 340f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsbergstatic const __DRItexOffsetExtension r300texOffsetExtension = { 341ccff0cb26378ce370fc8697a2a2ada138d2e119eKristian Høgsberg { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION }, 342f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg r300SetTexOffset, 343f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg}; 34478a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg#endif 34578a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg 3465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Create the device specific screen private data struct. 3475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 34867a8decffeada987d10da616d72c1e6ec473dfa5Brian Paulstatic radeonScreenPtr 34967a8decffeada987d10da616d72c1e6ec473dfa5Brian PaulradeonCreateScreen( __DRIscreenPrivate *sPriv ) 3505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 3515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonScreenPtr screen; 3525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; 35399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane unsigned char *RADEONMMIO; 354efaf90b03e8b69e04909bce071f8ef6b65cc0e9dKristian Høgsberg int i; 3553bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie int ret; 3563bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie uint32_t temp; 3575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 358dabec11d277e68b6940e741651e61102767240b9Alan Hourihane if (sPriv->devPrivSize != sizeof(RADEONDRIRec)) { 359dabec11d277e68b6940e741651e61102767240b9Alan Hourihane fprintf(stderr,"\nERROR! sizeof(RADEONDRIRec) does not match passed size from device driver\n"); 360dabec11d277e68b6940e741651e61102767240b9Alan Hourihane return GL_FALSE; 361dabec11d277e68b6940e741651e61102767240b9Alan Hourihane } 3625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* Allocate the private area */ 3645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen = (radeonScreenPtr) CALLOC( sizeof(*screen) ); 3655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !screen ) { 3665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: Could not allocate memory for screen structure", 3675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __FUNCTION__); 3685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 3695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3713a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if DO_DEBUG && RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 3723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt RADEON_DEBUG = driParseDebugString(getenv("RADEON_DEBUG"), debug_control); 3733a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 3743a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 375bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl /* parse information in __driConfigOptions */ 376d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul driParseOptionInfo (&screen->optionCache, 377d450d0b0e228e5b16c04b2a1acb9ea549aa690f2Brian Paul __driConfigOptions, __driNConfigOptions); 3785df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 3795df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul /* This is first since which regions we map depends on whether or 3805df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * not we are using a PCI card. 3815df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 3826a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie screen->card_type = (dri_priv->IsPCI ? RADEON_CARD_PCI : RADEON_CARD_AGP); 383bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl { 3845df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul int ret; 3856a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BUFFER_OFFSET, 3866a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie &screen->gart_buffer_offset); 3876a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie 3885df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (ret) { 389bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl FREE( screen ); 390ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BUFFER_OFFSET): %d\n", ret); 3915df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 3925df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 3935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 394f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_GART_BASE, 3956a9f0a27c3853738e4bbfb33e8b20464a7d92923Dave Airlie &screen->gart_base); 396f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie if (ret) { 397f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie FREE( screen ); 398f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_GART_BASE): %d\n", ret); 399f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie return NULL; 400f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie } 401f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie 402f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_IRQ_NR, 403f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie &screen->irq); 404f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie if (ret) { 405f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie FREE( screen ); 406f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_IRQ_NR): %d\n", ret); 407f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie return NULL; 4085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 409efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsCubeMapsR200 = (sPriv->drm_version.minor >= 7); 410efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsBlendColor = (sPriv->drm_version.minor >= 11); 411efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsTriPerf = (sPriv->drm_version.minor >= 16); 412efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsFragShader = (sPriv->drm_version.minor >= 18); 413efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsPointSprites = (sPriv->drm_version.minor >= 13); 414efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsCubeMapsR100 = (sPriv->drm_version.minor >= 15); 415efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg screen->drmSupportsVertexProgram = (sPriv->drm_version.minor >= 25); 4165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.handle = dri_priv->registerHandle; 4195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.size = dri_priv->registerSize; 4205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( drmMap( sPriv->fd, 4215df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.handle, 4225df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->mmio.size, 4235df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &screen->mmio.map ) ) { 4245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 4255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: drmMap failed\n", __FUNCTION__ ); 4265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 42999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane RADEONMMIO = screen->mmio.map; 43099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 4315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.handle = dri_priv->statusHandle; 4325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.size = dri_priv->statusSize; 4335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( drmMap( sPriv->fd, 4345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.handle, 4355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->status.size, 4365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul &screen->status.map ) ) { 4375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 4385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 4395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: drmMap (2) failed\n", __FUNCTION__ ); 4405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 44238b317d508a2a3a4cc6d700ebca80c3b06c913e2Alan Hourihane screen->scratch = (__volatile__ u_int32_t *) 4435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ((GLubyte *)screen->status.map + RADEON_SCRATCH_REG_OFFSET); 4445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->buffers = drmMapBufs( sPriv->fd ); 4465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !screen->buffers ) { 4475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->status.map, screen->status.size ); 4485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 4495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 4505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __driUtilMessage("%s: drmMapBufs failed\n", __FUNCTION__ ); 4515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 454bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { 455bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.handle = dri_priv->gartTexHandle; 456bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.size = dri_priv->gartTexMapSize; 4575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( drmMap( sPriv->fd, 458bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.handle, 459bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl screen->gartTextures.size, 460bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl (drmAddressPtr)&screen->gartTextures.map ) ) { 4615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmapBufs( screen->buffers ); 4625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->status.map, screen->status.size ); 4635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 4645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 465bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl __driUtilMessage("%s: drmMap failed for GART texture area\n", __FUNCTION__); 4665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return NULL; 4675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 468bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 469f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie screen->gart_texture_offset = dri_priv->gartTexOffset + screen->gart_base; 4705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 4715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 4723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = 0; 4733a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt /* XXX: add more chipsets */ 4745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul switch ( dri_priv->deviceID ) { 4753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_LY: 4763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_LZ: 4773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_QY: 4783a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RADEON_QZ: 4793a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RN50_515E: 4803a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RN50_5969: 4813a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV100; 4823a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4833a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4843a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS100_4136: 4853a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS100_4336: 4863a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RS100; 4873a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4883a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4893a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS200_4137: 4903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS200_4337: 4913a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS250_4237: 4923a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS250_4437: 4933a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RS200; 4943a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 4953a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 4965df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QD: 4975df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QE: 4985df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QF: 4995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_QG: 500de7b071b5534fc423a056abd521de8bf9120f89eRoland Scheidegger /* all original radeons (7200) presumably have a stencil op bug */ 5013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R100; 5023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL; 5033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RV200_QW: 506de08b0d7ed8af9d56bf8f82762095de3fe094c95Roland Scheidegger case PCI_CHIP_RV200_QX: 5075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul case PCI_CHIP_RADEON_LW: 508de08b0d7ed8af9d56bf8f82762095de3fe094c95Roland Scheidegger case PCI_CHIP_RADEON_LX: 5093a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV200; 5103a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_BB: 5143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_BC: 5153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_QH: 5163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_QL: 5173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R200_QM: 5183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R200; 5193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul break; 5213a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5223a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_If: 5233a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Ig: 5243a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Ld: 5253a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Lf: 5263a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV250_Lg: 5273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV250; 5283a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL; 5293a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5303a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5313a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5960: 5323a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5961: 5333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5962: 5343a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5964: 5353a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5965: 5363a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5C61: 5373a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV280_5C63: 5383a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV280; 5393a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5403a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5413a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5423a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS300_5834: 5433a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RS300_5835: 5444e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS350_7834: 5454e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS350_7835: 5463a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RS300; 5473a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 54965c4ced1ccea7ff88123296b7f0587faa6f23eefAlex Deucher /* 9500 with 1 pipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */ 5503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AD: 55165c4ced1ccea7ff88123296b7f0587faa6f23eefAlex Deucher screen->chip_family = CHIP_FAMILY_RV350; 55265c4ced1ccea7ff88123296b7f0587faa6f23eefAlex Deucher screen->chip_flags = RADEON_CHIPSET_TCL; 55365c4ced1ccea7ff88123296b7f0587faa6f23eefAlex Deucher break; 5543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AE: 5553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AF: 5563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_AG: 5573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_ND: 5583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_NE: 5593a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_NF: 5603a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R300_NG: 5613a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R300; 5623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5653a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AP: 5663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AQ: 5673a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AR: 5683a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AS: 5693a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AT: 5703a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AV: 5713a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_AU: 5723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NP: 5733a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NQ: 5743a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NR: 5753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NS: 5763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NT: 5773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV350_NV: 5783a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV350; 5793a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5803a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5813a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5823a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AH: 5833a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AI: 5843a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AJ: 5853a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_AK: 5863a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_NH: 5873a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_NI: 5883a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R360_NJ: 5893a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R350_NK: 5903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R350; 5913a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 5923a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 5933a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 5943a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5460: 5954e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV370_5462: 5963a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5464: 5973a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B60: 5983a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B62: 5994e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV370_5B63: 6003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B64: 6013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_RV370_5B65: 60280efe27560134510dce88a52729e5a3d93e8e275Alex Deucher case PCI_CHIP_RV370_5657: 6034e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3150: 6044e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3152: 6054e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3154: 6064e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3E50: 6074e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV380_3E54: 6083a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_RV380; 6093a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 6103a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 6113a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 6123a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JN: 6133a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JH: 6143a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JI: 6153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JJ: 6163a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JK: 6173a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JL: 6183a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JM: 6193a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JO: 6203a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt case PCI_CHIP_R420_JP: 6214e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R420_JT: 6224e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B49: 6234e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B4A: 6244e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B4B: 6254e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R481_4B4C: 6264e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UH: 6274e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UI: 6284e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UJ: 6294e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UK: 6304e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554C: 6314e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554D: 6324e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554E: 6334e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_554F: 6344e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_5550: 6354e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UQ: 6364e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UR: 6374e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_UT: 6384e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_5D48: 6394e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_5D49: 6404e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R430_5D4A: 6414e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4C: 6424e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4D: 6434e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4E: 6444e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D4F: 6454e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D50: 6464e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R480_5D52: 6474e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_R423_5D57: 6483a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_family = CHIP_FAMILY_R420; 6493a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags = RADEON_CHIPSET_TCL; 6503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt break; 6513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 6520b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher /* RV410 SE chips have half the pipes of regular RV410 */ 6530b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher case PCI_CHIP_RV410_5E4C: 6540b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher case PCI_CHIP_RV410_5E4F: 6550b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher screen->chip_family = CHIP_FAMILY_RV380; 6560b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher screen->chip_flags = RADEON_CHIPSET_TCL; 6570b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher break; 6580b7e0f81591c0b70452ff9250af9b145e8c15adfAlex Deucher 6594e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_564A: 6604e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_564B: 6614e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_564F: 6624e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5652: 6634e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5653: 6644e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E48: 6654e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4A: 6664e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4B: 6674e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RV410_5E4D: 6684e7766992607db215430ee388751f32692401c0aRoland Scheidegger screen->chip_family = CHIP_FAMILY_RV410; 6694e7766992607db215430ee388751f32692401c0aRoland Scheidegger screen->chip_flags = RADEON_CHIPSET_TCL; 6704e7766992607db215430ee388751f32692401c0aRoland Scheidegger break; 6714e7766992607db215430ee388751f32692401c0aRoland Scheidegger 6724e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS480_5954: 6734e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS480_5955: 6744e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS482_5974: 6754e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS482_5975: 6764e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS400_5A41: 6774e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RS400_5A42: 6784e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RC410_5A61: 6794e7766992607db215430ee388751f32692401c0aRoland Scheidegger case PCI_CHIP_RC410_5A62: 6804e7766992607db215430ee388751f32692401c0aRoland Scheidegger screen->chip_family = CHIP_FAMILY_RS400; 6818130a4fe982a7583e439a1fac61c5050f85bdf46Dave Airlie fprintf(stderr, "Warning, xpress200 detected.\n"); 6824e7766992607db215430ee388751f32692401c0aRoland Scheidegger break; 6834e7766992607db215430ee388751f32692401c0aRoland Scheidegger 6843bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie case PCI_CHIP_RS690_791E: 6853bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie screen->chip_family = CHIP_FAMILY_RS690; 6863bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie fprintf(stderr, "Warning, RS690 detected, 3D support is incomplete.\n"); 6873bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie break; 6883bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie 6893a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt default: 6903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt fprintf(stderr, "unknown chip id 0x%x, can't guess.\n", 6913a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt dri_priv->deviceID); 6923a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return NULL; 6935df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 6949cb82f7917b11288169146035700b992b86a7ec2Aapo Tahkola if ((screen->chip_family == CHIP_FAMILY_R350 || screen->chip_family == CHIP_FAMILY_R300) && 695efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg sPriv->ddx_version.minor < 2) { 6969cb82f7917b11288169146035700b992b86a7ec2Aapo Tahkola fprintf(stderr, "xf86-video-ati-6.6.2 or newer needed for Radeon 9500/9700/9800 cards.\n"); 6979cb82f7917b11288169146035700b992b86a7ec2Aapo Tahkola return NULL; 698fb0175db931e1b1457b9b7ea2faa44f07d549266Aapo Tahkola } 6995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7003a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (screen->chip_family <= CHIP_FAMILY_RS200) 7018bc4dae67e083c6415c07e6ff77e700f7395dc9eRoland Scheidegger screen->chip_flags |= RADEON_CLASS_R100; 7023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt else if (screen->chip_family <= CHIP_FAMILY_RV280) 7033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags |= RADEON_CLASS_R200; 7043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt else 7053a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt screen->chip_flags |= RADEON_CLASS_R300; 7063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 7075df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->cpp = dri_priv->bpp / 8; 7085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->AGPMode = dri_priv->AGPMode; 7095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7103bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie ret = radeonGetParam( sPriv->fd, RADEON_PARAM_FB_LOCATION, 7113bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie &temp); 7123bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie if (ret) { 7133bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie if (screen->chip_family < CHIP_FAMILY_RS690) 7143bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff) << 16; 7153bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie else { 7163bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie FREE( screen ); 7173bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie fprintf(stderr, "Unable to get fb location need newer drm\n"); 7183bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie return NULL; 7193bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie } 7203bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie } else { 7213bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie screen->fbLocation = (temp & 0xffff) << 16; 7223bfef648000e544a3505feea5bda7aa9f184f304Dave Airlie } 72399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 724efd03a278ae55b454509e9659c42899133983ebdKristian Høgsberg if ( sPriv->drm_version.minor >= 10 ) { 725ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl drm_radeon_setparam_t sp; 72699ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 72799ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane sp.param = RADEON_SETPARAM_FB_LOCATION; 72899ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane sp.value = screen->fbLocation; 72999ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 73099ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, 73199ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane &sp, sizeof( sp ) ); 73299ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane } 73399ef0a03292e7dc6aa2465aaaa620f394d2c286bAlan Hourihane 7345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->frontOffset = dri_priv->frontOffset; 7355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->frontPitch = dri_priv->frontPitch; 7365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->backOffset = dri_priv->backOffset; 7375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->backPitch = dri_priv->backPitch; 7385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->depthOffset = dri_priv->depthOffset; 7395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->depthPitch = dri_priv->depthPitch; 7405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 741a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger /* Check if ddx has set up a surface reg to cover depth buffer */ 7423d51c7900105a99fc30a4318080fd4cc373c8eecRoland Scheidegger screen->depthHasSurface = (sPriv->ddx_version.major > 4) || 7433d51c7900105a99fc30a4318080fd4cc373c8eecRoland Scheidegger /* these chips don't use tiled z without hyperz. So always pretend 7443d51c7900105a99fc30a4318080fd4cc373c8eecRoland Scheidegger we have set up a surface which will cause linear reads/writes */ 7453d51c7900105a99fc30a4318080fd4cc373c8eecRoland Scheidegger ((screen->chip_family & RADEON_CLASS_R100) && 7463d51c7900105a99fc30a4318080fd4cc373c8eecRoland Scheidegger !(screen->chip_flags & RADEON_CHIPSET_TCL)); 747a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger 7489790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer if ( dri_priv->textureSize == 0 ) { 7499790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; 7509790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->gartTexMapSize; 7519790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 7529790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer dri_priv->log2GARTTexGran; 7539790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer } else { 7549790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texOffset[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureOffset 7559790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer + screen->fbLocation; 7569790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->texSize[RADEON_LOCAL_TEX_HEAP] = dri_priv->textureSize; 7579790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer screen->logTexGranularity[RADEON_LOCAL_TEX_HEAP] = 7589790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer dri_priv->log2TexGran; 7599790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer } 7605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 7619790e641ef24859833c01a1fa7004a1c2b73ddd1Michel Dänzer if ( !screen->gartTextures.map || dri_priv->textureSize == 0 762bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl || getenv( "RADEON_GARTTEXTURING_FORCE_DISABLE" ) ) { 7635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->numTexHeaps = RADEON_NR_TEX_HEAPS - 1; 764ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texOffset[RADEON_GART_TEX_HEAP] = 0; 765ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texSize[RADEON_GART_TEX_HEAP] = 0; 766ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 0; 7675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } else { 7685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->numTexHeaps = RADEON_NR_TEX_HEAPS; 769ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texOffset[RADEON_GART_TEX_HEAP] = screen->gart_texture_offset; 770ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->texSize[RADEON_GART_TEX_HEAP] = dri_priv->gartTexMapSize; 771ae4a1cc0666860bf5cc37a5cb549afc9aa5448b0Jon Smirl screen->logTexGranularity[RADEON_GART_TEX_HEAP] = 772bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl dri_priv->log2GARTTexGran; 7735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 774aaebfc88c08c79cd70f1e0d1d262a25e9ded47d1Jon Smirl 775efaf90b03e8b69e04909bce071f8ef6b65cc0e9dKristian Høgsberg i = 0; 776efaf90b03e8b69e04909bce071f8ef6b65cc0e9dKristian Høgsberg screen->extensions[i++] = &driCopySubBufferExtension.base; 777a7a0a2beb54dcb78d7e0ab64cf2f5a6ede8191a4Kristian Høgsberg screen->extensions[i++] = &driFrameTrackingExtension.base; 778f968f67e6214416f04b8875ce59a94a02f464c81Kristian Høgsberg screen->extensions[i++] = &driReadDrawableExtension; 779f968f67e6214416f04b8875ce59a94a02f464c81Kristian Høgsberg 780106a6f29bbdc71982afd629bdf89369cefd1459eKristian Høgsberg if ( screen->irq != 0 ) { 781106a6f29bbdc71982afd629bdf89369cefd1459eKristian Høgsberg screen->extensions[i++] = &driSwapControlExtension.base; 782106a6f29bbdc71982afd629bdf89369cefd1459eKristian Høgsberg screen->extensions[i++] = &driMediaStreamCounterExtension.base; 783f7c9eafa856623d5ce72afb8b20b7ccbcc3e671dIan Romanick } 784c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick 7853a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 78678a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg if (IS_R200_CLASS(screen)) 78778a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg screen->extensions[i++] = &r200AllocateExtension.base; 788badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzer 789badc061a65b8e8b3d92eb4a45bd9eb4191eaaf62Michel Dänzer screen->extensions[i++] = &r200texOffsetExtension.base; 7903a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 7913a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 792f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 793f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg screen->extensions[i++] = &r300texOffsetExtension.base; 794f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg#endif 795f29f0ae8383888a6493b615edc3bab254cf6df39Kristian Høgsberg 79678a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg screen->extensions[i++] = NULL; 79778a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg sPriv->extensions = screen->extensions; 79878a6aa57a0155d72280dd91c05513c847bf76f3bKristian Høgsberg 7995df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->driScreen = sPriv; 8005df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul screen->sarea_priv_offset = dri_priv->sarea_priv_offset; 8015df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return screen; 8025df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8035df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8045df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Destroy the device specific screen private data struct. 8055df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 80667a8decffeada987d10da616d72c1e6ec473dfa5Brian Paulstatic void 80767a8decffeada987d10da616d72c1e6ec473dfa5Brian PaulradeonDestroyScreen( __DRIscreenPrivate *sPriv ) 8085df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 8095df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonScreenPtr screen = (radeonScreenPtr)sPriv->private; 8105df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8115df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (!screen) 8125df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return; 8135df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 814bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl if ( screen->gartTextures.map ) { 815bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl drmUnmap( screen->gartTextures.map, screen->gartTextures.size ); 8165df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8175df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmapBufs( screen->buffers ); 8185df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->status.map, screen->status.size ); 8195df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul drmUnmap( screen->mmio.map, screen->mmio.size ); 8205df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 821bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl /* free all option information */ 822bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl driDestroyOptionInfo (&screen->optionCache); 823bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl 8245df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul FREE( screen ); 8255df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sPriv->private = NULL; 8265df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8275df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8285df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8295df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/* Initialize the driver specific screen private data. 8305df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8315df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic GLboolean 8325df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulradeonInitDriver( __DRIscreenPrivate *sPriv ) 8335df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 8345df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sPriv->private = (void *) radeonCreateScreen( sPriv ); 8355df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( !sPriv->private ) { 8365df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonDestroyScreen( sPriv ); 8375df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return GL_FALSE; 8385df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return GL_TRUE; 8415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 8425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 8448cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger/** 845e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul * Create the Mesa framebuffer and renderbuffers for a given window/drawable. 8468cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * 8478cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * \todo This function (and its interface) will need to be updated to support 8488cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger * pbuffers. 8495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 8505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic GLboolean 8515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulradeonCreateBuffer( __DRIscreenPrivate *driScrnPriv, 8525df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul __DRIdrawablePrivate *driDrawPriv, 8535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const __GLcontextModes *mesaVis, 8545df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul GLboolean isPixmap ) 8555df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 856e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private; 857e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 8585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if (isPixmap) { 8595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return GL_FALSE; /* not implemented */ 8605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 8615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul else { 8625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swDepth = GL_FALSE; 8635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swAlpha = GL_FALSE; 8645df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swAccum = mesaVis->accumRedBits > 0; 8655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul const GLboolean swStencil = mesaVis->stencilBits > 0 && 8665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul mesaVis->depthBits != 24; 867e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul struct gl_framebuffer *fb = _mesa_create_framebuffer(mesaVis); 868e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 869982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* front color renderbuffer */ 870e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul { 871e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *frontRb 87261ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_RGBA, 87361ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->frontOffset, 87461ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 87561ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->frontOffset, screen->frontPitch, 87661ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 877e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(frontRb, mesaVis); 878e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_FRONT_LEFT, &frontRb->Base); 879e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 880e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 881982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* back color renderbuffer */ 882e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if (mesaVis->doubleBufferMode) { 883e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *backRb 88461ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_RGBA, 88561ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->backOffset, 88661ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 88761ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->backOffset, screen->backPitch, 88861ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 889e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(backRb, mesaVis); 890e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_BACK_LEFT, &backRb->Base); 891e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 892e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 893982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* depth renderbuffer */ 894e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if (mesaVis->depthBits == 16) { 895e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *depthRb 89661ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_DEPTH_COMPONENT16, 89761ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->depthOffset, 89861ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 89961ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->depthOffset, screen->depthPitch, 90061ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 901e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(depthRb, mesaVis); 902e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 903982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul depthRb->depthHasSurface = screen->depthHasSurface; 904e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 905e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul else if (mesaVis->depthBits == 24) { 906e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *depthRb 90761ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_DEPTH_COMPONENT24, 90861ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->depthOffset, 90961ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 91061ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->depthOffset, screen->depthPitch, 91161ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 912e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(depthRb, mesaVis); 913e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &depthRb->Base); 914982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul depthRb->depthHasSurface = screen->depthHasSurface; 915e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 916e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 917982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul /* stencil renderbuffer */ 918e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul if (mesaVis->stencilBits > 0 && !swStencil) { 919e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driRenderbuffer *stencilRb 92061ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul = driNewRenderbuffer(GL_STENCIL_INDEX8_EXT, 92161ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driScrnPriv->pFB + screen->depthOffset, 92261ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->cpp, 92361ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul screen->depthOffset, screen->depthPitch, 92461ba6b5a74625a01e07ae267c6e4ebf192434e40Brian Paul driDrawPriv); 925e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul radeonSetSpanFunctions(stencilRb, mesaVis); 926e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_renderbuffer(fb, BUFFER_STENCIL, &stencilRb->Base); 927350a1676357301f3d103b6d16d01c766644bf872Brian Paul stencilRb->depthHasSurface = screen->depthHasSurface; 928e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul } 929e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul 930e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul _mesa_add_soft_renderbuffers(fb, 931e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul GL_FALSE, /* color */ 932e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swDepth, 933e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swStencil, 934e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swAccum, 935e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul swAlpha, 936e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul GL_FALSE /* aux */); 937e4b2356c07d31fbeeabb13b2fb47db703b473080Brian Paul driDrawPriv->driverPrivate = (void *) fb; 938982e8e4d5c95e9e9040b4b70d7322a2a8a9396d9Brian Paul 9395df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return (driDrawPriv->driverPrivate != NULL); 9405df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 9415df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 9425df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9445df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic void 9455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulradeonDestroyBuffer(__DRIdrawablePrivate *driDrawPriv) 9465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 947a510bc3ee1a696da120c09ee4ec33dc033f671acBrian _mesa_unreference_framebuffer((GLframebuffer **)(&(driDrawPriv->driverPrivate))); 9485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 9495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 9503a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 9513a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt/** 9523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt * Choose the appropriate CreateContext function based on the chipset. 9533a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt * Eventually, all drivers will go through this process. 9543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt */ 9553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic GLboolean radeonCreateContext(const __GLcontextModes * glVisual, 9563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt __DRIcontextPrivate * driContextPriv, 9573a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt void *sharedContextPriv) 9583a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt{ 9593a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv; 9603a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private); 9613a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9623a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (IS_R300_CLASS(screen)) 9633a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return r300CreateContext(glVisual, driContextPriv, sharedContextPriv); 9643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return GL_FALSE; 9653a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt} 9663a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9673a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt/** 9683a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt * Choose the appropriate DestroyContext function based on the chipset. 9693a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt */ 9703a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholtstatic void radeonDestroyContext(__DRIcontextPrivate * driContextPriv) 9713a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt{ 9723a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate; 9733a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9743a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if (IS_R300_CLASS(radeon->radeonScreen)) 9753a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt return r300DestroyContext(driContextPriv); 9763a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt} 9773a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9783a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 9793a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 9803a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 981bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl/** 98264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * This is the driver specific part of the createNewScreen entry point. 98364106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * 98464106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * \todo maybe fold this into intelInitDriver 985bcc6eddd335e97d49ed2ef3a1440f94d58dce12dJon Smirl * 98664106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * \return the __GLcontextModes supported by this driver 9875df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 988e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsbergstatic const __DRIconfig ** 989e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian HøgsbergradeonInitScreen(__DRIscreenPrivate *psp) 9905df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 9913a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON 9923a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const char *driver_name = "Radeon"; 993a205137423e42010a025c70b05af98a6c0564f28Roland Scheidegger static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 9945b98ada88071a752b6000756949a1951183cdd0bIan Romanick static const __DRIversion dri_expected = { 4, 0, 0 }; 995f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie static const __DRIversion drm_expected = { 1, 6, 0 }; 9963a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 9973a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const char *driver_name = "R200"; 9983a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 9993a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIversion dri_expected = { 4, 0, 0 }; 1000f8ca99d697e428936cea0c7c7fc03352cf909cc6Dave Airlie static const __DRIversion drm_expected = { 1, 6, 0 }; 10013a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R300) 10023a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const char *driver_name = "R300"; 10033a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIutilversion2 ddx_expected = { 4, 5, 0, 0 }; 10043a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt static const __DRIversion dri_expected = { 4, 0, 0 }; 1005dba9c0bafd889d30f044d1e2e870b07ed60efd0aAapo Tahkola static const __DRIversion drm_expected = { 1, 24, 0 }; 10063a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 100764106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg RADEONDRIPtr dri_priv = (RADEONDRIPtr) psp->pDevPriv; 10085f1ba3e21b62cee1a4f900a2e6964728f3eeea9bIan Romanick 10093a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt if ( ! driCheckDriDdxDrmVersions3( driver_name, 101064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg &psp->dri_version, & dri_expected, 101164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg &psp->ddx_version, & ddx_expected, 101264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg &psp->drm_version, & drm_expected ) ) { 10135b98ada88071a752b6000756949a1951183cdd0bIan Romanick return NULL; 10145b98ada88071a752b6000756949a1951183cdd0bIan Romanick } 10153a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt 101664106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg /* Calling driInitExtensions here, with a NULL context pointer, 101764106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * does not actually enable the extensions. It just makes sure 101864106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * that all the dispatch offsets for all the extensions that 101964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * *might* be enables are known. This is needed because the 102064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * dispatch offsets need to be known when _mesa_context_create 102164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * is called, but we can't enable the extensions until we have a 102264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * context pointer. 102364106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * 102464106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg * Hello chicken. Hello egg. How are you two today? 102564106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg */ 102664106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitExtensions( NULL, card_extensions, GL_FALSE ); 10273a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 102864106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitExtensions( NULL, blend_extensions, GL_FALSE ); 102964106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitSingleExtension( NULL, ARB_vp_extension ); 103064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitSingleExtension( NULL, NV_vp_extension ); 103164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitSingleExtension( NULL, ATI_fs_extension ); 103264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg driInitExtensions( NULL, point_extensions, GL_FALSE ); 10333a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 10348cff2ede6eec1dd480bb8a4835b6985955514d87Roland Scheidegger 103564106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg if (!radeonInitDriver(psp)) 103664106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg return NULL; 103764106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg 10386cb3f5c4d8618a14bb7ad1d9df10ed7e648a7b2bKristian Høgsberg return radeonFillInModes( psp, 10396cb3f5c4d8618a14bb7ad1d9df10ed7e648a7b2bKristian Høgsberg dri_priv->bpp, 104064106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg (dri_priv->bpp == 16) ? 16 : 24, 104164106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg (dri_priv->bpp == 16) ? 0 : 8, 104264106d0d9aeefa6974317042b6bc3e5eaabac5a2Kristian Høgsberg (dri_priv->backOffset != dri_priv->depthOffset) ); 10435df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1044c39bf5e273a4995a279ae2af59fc29e06ab47e29Ian Romanick 10455df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10465df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul/** 10475df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul * Get information about previous buffer swaps. 10485df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul */ 10495df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paulstatic int 10505df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian PaulgetSwapInfo( __DRIdrawablePrivate *dPriv, __DRIswapInfo * sInfo ) 10515df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul{ 10523a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 10535df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul radeonContextPtr rmesa; 10543a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#elif RADEON_COMMON && defined(RADEON_COMMON_FOR_R200) 10553a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt r200ContextPtr rmesa; 10563a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt#endif 10575df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10585df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL) 10595df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul || (dPriv->driContextPriv->driverPrivate == NULL) 10605df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul || (sInfo == NULL) ) { 10615df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return -1; 10625df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul } 10635df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10643a5626cb846ad767fe1c38fe35ebe4df3e3a0454Eric Anholt rmesa = dPriv->driContextPriv->driverPrivate; 10655df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_count = rmesa->swap_count; 10665df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_ust = rmesa->swap_ust; 10675df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_missed_count = rmesa->swap_missed_count; 10685df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10695df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0) 10705df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul ? driCalculateSwapUsage( dPriv, 0, rmesa->swap_missed_ust ) 10715df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul : 0.0; 10725df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul 10735df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul return 0; 10745df82c82bd53db90eb72c5aad4dd20cf6f1116b1Brian Paul} 1075e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg 1076e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg#if !RADEON_COMMON || (RADEON_COMMON && defined(RADEON_COMMON_FOR_R300)) 1077e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsbergconst struct __DriverAPIRec driDriverAPI = { 1078e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .InitScreen = radeonInitScreen, 1079e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .DestroyScreen = radeonDestroyScreen, 1080e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .CreateContext = radeonCreateContext, 1081e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .DestroyContext = radeonDestroyContext, 1082e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .CreateBuffer = radeonCreateBuffer, 1083e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .DestroyBuffer = radeonDestroyBuffer, 1084e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .SwapBuffers = radeonSwapBuffers, 1085e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .MakeCurrent = radeonMakeCurrent, 1086e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .UnbindContext = radeonUnbindContext, 1087e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .GetSwapInfo = getSwapInfo, 1088e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .GetDrawableMSC = driDrawableGetMSC32, 1089e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .WaitForMSC = driWaitForMSC32, 1090e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .WaitForSBC = NULL, 1091e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .SwapBuffersMSC = NULL, 1092e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .CopySubBuffer = radeonCopySubBuffer, 1093e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg}; 1094e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg#else 1095e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsbergconst struct __DriverAPIRec driDriverAPI = { 1096e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .InitScreen = radeonInitScreen, 1097e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .DestroyScreen = radeonDestroyScreen, 1098e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .CreateContext = r200CreateContext, 1099e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .DestroyContext = r200DestroyContext, 1100e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .CreateBuffer = radeonCreateBuffer, 1101e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .DestroyBuffer = radeonDestroyBuffer, 1102e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .SwapBuffers = r200SwapBuffers, 1103e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .MakeCurrent = r200MakeCurrent, 1104e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .UnbindContext = r200UnbindContext, 1105e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .GetSwapInfo = getSwapInfo, 1106e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .GetDrawableMSC = driDrawableGetMSC32, 1107e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .WaitForMSC = driWaitForMSC32, 1108e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .WaitForSBC = NULL, 1109e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .SwapBuffersMSC = NULL, 1110e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg .CopySubBuffer = r200CopySubBuffer, 1111e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg}; 1112e82dd8c6e1fa2fff5b960de26961080ba5e9651dKristian Høgsberg#endif 1113