radeon_screen.c revision 3996ed555e0a024051e4d161c8d31b2530d8cdc5 
1/**************************************************************************
2
3Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4                     VA Linux Systems Inc., Fremont, California.
5
6All Rights Reserved.
7
8Permission is hereby granted, free of charge, to any person obtaining
9a copy of this software and associated documentation files (the
10"Software"), to deal in the Software without restriction, including
11without limitation the rights to use, copy, modify, merge, publish,
12distribute, sublicense, and/or sell copies of the Software, and to
13permit persons to whom the Software is furnished to do so, subject to
14the following conditions:
15
16The above copyright notice and this permission notice (including the
17next paragraph) shall be included in all copies or substantial
18portions of the Software.
19
20THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28**************************************************************************/
29
30/**
31 * \file radeon_screen.c
32 * Screen initialization functions for the Radeon driver.
33 *
34 * \author Kevin E. Martin <martin@valinux.com>
35 * \author  Gareth Hughes <gareth@valinux.com>
36 */
37
38#include <errno.h>
39#include "main/glheader.h"
40#include "main/imports.h"
41#include "main/mtypes.h"
42#include "main/framebuffer.h"
43#include "main/renderbuffer.h"
44#include "main/fbobject.h"
45
46#define STANDALONE_MMIO
47#include "radeon_chipset.h"
48#include "radeon_macros.h"
49#include "radeon_screen.h"
50#include "radeon_common.h"
51#include "radeon_common_context.h"
52#if defined(RADEON_R100)
53#include "radeon_context.h"
54#include "radeon_tex.h"
55#elif defined(RADEON_R200)
56#include "r200_context.h"
57#include "r200_tex.h"
58#endif
59
60#include "utils.h"
61#include "vblank.h"
62
63#include "radeon_bocs_wrapper.h"
64
65#include "GL/internal/dri_interface.h"
66
67/* Radeon configuration
68 */
69#include "xmlpool.h"
70
71#define DRI_CONF_COMMAND_BUFFER_SIZE(def,min,max) \
72DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":" # max ) \
73        DRI_CONF_DESC(en,"Size of command buffer (in KB)") \
74        DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
75DRI_CONF_OPT_END
76
77#if defined(RADEON_R100)	/* R100 */
78PUBLIC const char __driConfigOptions[] =
79DRI_CONF_BEGIN
80    DRI_CONF_SECTION_PERFORMANCE
81        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
82        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
83        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
84        DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
85        DRI_CONF_HYPERZ(false)
86        DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
87    DRI_CONF_SECTION_END
88    DRI_CONF_SECTION_QUALITY
89        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
90        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
91        DRI_CONF_NO_NEG_LOD_BIAS(false)
92        DRI_CONF_FORCE_S3TC_ENABLE(false)
93        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
94        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
95        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
96        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
97    DRI_CONF_SECTION_END
98    DRI_CONF_SECTION_DEBUG
99        DRI_CONF_NO_RAST(false)
100    DRI_CONF_SECTION_END
101DRI_CONF_END;
102static const GLuint __driNConfigOptions = 15;
103
104#elif defined(RADEON_R200)
105
106PUBLIC const char __driConfigOptions[] =
107DRI_CONF_BEGIN
108    DRI_CONF_SECTION_PERFORMANCE
109        DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
110        DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
111        DRI_CONF_VBLANK_MODE(DRI_CONF_VBLANK_DEF_INTERVAL_0)
112        DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
113        DRI_CONF_HYPERZ(false)
114        DRI_CONF_COMMAND_BUFFER_SIZE(8, 8, 32)
115    DRI_CONF_SECTION_END
116    DRI_CONF_SECTION_QUALITY
117        DRI_CONF_TEXTURE_DEPTH(DRI_CONF_TEXTURE_DEPTH_FB)
118        DRI_CONF_DEF_MAX_ANISOTROPY(1.0,"1.0,2.0,4.0,8.0,16.0")
119        DRI_CONF_NO_NEG_LOD_BIAS(false)
120        DRI_CONF_FORCE_S3TC_ENABLE(false)
121        DRI_CONF_COLOR_REDUCTION(DRI_CONF_COLOR_REDUCTION_DITHER)
122        DRI_CONF_ROUND_MODE(DRI_CONF_ROUND_TRUNC)
123        DRI_CONF_DITHER_MODE(DRI_CONF_DITHER_XERRORDIFF)
124        DRI_CONF_ALLOW_LARGE_TEXTURES(2)
125        DRI_CONF_TEXTURE_BLEND_QUALITY(1.0,"0.0:1.0")
126    DRI_CONF_SECTION_END
127    DRI_CONF_SECTION_DEBUG
128        DRI_CONF_NO_RAST(false)
129    DRI_CONF_SECTION_END
130    DRI_CONF_SECTION_SOFTWARE
131        DRI_CONF_NV_VERTEX_PROGRAM(false)
132    DRI_CONF_SECTION_END
133DRI_CONF_END;
134static const GLuint __driNConfigOptions = 17;
135
136#endif
137
138static int getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo );
139
140#ifndef RADEON_INFO_TILE_CONFIG
141#define RADEON_INFO_TILE_CONFIG 0x6
142#endif
143
144static int
145radeonGetParam(__DRIscreen *sPriv, int param, void *value)
146{
147  int ret;
148  drm_radeon_getparam_t gp = { 0 };
149  struct drm_radeon_info info = { 0 };
150
151  if (sPriv->drm_version.major >= 2) {
152      info.value = (uint64_t)(uintptr_t)value;
153      switch (param) {
154      case RADEON_PARAM_DEVICE_ID:
155          info.request = RADEON_INFO_DEVICE_ID;
156          break;
157      case RADEON_PARAM_NUM_GB_PIPES:
158          info.request = RADEON_INFO_NUM_GB_PIPES;
159          break;
160      case RADEON_PARAM_NUM_Z_PIPES:
161          info.request = RADEON_INFO_NUM_Z_PIPES;
162          break;
163      case RADEON_INFO_TILE_CONFIG:
164	  info.request = RADEON_INFO_TILE_CONFIG;
165          break;
166      default:
167          return -EINVAL;
168      }
169      ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_INFO, &info, sizeof(info));
170  } else {
171      gp.param = param;
172      gp.value = value;
173
174      ret = drmCommandWriteRead(sPriv->fd, DRM_RADEON_GETPARAM, &gp, sizeof(gp));
175  }
176  return ret;
177}
178
179#if defined(RADEON_R100)
180static const __DRItexOffsetExtension radeonTexOffsetExtension = {
181    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
182    radeonSetTexOffset,
183};
184
185static const __DRItexBufferExtension radeonTexBufferExtension = {
186    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
187   radeonSetTexBuffer,
188   radeonSetTexBuffer2,
189};
190#endif
191
192#if defined(RADEON_R200)
193
194static const __DRItexOffsetExtension r200texOffsetExtension = {
195    { __DRI_TEX_OFFSET, __DRI_TEX_OFFSET_VERSION },
196   r200SetTexOffset,
197};
198
199static const __DRItexBufferExtension r200TexBufferExtension = {
200    { __DRI_TEX_BUFFER, __DRI_TEX_BUFFER_VERSION },
201   r200SetTexBuffer,
202   r200SetTexBuffer2,
203};
204#endif
205
206static void
207radeonDRI2Flush(__DRIdrawable *drawable)
208{
209    radeonContextPtr rmesa;
210
211    rmesa = (radeonContextPtr) drawable->driContextPriv->driverPrivate;
212    radeonFlush(rmesa->glCtx);
213}
214
215static const struct __DRI2flushExtensionRec radeonFlushExtension = {
216    { __DRI2_FLUSH, __DRI2_FLUSH_VERSION },
217    radeonDRI2Flush,
218    dri2InvalidateDrawable,
219};
220
221static __DRIimage *
222radeon_create_image_from_name(__DRIscreen *screen,
223                              int width, int height, int format,
224                              int name, int pitch, void *loaderPrivate)
225{
226   __DRIimage *image;
227   radeonScreenPtr radeonScreen = screen->private;
228
229   if (name == 0)
230      return NULL;
231
232   image = CALLOC(sizeof *image);
233   if (image == NULL)
234      return NULL;
235
236   switch (format) {
237   case __DRI_IMAGE_FORMAT_RGB565:
238      image->format = MESA_FORMAT_RGB565;
239      image->internal_format = GL_RGB;
240      image->data_type = GL_UNSIGNED_BYTE;
241      break;
242   case __DRI_IMAGE_FORMAT_XRGB8888:
243      image->format = MESA_FORMAT_XRGB8888;
244      image->internal_format = GL_RGB;
245      image->data_type = GL_UNSIGNED_BYTE;
246      break;
247   case __DRI_IMAGE_FORMAT_ARGB8888:
248      image->format = MESA_FORMAT_ARGB8888;
249      image->internal_format = GL_RGBA;
250      image->data_type = GL_UNSIGNED_BYTE;
251      break;
252   default:
253      free(image);
254      return NULL;
255   }
256
257   image->data = loaderPrivate;
258   image->cpp = _mesa_get_format_bytes(image->format);
259   image->width = width;
260   image->pitch = pitch;
261   image->height = height;
262
263   image->bo = radeon_bo_open(radeonScreen->bom,
264                              (uint32_t)name,
265                              image->pitch * image->height * image->cpp,
266                              0,
267                              RADEON_GEM_DOMAIN_VRAM,
268                              0);
269
270   if (image->bo == NULL) {
271      FREE(image);
272      return NULL;
273   }
274
275   return image;
276}
277
278static __DRIimage *
279radeon_create_image_from_renderbuffer(__DRIcontext *context,
280                                      int renderbuffer, void *loaderPrivate)
281{
282   __DRIimage *image;
283   radeonContextPtr radeon = context->driverPrivate;
284   struct gl_renderbuffer *rb;
285   struct radeon_renderbuffer *rrb;
286
287   rb = _mesa_lookup_renderbuffer(radeon->glCtx, renderbuffer);
288   if (!rb) {
289      _mesa_error(radeon->glCtx,
290                  GL_INVALID_OPERATION, "glRenderbufferExternalMESA");
291      return NULL;
292   }
293
294   rrb = radeon_renderbuffer(rb);
295   image = CALLOC(sizeof *image);
296   if (image == NULL)
297      return NULL;
298
299   image->internal_format = rb->InternalFormat;
300   image->format = rb->Format;
301   image->cpp = rrb->cpp;
302   image->data_type = rb->DataType;
303   image->data = loaderPrivate;
304   radeon_bo_ref(rrb->bo);
305   image->bo = rrb->bo;
306
307   image->width = rb->Width;
308   image->height = rb->Height;
309   image->pitch = rrb->pitch / image->cpp;
310
311   return image;
312}
313
314static void
315radeon_destroy_image(__DRIimage *image)
316{
317   radeon_bo_unref(image->bo);
318   FREE(image);
319}
320
321static __DRIimage *
322radeon_create_image(__DRIscreen *screen,
323                    int width, int height, int format,
324                    unsigned int use,
325                    void *loaderPrivate)
326{
327   __DRIimage *image;
328   radeonScreenPtr radeonScreen = screen->private;
329
330   image = CALLOC(sizeof *image);
331   if (image == NULL)
332      return NULL;
333
334   switch (format) {
335   case __DRI_IMAGE_FORMAT_RGB565:
336      image->format = MESA_FORMAT_RGB565;
337      image->internal_format = GL_RGB;
338      image->data_type = GL_UNSIGNED_BYTE;
339      break;
340   case __DRI_IMAGE_FORMAT_XRGB8888:
341      image->format = MESA_FORMAT_XRGB8888;
342      image->internal_format = GL_RGB;
343      image->data_type = GL_UNSIGNED_BYTE;
344      break;
345   case __DRI_IMAGE_FORMAT_ARGB8888:
346      image->format = MESA_FORMAT_ARGB8888;
347      image->internal_format = GL_RGBA;
348      image->data_type = GL_UNSIGNED_BYTE;
349      break;
350   default:
351      free(image);
352      return NULL;
353   }
354
355   image->data = loaderPrivate;
356   image->cpp = _mesa_get_format_bytes(image->format);
357   image->width = width;
358   image->height = height;
359   image->pitch = ((image->cpp * image->width + 255) & ~255) / image->cpp;
360
361   image->bo = radeon_bo_open(radeonScreen->bom,
362                              0,
363                              image->pitch * image->height * image->cpp,
364                              0,
365                              RADEON_GEM_DOMAIN_VRAM,
366                              0);
367
368   if (image->bo == NULL) {
369      FREE(image);
370      return NULL;
371   }
372
373   return image;
374}
375
376static GLboolean
377radeon_query_image(__DRIimage *image, int attrib, int *value)
378{
379   switch (attrib) {
380   case __DRI_IMAGE_ATTRIB_STRIDE:
381      *value = image->pitch * image->cpp;
382      return GL_TRUE;
383   case __DRI_IMAGE_ATTRIB_HANDLE:
384      *value = image->bo->handle;
385      return GL_TRUE;
386   case __DRI_IMAGE_ATTRIB_NAME:
387      radeon_gem_get_kernel_name(image->bo, (uint32_t *) value);
388      return GL_TRUE;
389   default:
390      return GL_FALSE;
391   }
392}
393
394static struct __DRIimageExtensionRec radeonImageExtension = {
395    { __DRI_IMAGE, __DRI_IMAGE_VERSION },
396   radeon_create_image_from_name,
397   radeon_create_image_from_renderbuffer,
398   radeon_destroy_image,
399   radeon_create_image,
400   radeon_query_image
401};
402
403static int radeon_set_screen_flags(radeonScreenPtr screen, int device_id)
404{
405   screen->device_id = device_id;
406   screen->chip_flags = 0;
407   switch ( device_id ) {
408   case PCI_CHIP_RN50_515E:
409   case PCI_CHIP_RN50_5969:
410	return -1;
411
412   case PCI_CHIP_RADEON_LY:
413   case PCI_CHIP_RADEON_LZ:
414   case PCI_CHIP_RADEON_QY:
415   case PCI_CHIP_RADEON_QZ:
416      screen->chip_family = CHIP_FAMILY_RV100;
417      break;
418
419   case PCI_CHIP_RS100_4136:
420   case PCI_CHIP_RS100_4336:
421      screen->chip_family = CHIP_FAMILY_RS100;
422      break;
423
424   case PCI_CHIP_RS200_4137:
425   case PCI_CHIP_RS200_4337:
426   case PCI_CHIP_RS250_4237:
427   case PCI_CHIP_RS250_4437:
428      screen->chip_family = CHIP_FAMILY_RS200;
429      break;
430
431   case PCI_CHIP_RADEON_QD:
432   case PCI_CHIP_RADEON_QE:
433   case PCI_CHIP_RADEON_QF:
434   case PCI_CHIP_RADEON_QG:
435      /* all original radeons (7200) presumably have a stencil op bug */
436      screen->chip_family = CHIP_FAMILY_R100;
437      screen->chip_flags = RADEON_CHIPSET_TCL | RADEON_CHIPSET_BROKEN_STENCIL;
438      break;
439
440   case PCI_CHIP_RV200_QW:
441   case PCI_CHIP_RV200_QX:
442   case PCI_CHIP_RADEON_LW:
443   case PCI_CHIP_RADEON_LX:
444      screen->chip_family = CHIP_FAMILY_RV200;
445      screen->chip_flags = RADEON_CHIPSET_TCL;
446      break;
447
448   case PCI_CHIP_R200_BB:
449   case PCI_CHIP_R200_QH:
450   case PCI_CHIP_R200_QL:
451   case PCI_CHIP_R200_QM:
452      screen->chip_family = CHIP_FAMILY_R200;
453      screen->chip_flags = RADEON_CHIPSET_TCL;
454      break;
455
456   case PCI_CHIP_RV250_If:
457   case PCI_CHIP_RV250_Ig:
458   case PCI_CHIP_RV250_Ld:
459   case PCI_CHIP_RV250_Lf:
460   case PCI_CHIP_RV250_Lg:
461      screen->chip_family = CHIP_FAMILY_RV250;
462      screen->chip_flags = R200_CHIPSET_YCBCR_BROKEN | RADEON_CHIPSET_TCL;
463      break;
464
465   case PCI_CHIP_RV280_5960:
466   case PCI_CHIP_RV280_5961:
467   case PCI_CHIP_RV280_5962:
468   case PCI_CHIP_RV280_5964:
469   case PCI_CHIP_RV280_5965:
470   case PCI_CHIP_RV280_5C61:
471   case PCI_CHIP_RV280_5C63:
472      screen->chip_family = CHIP_FAMILY_RV280;
473      screen->chip_flags = RADEON_CHIPSET_TCL;
474      break;
475
476   case PCI_CHIP_RS300_5834:
477   case PCI_CHIP_RS300_5835:
478   case PCI_CHIP_RS350_7834:
479   case PCI_CHIP_RS350_7835:
480      screen->chip_family = CHIP_FAMILY_RS300;
481      break;
482
483   case PCI_CHIP_R300_AD:
484   case PCI_CHIP_R300_AE:
485   case PCI_CHIP_R300_AF:
486   case PCI_CHIP_R300_AG:
487   case PCI_CHIP_R300_ND:
488   case PCI_CHIP_R300_NE:
489   case PCI_CHIP_R300_NF:
490   case PCI_CHIP_R300_NG:
491      screen->chip_family = CHIP_FAMILY_R300;
492      screen->chip_flags = RADEON_CHIPSET_TCL;
493      break;
494
495   case PCI_CHIP_RV350_AP:
496   case PCI_CHIP_RV350_AQ:
497   case PCI_CHIP_RV350_AR:
498   case PCI_CHIP_RV350_AS:
499   case PCI_CHIP_RV350_AT:
500   case PCI_CHIP_RV350_AV:
501   case PCI_CHIP_RV350_AU:
502   case PCI_CHIP_RV350_NP:
503   case PCI_CHIP_RV350_NQ:
504   case PCI_CHIP_RV350_NR:
505   case PCI_CHIP_RV350_NS:
506   case PCI_CHIP_RV350_NT:
507   case PCI_CHIP_RV350_NV:
508      screen->chip_family = CHIP_FAMILY_RV350;
509      screen->chip_flags = RADEON_CHIPSET_TCL;
510      break;
511
512   case PCI_CHIP_R350_AH:
513   case PCI_CHIP_R350_AI:
514   case PCI_CHIP_R350_AJ:
515   case PCI_CHIP_R350_AK:
516   case PCI_CHIP_R350_NH:
517   case PCI_CHIP_R350_NI:
518   case PCI_CHIP_R360_NJ:
519   case PCI_CHIP_R350_NK:
520      screen->chip_family = CHIP_FAMILY_R350;
521      screen->chip_flags = RADEON_CHIPSET_TCL;
522      break;
523
524   case PCI_CHIP_RV370_5460:
525   case PCI_CHIP_RV370_5462:
526   case PCI_CHIP_RV370_5464:
527   case PCI_CHIP_RV370_5B60:
528   case PCI_CHIP_RV370_5B62:
529   case PCI_CHIP_RV370_5B63:
530   case PCI_CHIP_RV370_5B64:
531   case PCI_CHIP_RV370_5B65:
532   case PCI_CHIP_RV380_3150:
533   case PCI_CHIP_RV380_3152:
534   case PCI_CHIP_RV380_3154:
535   case PCI_CHIP_RV380_3155:
536   case PCI_CHIP_RV380_3E50:
537   case PCI_CHIP_RV380_3E54:
538      screen->chip_family = CHIP_FAMILY_RV380;
539      screen->chip_flags = RADEON_CHIPSET_TCL;
540      break;
541
542   case PCI_CHIP_R420_JN:
543   case PCI_CHIP_R420_JH:
544   case PCI_CHIP_R420_JI:
545   case PCI_CHIP_R420_JJ:
546   case PCI_CHIP_R420_JK:
547   case PCI_CHIP_R420_JL:
548   case PCI_CHIP_R420_JM:
549   case PCI_CHIP_R420_JO:
550   case PCI_CHIP_R420_JP:
551   case PCI_CHIP_R420_JT:
552   case PCI_CHIP_R481_4B49:
553   case PCI_CHIP_R481_4B4A:
554   case PCI_CHIP_R481_4B4B:
555   case PCI_CHIP_R481_4B4C:
556   case PCI_CHIP_R423_UH:
557   case PCI_CHIP_R423_UI:
558   case PCI_CHIP_R423_UJ:
559   case PCI_CHIP_R423_UK:
560   case PCI_CHIP_R430_554C:
561   case PCI_CHIP_R430_554D:
562   case PCI_CHIP_R430_554E:
563   case PCI_CHIP_R430_554F:
564   case PCI_CHIP_R423_5550:
565   case PCI_CHIP_R423_UQ:
566   case PCI_CHIP_R423_UR:
567   case PCI_CHIP_R423_UT:
568   case PCI_CHIP_R430_5D48:
569   case PCI_CHIP_R430_5D49:
570   case PCI_CHIP_R430_5D4A:
571   case PCI_CHIP_R480_5D4C:
572   case PCI_CHIP_R480_5D4D:
573   case PCI_CHIP_R480_5D4E:
574   case PCI_CHIP_R480_5D4F:
575   case PCI_CHIP_R480_5D50:
576   case PCI_CHIP_R480_5D52:
577   case PCI_CHIP_R423_5D57:
578      screen->chip_family = CHIP_FAMILY_R420;
579      screen->chip_flags = RADEON_CHIPSET_TCL;
580      break;
581
582   case PCI_CHIP_RV410_5E4C:
583   case PCI_CHIP_RV410_5E4F:
584   case PCI_CHIP_RV410_564A:
585   case PCI_CHIP_RV410_564B:
586   case PCI_CHIP_RV410_564F:
587   case PCI_CHIP_RV410_5652:
588   case PCI_CHIP_RV410_5653:
589   case PCI_CHIP_RV410_5657:
590   case PCI_CHIP_RV410_5E48:
591   case PCI_CHIP_RV410_5E4A:
592   case PCI_CHIP_RV410_5E4B:
593   case PCI_CHIP_RV410_5E4D:
594      screen->chip_family = CHIP_FAMILY_RV410;
595      screen->chip_flags = RADEON_CHIPSET_TCL;
596      break;
597
598   case PCI_CHIP_RS480_5954:
599   case PCI_CHIP_RS480_5955:
600   case PCI_CHIP_RS482_5974:
601   case PCI_CHIP_RS482_5975:
602   case PCI_CHIP_RS400_5A41:
603   case PCI_CHIP_RS400_5A42:
604   case PCI_CHIP_RC410_5A61:
605   case PCI_CHIP_RC410_5A62:
606      screen->chip_family = CHIP_FAMILY_RS400;
607      break;
608
609   case PCI_CHIP_RS600_793F:
610   case PCI_CHIP_RS600_7941:
611   case PCI_CHIP_RS600_7942:
612      screen->chip_family = CHIP_FAMILY_RS600;
613      break;
614
615   case PCI_CHIP_RS690_791E:
616   case PCI_CHIP_RS690_791F:
617      screen->chip_family = CHIP_FAMILY_RS690;
618      break;
619   case PCI_CHIP_RS740_796C:
620   case PCI_CHIP_RS740_796D:
621   case PCI_CHIP_RS740_796E:
622   case PCI_CHIP_RS740_796F:
623      screen->chip_family = CHIP_FAMILY_RS740;
624      break;
625
626   case PCI_CHIP_R520_7100:
627   case PCI_CHIP_R520_7101:
628   case PCI_CHIP_R520_7102:
629   case PCI_CHIP_R520_7103:
630   case PCI_CHIP_R520_7104:
631   case PCI_CHIP_R520_7105:
632   case PCI_CHIP_R520_7106:
633   case PCI_CHIP_R520_7108:
634   case PCI_CHIP_R520_7109:
635   case PCI_CHIP_R520_710A:
636   case PCI_CHIP_R520_710B:
637   case PCI_CHIP_R520_710C:
638   case PCI_CHIP_R520_710E:
639   case PCI_CHIP_R520_710F:
640      screen->chip_family = CHIP_FAMILY_R520;
641      screen->chip_flags = RADEON_CHIPSET_TCL;
642      break;
643
644   case PCI_CHIP_RV515_7140:
645   case PCI_CHIP_RV515_7141:
646   case PCI_CHIP_RV515_7142:
647   case PCI_CHIP_RV515_7143:
648   case PCI_CHIP_RV515_7144:
649   case PCI_CHIP_RV515_7145:
650   case PCI_CHIP_RV515_7146:
651   case PCI_CHIP_RV515_7147:
652   case PCI_CHIP_RV515_7149:
653   case PCI_CHIP_RV515_714A:
654   case PCI_CHIP_RV515_714B:
655   case PCI_CHIP_RV515_714C:
656   case PCI_CHIP_RV515_714D:
657   case PCI_CHIP_RV515_714E:
658   case PCI_CHIP_RV515_714F:
659   case PCI_CHIP_RV515_7151:
660   case PCI_CHIP_RV515_7152:
661   case PCI_CHIP_RV515_7153:
662   case PCI_CHIP_RV515_715E:
663   case PCI_CHIP_RV515_715F:
664   case PCI_CHIP_RV515_7180:
665   case PCI_CHIP_RV515_7181:
666   case PCI_CHIP_RV515_7183:
667   case PCI_CHIP_RV515_7186:
668   case PCI_CHIP_RV515_7187:
669   case PCI_CHIP_RV515_7188:
670   case PCI_CHIP_RV515_718A:
671   case PCI_CHIP_RV515_718B:
672   case PCI_CHIP_RV515_718C:
673   case PCI_CHIP_RV515_718D:
674   case PCI_CHIP_RV515_718F:
675   case PCI_CHIP_RV515_7193:
676   case PCI_CHIP_RV515_7196:
677   case PCI_CHIP_RV515_719B:
678   case PCI_CHIP_RV515_719F:
679   case PCI_CHIP_RV515_7200:
680   case PCI_CHIP_RV515_7210:
681   case PCI_CHIP_RV515_7211:
682      screen->chip_family = CHIP_FAMILY_RV515;
683      screen->chip_flags = RADEON_CHIPSET_TCL;
684      break;
685
686   case PCI_CHIP_RV530_71C0:
687   case PCI_CHIP_RV530_71C1:
688   case PCI_CHIP_RV530_71C2:
689   case PCI_CHIP_RV530_71C3:
690   case PCI_CHIP_RV530_71C4:
691   case PCI_CHIP_RV530_71C5:
692   case PCI_CHIP_RV530_71C6:
693   case PCI_CHIP_RV530_71C7:
694   case PCI_CHIP_RV530_71CD:
695   case PCI_CHIP_RV530_71CE:
696   case PCI_CHIP_RV530_71D2:
697   case PCI_CHIP_RV530_71D4:
698   case PCI_CHIP_RV530_71D5:
699   case PCI_CHIP_RV530_71D6:
700   case PCI_CHIP_RV530_71DA:
701   case PCI_CHIP_RV530_71DE:
702      screen->chip_family = CHIP_FAMILY_RV530;
703      screen->chip_flags = RADEON_CHIPSET_TCL;
704      break;
705
706   case PCI_CHIP_R580_7240:
707   case PCI_CHIP_R580_7243:
708   case PCI_CHIP_R580_7244:
709   case PCI_CHIP_R580_7245:
710   case PCI_CHIP_R580_7246:
711   case PCI_CHIP_R580_7247:
712   case PCI_CHIP_R580_7248:
713   case PCI_CHIP_R580_7249:
714   case PCI_CHIP_R580_724A:
715   case PCI_CHIP_R580_724B:
716   case PCI_CHIP_R580_724C:
717   case PCI_CHIP_R580_724D:
718   case PCI_CHIP_R580_724E:
719   case PCI_CHIP_R580_724F:
720   case PCI_CHIP_R580_7284:
721      screen->chip_family = CHIP_FAMILY_R580;
722      screen->chip_flags = RADEON_CHIPSET_TCL;
723      break;
724
725   case PCI_CHIP_RV570_7280:
726   case PCI_CHIP_RV560_7281:
727   case PCI_CHIP_RV560_7283:
728   case PCI_CHIP_RV560_7287:
729   case PCI_CHIP_RV570_7288:
730   case PCI_CHIP_RV570_7289:
731   case PCI_CHIP_RV570_728B:
732   case PCI_CHIP_RV570_728C:
733   case PCI_CHIP_RV560_7290:
734   case PCI_CHIP_RV560_7291:
735   case PCI_CHIP_RV560_7293:
736   case PCI_CHIP_RV560_7297:
737      screen->chip_family = CHIP_FAMILY_RV560;
738      screen->chip_flags = RADEON_CHIPSET_TCL;
739      break;
740
741   case PCI_CHIP_R600_9400:
742   case PCI_CHIP_R600_9401:
743   case PCI_CHIP_R600_9402:
744   case PCI_CHIP_R600_9403:
745   case PCI_CHIP_R600_9405:
746   case PCI_CHIP_R600_940A:
747   case PCI_CHIP_R600_940B:
748   case PCI_CHIP_R600_940F:
749      screen->chip_family = CHIP_FAMILY_R600;
750      screen->chip_flags = RADEON_CHIPSET_TCL;
751      break;
752
753   case PCI_CHIP_RV610_94C0:
754   case PCI_CHIP_RV610_94C1:
755   case PCI_CHIP_RV610_94C3:
756   case PCI_CHIP_RV610_94C4:
757   case PCI_CHIP_RV610_94C5:
758   case PCI_CHIP_RV610_94C6:
759   case PCI_CHIP_RV610_94C7:
760   case PCI_CHIP_RV610_94C8:
761   case PCI_CHIP_RV610_94C9:
762   case PCI_CHIP_RV610_94CB:
763   case PCI_CHIP_RV610_94CC:
764   case PCI_CHIP_RV610_94CD:
765      screen->chip_family = CHIP_FAMILY_RV610;
766      screen->chip_flags = RADEON_CHIPSET_TCL;
767      break;
768
769   case PCI_CHIP_RV630_9580:
770   case PCI_CHIP_RV630_9581:
771   case PCI_CHIP_RV630_9583:
772   case PCI_CHIP_RV630_9586:
773   case PCI_CHIP_RV630_9587:
774   case PCI_CHIP_RV630_9588:
775   case PCI_CHIP_RV630_9589:
776   case PCI_CHIP_RV630_958A:
777   case PCI_CHIP_RV630_958B:
778   case PCI_CHIP_RV630_958C:
779   case PCI_CHIP_RV630_958D:
780   case PCI_CHIP_RV630_958E:
781   case PCI_CHIP_RV630_958F:
782      screen->chip_family = CHIP_FAMILY_RV630;
783      screen->chip_flags = RADEON_CHIPSET_TCL;
784      break;
785
786   case PCI_CHIP_RV670_9500:
787   case PCI_CHIP_RV670_9501:
788   case PCI_CHIP_RV670_9504:
789   case PCI_CHIP_RV670_9505:
790   case PCI_CHIP_RV670_9506:
791   case PCI_CHIP_RV670_9507:
792   case PCI_CHIP_RV670_9508:
793   case PCI_CHIP_RV670_9509:
794   case PCI_CHIP_RV670_950F:
795   case PCI_CHIP_RV670_9511:
796   case PCI_CHIP_RV670_9515:
797   case PCI_CHIP_RV670_9517:
798   case PCI_CHIP_RV670_9519:
799      screen->chip_family = CHIP_FAMILY_RV670;
800      screen->chip_flags = RADEON_CHIPSET_TCL;
801      break;
802
803   case PCI_CHIP_RV620_95C0:
804   case PCI_CHIP_RV620_95C2:
805   case PCI_CHIP_RV620_95C4:
806   case PCI_CHIP_RV620_95C5:
807   case PCI_CHIP_RV620_95C6:
808   case PCI_CHIP_RV620_95C7:
809   case PCI_CHIP_RV620_95C9:
810   case PCI_CHIP_RV620_95CC:
811   case PCI_CHIP_RV620_95CD:
812   case PCI_CHIP_RV620_95CE:
813   case PCI_CHIP_RV620_95CF:
814      screen->chip_family = CHIP_FAMILY_RV620;
815      screen->chip_flags = RADEON_CHIPSET_TCL;
816      break;
817
818   case PCI_CHIP_RV635_9590:
819   case PCI_CHIP_RV635_9591:
820   case PCI_CHIP_RV635_9593:
821   case PCI_CHIP_RV635_9595:
822   case PCI_CHIP_RV635_9596:
823   case PCI_CHIP_RV635_9597:
824   case PCI_CHIP_RV635_9598:
825   case PCI_CHIP_RV635_9599:
826   case PCI_CHIP_RV635_959B:
827      screen->chip_family = CHIP_FAMILY_RV635;
828      screen->chip_flags = RADEON_CHIPSET_TCL;
829      break;
830
831   case PCI_CHIP_RS780_9610:
832   case PCI_CHIP_RS780_9611:
833   case PCI_CHIP_RS780_9612:
834   case PCI_CHIP_RS780_9613:
835   case PCI_CHIP_RS780_9614:
836   case PCI_CHIP_RS780_9615:
837   case PCI_CHIP_RS780_9616:
838      screen->chip_family = CHIP_FAMILY_RS780;
839      screen->chip_flags = RADEON_CHIPSET_TCL;
840      break;
841   case PCI_CHIP_RS880_9710:
842   case PCI_CHIP_RS880_9711:
843   case PCI_CHIP_RS880_9712:
844   case PCI_CHIP_RS880_9713:
845   case PCI_CHIP_RS880_9714:
846   case PCI_CHIP_RS880_9715:
847      screen->chip_family = CHIP_FAMILY_RS880;
848      screen->chip_flags = RADEON_CHIPSET_TCL;
849      break;
850
851   case PCI_CHIP_RV770_9440:
852   case PCI_CHIP_RV770_9441:
853   case PCI_CHIP_RV770_9442:
854   case PCI_CHIP_RV770_9443:
855   case PCI_CHIP_RV770_9444:
856   case PCI_CHIP_RV770_9446:
857   case PCI_CHIP_RV770_944A:
858   case PCI_CHIP_RV770_944B:
859   case PCI_CHIP_RV770_944C:
860   case PCI_CHIP_RV770_944E:
861   case PCI_CHIP_RV770_9450:
862   case PCI_CHIP_RV770_9452:
863   case PCI_CHIP_RV770_9456:
864   case PCI_CHIP_RV770_945A:
865   case PCI_CHIP_RV770_945B:
866   case PCI_CHIP_RV770_945E:
867   case PCI_CHIP_RV790_9460:
868   case PCI_CHIP_RV790_9462:
869   case PCI_CHIP_RV770_946A:
870   case PCI_CHIP_RV770_946B:
871   case PCI_CHIP_RV770_947A:
872   case PCI_CHIP_RV770_947B:
873      screen->chip_family = CHIP_FAMILY_RV770;
874      screen->chip_flags = RADEON_CHIPSET_TCL;
875      break;
876
877   case PCI_CHIP_RV730_9480:
878   case PCI_CHIP_RV730_9487:
879   case PCI_CHIP_RV730_9488:
880   case PCI_CHIP_RV730_9489:
881   case PCI_CHIP_RV730_948A:
882   case PCI_CHIP_RV730_948F:
883   case PCI_CHIP_RV730_9490:
884   case PCI_CHIP_RV730_9491:
885   case PCI_CHIP_RV730_9495:
886   case PCI_CHIP_RV730_9498:
887   case PCI_CHIP_RV730_949C:
888   case PCI_CHIP_RV730_949E:
889   case PCI_CHIP_RV730_949F:
890      screen->chip_family = CHIP_FAMILY_RV730;
891      screen->chip_flags = RADEON_CHIPSET_TCL;
892      break;
893
894   case PCI_CHIP_RV710_9540:
895   case PCI_CHIP_RV710_9541:
896   case PCI_CHIP_RV710_9542:
897   case PCI_CHIP_RV710_954E:
898   case PCI_CHIP_RV710_954F:
899   case PCI_CHIP_RV710_9552:
900   case PCI_CHIP_RV710_9553:
901   case PCI_CHIP_RV710_9555:
902   case PCI_CHIP_RV710_9557:
903   case PCI_CHIP_RV710_955F:
904      screen->chip_family = CHIP_FAMILY_RV710;
905      screen->chip_flags = RADEON_CHIPSET_TCL;
906      break;
907
908   case PCI_CHIP_RV740_94A0:
909   case PCI_CHIP_RV740_94A1:
910   case PCI_CHIP_RV740_94A3:
911   case PCI_CHIP_RV740_94B1:
912   case PCI_CHIP_RV740_94B3:
913   case PCI_CHIP_RV740_94B4:
914   case PCI_CHIP_RV740_94B5:
915   case PCI_CHIP_RV740_94B9:
916      screen->chip_family = CHIP_FAMILY_RV740;
917      screen->chip_flags = RADEON_CHIPSET_TCL;
918      break;
919
920    case PCI_CHIP_CEDAR_68E0:
921    case PCI_CHIP_CEDAR_68E1:
922    case PCI_CHIP_CEDAR_68E4:
923    case PCI_CHIP_CEDAR_68E5:
924    case PCI_CHIP_CEDAR_68E8:
925    case PCI_CHIP_CEDAR_68E9:
926    case PCI_CHIP_CEDAR_68F1:
927    case PCI_CHIP_CEDAR_68F2:
928    case PCI_CHIP_CEDAR_68F8:
929    case PCI_CHIP_CEDAR_68F9:
930    case PCI_CHIP_CEDAR_68FE:
931       screen->chip_family = CHIP_FAMILY_CEDAR;
932       screen->chip_flags = RADEON_CHIPSET_TCL;
933       break;
934
935    case PCI_CHIP_REDWOOD_68C0:
936    case PCI_CHIP_REDWOOD_68C1:
937    case PCI_CHIP_REDWOOD_68C8:
938    case PCI_CHIP_REDWOOD_68C9:
939    case PCI_CHIP_REDWOOD_68D8:
940    case PCI_CHIP_REDWOOD_68D9:
941    case PCI_CHIP_REDWOOD_68DA:
942    case PCI_CHIP_REDWOOD_68DE:
943       screen->chip_family = CHIP_FAMILY_REDWOOD;
944       screen->chip_flags = RADEON_CHIPSET_TCL;
945       break;
946
947    case PCI_CHIP_JUNIPER_68A0:
948    case PCI_CHIP_JUNIPER_68A1:
949    case PCI_CHIP_JUNIPER_68A8:
950    case PCI_CHIP_JUNIPER_68A9:
951    case PCI_CHIP_JUNIPER_68B0:
952    case PCI_CHIP_JUNIPER_68B8:
953    case PCI_CHIP_JUNIPER_68B9:
954    case PCI_CHIP_JUNIPER_68BA:
955    case PCI_CHIP_JUNIPER_68BE:
956    case PCI_CHIP_JUNIPER_68BF:
957       screen->chip_family = CHIP_FAMILY_JUNIPER;
958       screen->chip_flags = RADEON_CHIPSET_TCL;
959       break;
960
961    case PCI_CHIP_CYPRESS_6880:
962    case PCI_CHIP_CYPRESS_6888:
963    case PCI_CHIP_CYPRESS_6889:
964    case PCI_CHIP_CYPRESS_688A:
965    case PCI_CHIP_CYPRESS_6898:
966    case PCI_CHIP_CYPRESS_6899:
967    case PCI_CHIP_CYPRESS_689B:
968    case PCI_CHIP_CYPRESS_689E:
969       screen->chip_family = CHIP_FAMILY_CYPRESS;
970       screen->chip_flags = RADEON_CHIPSET_TCL;
971       break;
972
973    case PCI_CHIP_HEMLOCK_689C:
974    case PCI_CHIP_HEMLOCK_689D:
975       screen->chip_family = CHIP_FAMILY_HEMLOCK;
976       screen->chip_flags = RADEON_CHIPSET_TCL;
977       break;
978
979    case PCI_CHIP_PALM_9802:
980    case PCI_CHIP_PALM_9803:
981    case PCI_CHIP_PALM_9804:
982    case PCI_CHIP_PALM_9805:
983    case PCI_CHIP_PALM_9806:
984    case PCI_CHIP_PALM_9807:
985       screen->chip_family = CHIP_FAMILY_PALM;
986       screen->chip_flags = RADEON_CHIPSET_TCL;
987       break;
988
989    case PCI_CHIP_SUMO_9640:
990    case PCI_CHIP_SUMO_9641:
991    case PCI_CHIP_SUMO_9647:
992    case PCI_CHIP_SUMO_9648:
993    case PCI_CHIP_SUMO_964A:
994    case PCI_CHIP_SUMO_964E:
995    case PCI_CHIP_SUMO_964F:
996       screen->chip_family = CHIP_FAMILY_SUMO;
997       screen->chip_flags = RADEON_CHIPSET_TCL;
998       break;
999
1000    case PCI_CHIP_SUMO2_9642:
1001    case PCI_CHIP_SUMO2_9643:
1002    case PCI_CHIP_SUMO2_9644:
1003    case PCI_CHIP_SUMO2_9645:
1004       screen->chip_family = CHIP_FAMILY_SUMO2;
1005       screen->chip_flags = RADEON_CHIPSET_TCL;
1006       break;
1007
1008   case PCI_CHIP_BARTS_6720:
1009   case PCI_CHIP_BARTS_6721:
1010   case PCI_CHIP_BARTS_6722:
1011   case PCI_CHIP_BARTS_6723:
1012   case PCI_CHIP_BARTS_6724:
1013   case PCI_CHIP_BARTS_6725:
1014   case PCI_CHIP_BARTS_6726:
1015   case PCI_CHIP_BARTS_6727:
1016   case PCI_CHIP_BARTS_6728:
1017   case PCI_CHIP_BARTS_6729:
1018   case PCI_CHIP_BARTS_6738:
1019   case PCI_CHIP_BARTS_6739:
1020   case PCI_CHIP_BARTS_673E:
1021       screen->chip_family = CHIP_FAMILY_BARTS;
1022       screen->chip_flags = RADEON_CHIPSET_TCL;
1023       break;
1024
1025   case PCI_CHIP_TURKS_6740:
1026   case PCI_CHIP_TURKS_6741:
1027   case PCI_CHIP_TURKS_6742:
1028   case PCI_CHIP_TURKS_6743:
1029   case PCI_CHIP_TURKS_6744:
1030   case PCI_CHIP_TURKS_6745:
1031   case PCI_CHIP_TURKS_6746:
1032   case PCI_CHIP_TURKS_6747:
1033   case PCI_CHIP_TURKS_6748:
1034   case PCI_CHIP_TURKS_6749:
1035   case PCI_CHIP_TURKS_6750:
1036   case PCI_CHIP_TURKS_6758:
1037   case PCI_CHIP_TURKS_6759:
1038   case PCI_CHIP_TURKS_675F:
1039       screen->chip_family = CHIP_FAMILY_TURKS;
1040       screen->chip_flags = RADEON_CHIPSET_TCL;
1041       break;
1042
1043   case PCI_CHIP_CAICOS_6760:
1044   case PCI_CHIP_CAICOS_6761:
1045   case PCI_CHIP_CAICOS_6762:
1046   case PCI_CHIP_CAICOS_6763:
1047   case PCI_CHIP_CAICOS_6764:
1048   case PCI_CHIP_CAICOS_6765:
1049   case PCI_CHIP_CAICOS_6766:
1050   case PCI_CHIP_CAICOS_6767:
1051   case PCI_CHIP_CAICOS_6768:
1052   case PCI_CHIP_CAICOS_6770:
1053   case PCI_CHIP_CAICOS_6778:
1054   case PCI_CHIP_CAICOS_6779:
1055       screen->chip_family = CHIP_FAMILY_CAICOS;
1056       screen->chip_flags = RADEON_CHIPSET_TCL;
1057       break;
1058
1059   default:
1060      fprintf(stderr, "unknown chip id 0x%x, can't guess.\n",
1061	      device_id);
1062      return -1;
1063   }
1064
1065   return 0;
1066}
1067
1068static radeonScreenPtr
1069radeonCreateScreen2(__DRIscreen *sPriv)
1070{
1071   radeonScreenPtr screen;
1072   int i;
1073   int ret;
1074   uint32_t device_id = 0;
1075   uint32_t temp = 0;
1076
1077   /* Allocate the private area */
1078   screen = (radeonScreenPtr) CALLOC( sizeof(*screen) );
1079   if ( !screen ) {
1080      __driUtilMessage("%s: Could not allocate memory for screen structure",
1081		       __FUNCTION__);
1082      fprintf(stderr, "leaving here\n");
1083      return NULL;
1084   }
1085
1086   radeon_init_debug();
1087
1088   /* parse information in __driConfigOptions */
1089   driParseOptionInfo (&screen->optionCache,
1090		       __driConfigOptions, __driNConfigOptions);
1091
1092   screen->chip_flags = 0;
1093
1094   /* if we have kms we can support all of these */
1095   screen->drmSupportsCubeMapsR200 = 1;
1096   screen->drmSupportsBlendColor = 1;
1097   screen->drmSupportsTriPerf = 1;
1098   screen->drmSupportsFragShader = 1;
1099   screen->drmSupportsPointSprites = 1;
1100   screen->drmSupportsCubeMapsR100 = 1;
1101   screen->drmSupportsVertexProgram = 1;
1102   screen->drmSupportsOcclusionQueries = 1;
1103   screen->irq = 1;
1104
1105   ret = radeonGetParam(sPriv, RADEON_PARAM_DEVICE_ID, &device_id);
1106   if (ret) {
1107     FREE( screen );
1108     fprintf(stderr, "drm_radeon_getparam_t (RADEON_PARAM_DEVICE_ID): %d\n", ret);
1109     return NULL;
1110   }
1111
1112   ret = radeon_set_screen_flags(screen, device_id);
1113   if (ret == -1)
1114     return NULL;
1115
1116   if (getenv("R300_NO_TCL"))
1117	   screen->chip_flags &= ~RADEON_CHIPSET_TCL;
1118
1119   if (screen->chip_family <= CHIP_FAMILY_RS200)
1120	   screen->chip_flags |= RADEON_CLASS_R100;
1121   else if (screen->chip_family <= CHIP_FAMILY_RV280)
1122	   screen->chip_flags |= RADEON_CLASS_R200;
1123   else if (screen->chip_family <= CHIP_FAMILY_RV570)
1124	   screen->chip_flags |= RADEON_CLASS_R300;
1125   else
1126	   screen->chip_flags |= RADEON_CLASS_R600;
1127
1128   /* r6xx+ tiling, default group bytes */
1129   if (screen->chip_family >= CHIP_FAMILY_CEDAR)
1130	   screen->group_bytes = 512;
1131   else
1132	   screen->group_bytes = 256;
1133   if (IS_R600_CLASS(screen)) {
1134	   if ((sPriv->drm_version.minor >= 6) &&
1135	       (screen->chip_family < CHIP_FAMILY_CEDAR)) {
1136		   ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1137		   if (ret)
1138			   fprintf(stderr, "failed to get tiling info\n");
1139		   else {
1140			   screen->tile_config = temp;
1141			   screen->r7xx_bank_op = 0;
1142			   switch ((screen->tile_config & 0xe) >> 1) {
1143			   case 0:
1144				   screen->num_channels = 1;
1145				   break;
1146			   case 1:
1147				   screen->num_channels = 2;
1148				   break;
1149			   case 2:
1150				   screen->num_channels = 4;
1151				   break;
1152			   case 3:
1153				   screen->num_channels = 8;
1154				   break;
1155			   default:
1156				   fprintf(stderr, "bad channels\n");
1157				   break;
1158			   }
1159			   switch ((screen->tile_config & 0x30) >> 4) {
1160			   case 0:
1161				   screen->num_banks = 4;
1162				   break;
1163			   case 1:
1164				   screen->num_banks = 8;
1165				   break;
1166			   default:
1167				   fprintf(stderr, "bad banks\n");
1168				   break;
1169			   }
1170			   switch ((screen->tile_config & 0xc0) >> 6) {
1171			   case 0:
1172				   screen->group_bytes = 256;
1173				   break;
1174			   case 1:
1175				   screen->group_bytes = 512;
1176				   break;
1177			   default:
1178				   fprintf(stderr, "bad group_bytes\n");
1179				   break;
1180			   }
1181		   }
1182	   } else if ((sPriv->drm_version.minor >= 7) &&
1183		      (screen->chip_family >= CHIP_FAMILY_CEDAR)) {
1184		   ret = radeonGetParam(sPriv, RADEON_INFO_TILE_CONFIG, &temp);
1185		   if (ret)
1186			   fprintf(stderr, "failed to get tiling info\n");
1187		   else {
1188			   screen->tile_config = temp;
1189			   screen->r7xx_bank_op = 0;
1190			   switch (screen->tile_config & 0xf) {
1191			   case 0:
1192				   screen->num_channels = 1;
1193				   break;
1194			   case 1:
1195				   screen->num_channels = 2;
1196				   break;
1197			   case 2:
1198				   screen->num_channels = 4;
1199				   break;
1200			   case 3:
1201				   screen->num_channels = 8;
1202				   break;
1203			   default:
1204				   fprintf(stderr, "bad channels\n");
1205				   break;
1206			   }
1207			   switch ((screen->tile_config & 0xf0) >> 4) {
1208			   case 0:
1209				   screen->num_banks = 4;
1210				   break;
1211			   case 1:
1212				   screen->num_banks = 8;
1213				   break;
1214			   case 2:
1215				   screen->num_banks = 16;
1216				   break;
1217			   default:
1218				   fprintf(stderr, "bad banks\n");
1219				   break;
1220			   }
1221			   switch ((screen->tile_config & 0xf00) >> 8) {
1222			   case 0:
1223				   screen->group_bytes = 256;
1224				   break;
1225			   case 1:
1226				   screen->group_bytes = 512;
1227				   break;
1228			   default:
1229				   fprintf(stderr, "bad group_bytes\n");
1230				   break;
1231			   }
1232		   }
1233	   }
1234   }
1235
1236   if (IS_R300_CLASS(screen)) {
1237       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_GB_PIPES, &temp);
1238       if (ret) {
1239	   fprintf(stderr, "Unable to get num_pipes, need newer drm\n");
1240	   switch (screen->chip_family) {
1241	   case CHIP_FAMILY_R300:
1242	   case CHIP_FAMILY_R350:
1243	       screen->num_gb_pipes = 2;
1244	       break;
1245	   case CHIP_FAMILY_R420:
1246	   case CHIP_FAMILY_R520:
1247	   case CHIP_FAMILY_R580:
1248	   case CHIP_FAMILY_RV560:
1249	   case CHIP_FAMILY_RV570:
1250	       screen->num_gb_pipes = 4;
1251	       break;
1252	   case CHIP_FAMILY_RV350:
1253	   case CHIP_FAMILY_RV515:
1254	   case CHIP_FAMILY_RV530:
1255	   case CHIP_FAMILY_RV410:
1256	   default:
1257	       screen->num_gb_pipes = 1;
1258	       break;
1259	   }
1260       } else {
1261	   screen->num_gb_pipes = temp;
1262       }
1263
1264       /* pipe overrides */
1265       switch (device_id) {
1266       case PCI_CHIP_R300_AD: /* 9500 with 1 quadpipe verified by: Reid Linnemann <lreid@cs.okstate.edu> */
1267       case PCI_CHIP_R350_AH: /* 9800 SE only have 1 quadpipe */
1268       case PCI_CHIP_RV410_5E4C: /* RV410 SE only have 1 quadpipe */
1269       case PCI_CHIP_RV410_5E4F: /* RV410 SE only have 1 quadpipe */
1270	   screen->num_gb_pipes = 1;
1271	   break;
1272       default:
1273	   break;
1274       }
1275
1276       ret = radeonGetParam(sPriv, RADEON_PARAM_NUM_Z_PIPES, &temp);
1277       if (ret)
1278	       screen->num_z_pipes = 2;
1279       else
1280	       screen->num_z_pipes = temp;
1281
1282   }
1283
1284   i = 0;
1285   screen->extensions[i++] = &driCopySubBufferExtension.base;
1286   screen->extensions[i++] = &driReadDrawableExtension;
1287   screen->extensions[i++] = &dri2ConfigQueryExtension.base;
1288
1289   if ( screen->irq != 0 ) {
1290       screen->extensions[i++] = &driSwapControlExtension.base;
1291       screen->extensions[i++] = &driMediaStreamCounterExtension.base;
1292   }
1293
1294#if defined(RADEON_R100)
1295   screen->extensions[i++] = &radeonTexBufferExtension.base;
1296#endif
1297
1298#if defined(RADEON_R200)
1299   screen->extensions[i++] = &r200TexBufferExtension.base;
1300#endif
1301
1302   screen->extensions[i++] = &radeonFlushExtension.base;
1303   screen->extensions[i++] = &radeonImageExtension.base;
1304
1305   screen->extensions[i++] = NULL;
1306   sPriv->extensions = screen->extensions;
1307
1308   screen->driScreen = sPriv;
1309   screen->bom = radeon_bo_manager_gem_ctor(sPriv->fd);
1310   if (screen->bom == NULL) {
1311       free(screen);
1312       return NULL;
1313   }
1314   return screen;
1315}
1316
1317/* Destroy the device specific screen private data struct.
1318 */
1319static void
1320radeonDestroyScreen( __DRIscreen *sPriv )
1321{
1322    radeonScreenPtr screen = (radeonScreenPtr)sPriv->private;
1323
1324    if (!screen)
1325        return;
1326
1327#ifdef RADEON_BO_TRACK
1328    radeon_tracker_print(&screen->bom->tracker, stderr);
1329#endif
1330    radeon_bo_manager_gem_dtor(screen->bom);
1331
1332    /* free all option information */
1333    driDestroyOptionInfo (&screen->optionCache);
1334
1335    FREE( screen );
1336    sPriv->private = NULL;
1337}
1338
1339
1340/* Initialize the driver specific screen private data.
1341 */
1342static GLboolean
1343radeonInitDriver( __DRIscreen *sPriv )
1344{
1345   assert(sPriv->dri2.enabled);
1346
1347    sPriv->private = (void *) radeonCreateScreen2( sPriv );
1348    if ( !sPriv->private ) {
1349        radeonDestroyScreen( sPriv );
1350        return GL_FALSE;
1351    }
1352
1353    return GL_TRUE;
1354}
1355
1356
1357
1358/**
1359 * Create the Mesa framebuffer and renderbuffers for a given window/drawable.
1360 *
1361 * \todo This function (and its interface) will need to be updated to support
1362 * pbuffers.
1363 */
1364static GLboolean
1365radeonCreateBuffer( __DRIscreen *driScrnPriv,
1366                    __DRIdrawable *driDrawPriv,
1367                    const struct gl_config *mesaVis,
1368                    GLboolean isPixmap )
1369{
1370    radeonScreenPtr screen = (radeonScreenPtr) driScrnPriv->private;
1371
1372    const GLboolean swDepth = GL_FALSE;
1373    const GLboolean swAlpha = GL_FALSE;
1374    const GLboolean swAccum = mesaVis->accumRedBits > 0;
1375    const GLboolean swStencil = mesaVis->stencilBits > 0 &&
1376	mesaVis->depthBits != 24;
1377    gl_format rgbFormat;
1378    struct radeon_framebuffer *rfb;
1379
1380    if (isPixmap)
1381      return GL_FALSE; /* not implemented */
1382
1383    rfb = CALLOC_STRUCT(radeon_framebuffer);
1384    if (!rfb)
1385      return GL_FALSE;
1386
1387    _mesa_initialize_window_framebuffer(&rfb->base, mesaVis);
1388
1389    if (mesaVis->redBits == 5)
1390        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_RGB565 : MESA_FORMAT_RGB565_REV;
1391    else if (mesaVis->alphaBits == 0)
1392        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_XRGB8888 : MESA_FORMAT_XRGB8888_REV;
1393    else
1394        rgbFormat = _mesa_little_endian() ? MESA_FORMAT_ARGB8888 : MESA_FORMAT_ARGB8888_REV;
1395
1396    /* front color renderbuffer */
1397    rfb->color_rb[0] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1398    _mesa_add_renderbuffer(&rfb->base, BUFFER_FRONT_LEFT, &rfb->color_rb[0]->base);
1399    rfb->color_rb[0]->has_surface = 1;
1400
1401    /* back color renderbuffer */
1402    if (mesaVis->doubleBufferMode) {
1403      rfb->color_rb[1] = radeon_create_renderbuffer(rgbFormat, driDrawPriv);
1404	_mesa_add_renderbuffer(&rfb->base, BUFFER_BACK_LEFT, &rfb->color_rb[1]->base);
1405	rfb->color_rb[1]->has_surface = 1;
1406    }
1407
1408    if (mesaVis->depthBits == 24) {
1409      if (mesaVis->stencilBits == 8) {
1410	struct radeon_renderbuffer *depthStencilRb =
1411           radeon_create_renderbuffer(MESA_FORMAT_S8_Z24, driDrawPriv);
1412	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depthStencilRb->base);
1413	_mesa_add_renderbuffer(&rfb->base, BUFFER_STENCIL, &depthStencilRb->base);
1414	depthStencilRb->has_surface = screen->depthHasSurface;
1415      } else {
1416	/* depth renderbuffer */
1417	struct radeon_renderbuffer *depth =
1418           radeon_create_renderbuffer(MESA_FORMAT_X8_Z24, driDrawPriv);
1419	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1420	depth->has_surface = screen->depthHasSurface;
1421      }
1422    } else if (mesaVis->depthBits == 16) {
1423        /* just 16-bit depth buffer, no hw stencil */
1424	struct radeon_renderbuffer *depth =
1425           radeon_create_renderbuffer(MESA_FORMAT_Z16, driDrawPriv);
1426	_mesa_add_renderbuffer(&rfb->base, BUFFER_DEPTH, &depth->base);
1427	depth->has_surface = screen->depthHasSurface;
1428    }
1429
1430    _mesa_add_soft_renderbuffers(&rfb->base,
1431	    GL_FALSE, /* color */
1432	    swDepth,
1433	    swStencil,
1434	    swAccum,
1435	    swAlpha,
1436	    GL_FALSE /* aux */);
1437    driDrawPriv->driverPrivate = (void *) rfb;
1438
1439    return (driDrawPriv->driverPrivate != NULL);
1440}
1441
1442
1443static void radeon_cleanup_renderbuffers(struct radeon_framebuffer *rfb)
1444{
1445	struct radeon_renderbuffer *rb;
1446
1447	rb = rfb->color_rb[0];
1448	if (rb && rb->bo) {
1449		radeon_bo_unref(rb->bo);
1450		rb->bo = NULL;
1451	}
1452	rb = rfb->color_rb[1];
1453	if (rb && rb->bo) {
1454		radeon_bo_unref(rb->bo);
1455		rb->bo = NULL;
1456	}
1457	rb = radeon_get_renderbuffer(&rfb->base, BUFFER_DEPTH);
1458	if (rb && rb->bo) {
1459		radeon_bo_unref(rb->bo);
1460		rb->bo = NULL;
1461	}
1462}
1463
1464void
1465radeonDestroyBuffer(__DRIdrawable *driDrawPriv)
1466{
1467    struct radeon_framebuffer *rfb;
1468    if (!driDrawPriv)
1469	return;
1470
1471    rfb = (void*)driDrawPriv->driverPrivate;
1472    if (!rfb)
1473	return;
1474    radeon_cleanup_renderbuffers(rfb);
1475    _mesa_reference_framebuffer((struct gl_framebuffer **)(&(driDrawPriv->driverPrivate)), NULL);
1476}
1477
1478#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0]))
1479
1480/**
1481 * This is the driver specific part of the createNewScreen entry point.
1482 * Called when using DRI2.
1483 *
1484 * \return the struct gl_config supported by this driver
1485 */
1486static const
1487__DRIconfig **radeonInitScreen2(__DRIscreen *psp)
1488{
1489   GLenum fb_format[3];
1490   GLenum fb_type[3];
1491   /* GLX_SWAP_COPY_OML is only supported because the Intel driver doesn't
1492    * support pageflipping at all.
1493    */
1494   static const GLenum back_buffer_modes[] = {
1495     GLX_NONE, GLX_SWAP_UNDEFINED_OML, /*, GLX_SWAP_COPY_OML*/
1496   };
1497   uint8_t depth_bits[4], stencil_bits[4], msaa_samples_array[1];
1498   int color;
1499   __DRIconfig **configs = NULL;
1500
1501   if (!radeonInitDriver(psp)) {
1502       return NULL;
1503    }
1504   depth_bits[0] = 0;
1505   stencil_bits[0] = 0;
1506   depth_bits[1] = 16;
1507   stencil_bits[1] = 0;
1508   depth_bits[2] = 24;
1509   stencil_bits[2] = 0;
1510   depth_bits[3] = 24;
1511   stencil_bits[3] = 8;
1512
1513   msaa_samples_array[0] = 0;
1514
1515   fb_format[0] = GL_RGB;
1516   fb_type[0] = GL_UNSIGNED_SHORT_5_6_5;
1517
1518   fb_format[1] = GL_BGR;
1519   fb_type[1] = GL_UNSIGNED_INT_8_8_8_8_REV;
1520
1521   fb_format[2] = GL_BGRA;
1522   fb_type[2] = GL_UNSIGNED_INT_8_8_8_8_REV;
1523
1524   for (color = 0; color < ARRAY_SIZE(fb_format); color++) {
1525      __DRIconfig **new_configs;
1526
1527      new_configs = driCreateConfigs(fb_format[color], fb_type[color],
1528				     depth_bits,
1529				     stencil_bits,
1530				     ARRAY_SIZE(depth_bits),
1531				     back_buffer_modes,
1532				     ARRAY_SIZE(back_buffer_modes),
1533				     msaa_samples_array,
1534				     ARRAY_SIZE(msaa_samples_array),
1535				     GL_TRUE);
1536      if (configs == NULL)
1537	 configs = new_configs;
1538      else
1539	 configs = driConcatConfigs(configs, new_configs);
1540   }
1541
1542   if (configs == NULL) {
1543      fprintf(stderr, "[%s:%u] Error creating FBConfig!\n", __func__,
1544              __LINE__);
1545      return NULL;
1546   }
1547
1548   return (const __DRIconfig **)configs;
1549}
1550
1551/**
1552 * Get information about previous buffer swaps.
1553 */
1554static int
1555getSwapInfo( __DRIdrawable *dPriv, __DRIswapInfo * sInfo )
1556{
1557    struct radeon_framebuffer *rfb;
1558
1559    if ( (dPriv == NULL) || (dPriv->driContextPriv == NULL)
1560	 || (dPriv->driContextPriv->driverPrivate == NULL)
1561	 || (sInfo == NULL) ) {
1562	return -1;
1563   }
1564
1565    rfb = dPriv->driverPrivate;
1566    sInfo->swap_count = rfb->swap_count;
1567    sInfo->swap_ust = rfb->swap_ust;
1568    sInfo->swap_missed_count = rfb->swap_missed_count;
1569
1570   sInfo->swap_missed_usage = (sInfo->swap_missed_count != 0)
1571       ? driCalculateSwapUsage( dPriv, 0, rfb->swap_missed_ust )
1572       : 0.0;
1573
1574   return 0;
1575}
1576
1577const struct __DriverAPIRec driDriverAPI = {
1578   .DestroyScreen   = radeonDestroyScreen,
1579#if defined(RADEON_R200)
1580   .CreateContext   = r200CreateContext,
1581   .DestroyContext  = r200DestroyContext,
1582#else
1583   .CreateContext   = r100CreateContext,
1584   .DestroyContext  = radeonDestroyContext,
1585#endif
1586   .CreateBuffer    = radeonCreateBuffer,
1587   .DestroyBuffer   = radeonDestroyBuffer,
1588   .SwapBuffers     = radeonSwapBuffers,
1589   .MakeCurrent     = radeonMakeCurrent,
1590   .UnbindContext   = radeonUnbindContext,
1591   .GetSwapInfo     = getSwapInfo,
1592   .GetDrawableMSC  = driDrawableGetMSC32,
1593   .WaitForMSC      = driWaitForMSC32,
1594   .WaitForSBC      = NULL,
1595   .SwapBuffersMSC  = NULL,
1596   .CopySubBuffer   = radeonCopySubBuffer,
1597    /* DRI2 */
1598   .InitScreen2     = radeonInitScreen2,
1599};
1600
1601/* This is the table of extensions that the loader will dlsym() for. */
1602PUBLIC const __DRIextension *__driDriverExtensions[] = {
1603    &driCoreExtension.base,
1604    &driLegacyExtension.base,
1605    &driDRI2Extension.base,
1606    NULL
1607};
1608