1a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 2a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 3752f90673ebbb6b2f55fc5e46606dea371313713sewardj/*--- begin host_amd64_defs.h ---*/ 4a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 5a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 6a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/* 7752f90673ebbb6b2f55fc5e46606dea371313713sewardj This file is part of Valgrind, a dynamic binary instrumentation 8752f90673ebbb6b2f55fc5e46606dea371313713sewardj framework. 9a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 1089ae8477745fd2a15453557d729a50e627325ee2sewardj Copyright (C) 2004-2013 OpenWorks LLP 11752f90673ebbb6b2f55fc5e46606dea371313713sewardj info@open-works.net 12a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 13752f90673ebbb6b2f55fc5e46606dea371313713sewardj This program is free software; you can redistribute it and/or 14752f90673ebbb6b2f55fc5e46606dea371313713sewardj modify it under the terms of the GNU General Public License as 15752f90673ebbb6b2f55fc5e46606dea371313713sewardj published by the Free Software Foundation; either version 2 of the 16752f90673ebbb6b2f55fc5e46606dea371313713sewardj License, or (at your option) any later version. 17a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 18752f90673ebbb6b2f55fc5e46606dea371313713sewardj This program is distributed in the hope that it will be useful, but 19752f90673ebbb6b2f55fc5e46606dea371313713sewardj WITHOUT ANY WARRANTY; without even the implied warranty of 20752f90673ebbb6b2f55fc5e46606dea371313713sewardj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21752f90673ebbb6b2f55fc5e46606dea371313713sewardj General Public License for more details. 22752f90673ebbb6b2f55fc5e46606dea371313713sewardj 23752f90673ebbb6b2f55fc5e46606dea371313713sewardj You should have received a copy of the GNU General Public License 24752f90673ebbb6b2f55fc5e46606dea371313713sewardj along with this program; if not, write to the Free Software 25752f90673ebbb6b2f55fc5e46606dea371313713sewardj Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 267bd6ffe203f3aa9e7b25f7eae40a9b9cf48710cfsewardj 02110-1301, USA. 277bd6ffe203f3aa9e7b25f7eae40a9b9cf48710cfsewardj 28752f90673ebbb6b2f55fc5e46606dea371313713sewardj The GNU General Public License is contained in the file COPYING. 29a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 30a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj Neither the names of the U.S. Department of Energy nor the 31a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj University of California nor the names of its contributors may be 32a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj used to endorse or promote products derived from this software 33a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj without prior written permission. 34a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj*/ 35a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 36cef7d3e3df4796e35b4521158d9dc058f034aa87sewardj#ifndef __VEX_HOST_AMD64_DEFS_H 37cef7d3e3df4796e35b4521158d9dc058f034aa87sewardj#define __VEX_HOST_AMD64_DEFS_H 38a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 3958a637b6675d4d68e13d18b75cea7eee2a2a91feflorian#include "libvex_basictypes.h" 4058a637b6675d4d68e13d18b75cea7eee2a2a91feflorian#include "libvex.h" // VexArch 4158a637b6675d4d68e13d18b75cea7eee2a2a91feflorian#include "host_generic_regs.h" // HReg 42c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 43c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Registers. --------- */ 44c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 45c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* The usual HReg abstraction. There are 16 real int regs, 6 real 46c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj float regs, and 16 real vector regs. 47c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj*/ 48c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 49a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#define ST_IN static inline 50a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RSI ( void ) { return mkHReg(False, HRcInt64, 6, 0); } 51a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RDI ( void ) { return mkHReg(False, HRcInt64, 7, 1); } 52a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R8 ( void ) { return mkHReg(False, HRcInt64, 8, 2); } 53a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R9 ( void ) { return mkHReg(False, HRcInt64, 9, 3); } 54a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R12 ( void ) { return mkHReg(False, HRcInt64, 12, 4); } 55a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R13 ( void ) { return mkHReg(False, HRcInt64, 13, 5); } 56a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R14 ( void ) { return mkHReg(False, HRcInt64, 14, 6); } 57a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R15 ( void ) { return mkHReg(False, HRcInt64, 15, 7); } 58a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RBX ( void ) { return mkHReg(False, HRcInt64, 3, 8); } 59a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 60a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM3 ( void ) { return mkHReg(False, HRcVec128, 3, 9); } 61a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM4 ( void ) { return mkHReg(False, HRcVec128, 4, 10); } 62a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM5 ( void ) { return mkHReg(False, HRcVec128, 5, 11); } 63a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM6 ( void ) { return mkHReg(False, HRcVec128, 6, 12); } 64a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM7 ( void ) { return mkHReg(False, HRcVec128, 7, 13); } 65a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM8 ( void ) { return mkHReg(False, HRcVec128, 8, 14); } 66a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM9 ( void ) { return mkHReg(False, HRcVec128, 9, 15); } 67a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM10 ( void ) { return mkHReg(False, HRcVec128, 10, 16); } 68a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM11 ( void ) { return mkHReg(False, HRcVec128, 11, 17); } 69a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM12 ( void ) { return mkHReg(False, HRcVec128, 12, 18); } 70a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 71a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R10 ( void ) { return mkHReg(False, HRcInt64, 10, 19); } 72a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 73a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RAX ( void ) { return mkHReg(False, HRcInt64, 0, 20); } 74a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RCX ( void ) { return mkHReg(False, HRcInt64, 1, 21); } 75a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RDX ( void ) { return mkHReg(False, HRcInt64, 2, 22); } 76a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RSP ( void ) { return mkHReg(False, HRcInt64, 4, 23); } 77a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_RBP ( void ) { return mkHReg(False, HRcInt64, 5, 24); } 78a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_R11 ( void ) { return mkHReg(False, HRcInt64, 11, 25); } 79a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 80a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM0 ( void ) { return mkHReg(False, HRcVec128, 0, 26); } 81a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjST_IN HReg hregAMD64_XMM1 ( void ) { return mkHReg(False, HRcVec128, 1, 27); } 82a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj#undef ST_IN 83c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 84a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjextern void ppHRegAMD64 ( HReg ); 85c4530ae9079b0c3f8d4e8df35073613d718cadecsewardj 86c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 87c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Condition codes, AMD encoding. --------- */ 88c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 89c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 90c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 91c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_O = 0, /* overflow */ 92c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NO = 1, /* no overflow */ 93c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 94c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_B = 2, /* below */ 95c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NB = 3, /* not below */ 96c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 97c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_Z = 4, /* zero */ 98c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NZ = 5, /* not zero */ 99c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 100c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_BE = 6, /* below or equal */ 101c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NBE = 7, /* not below or equal */ 102c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 103c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_S = 8, /* negative */ 104c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NS = 9, /* not negative */ 105c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 106c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_P = 10, /* parity even */ 107c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NP = 11, /* not parity even */ 108c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 109c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_L = 12, /* jump less */ 110c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NL = 13, /* not less */ 111c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 112c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_LE = 14, /* less or equal */ 113c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NLE = 15, /* not less or equal */ 114c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 115c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_ALWAYS = 16 /* the usual hack */ 116c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 117c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64CondCode; 118c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 11955085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar* showAMD64CondCode ( AMD64CondCode ); 120c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 121c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 122c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Memory address expressions (amodes). --------- */ 123c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 124c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 125c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 126c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Aam_IR, /* Immediate + Reg */ 127c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Aam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ 128c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 129c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AModeTag; 130c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 131c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 132c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 133c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AModeTag tag; 134c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 135c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 136c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm; 137c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 138c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } IR; 139c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 140c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm; 141c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg base; 142c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg index; 143c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Int shift; /* 0, 1, 2 or 3 only */ 144c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } IRRS; 145c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Aam; 146c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 147c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AMode; 148c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 149c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64AMode* AMD64AMode_IR ( UInt, HReg ); 150c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int ); 151c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 152c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64AMode* dopyAMD64AMode ( AMD64AMode* ); 153c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 154c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64AMode ( AMD64AMode* ); 155c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 156c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 157c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Operand, which can be reg, immediate or memory. --------- */ 158c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 159c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 160c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 161c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi_Imm, 162c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi_Reg, 163c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi_Mem 164c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 165c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMITag; 166c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 167c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 168c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 169c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMITag tag; 170c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 171c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 172c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm32; 173c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Imm; 174c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 175c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 176c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Reg; 177c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 178c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AMode* am; 179c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Mem; 180c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 181c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi; 182c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 183c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMI; 184c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 185c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RMI* AMD64RMI_Imm ( UInt ); 186c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RMI* AMD64RMI_Reg ( HReg ); 187c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* ); 188c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 1899cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardjextern void ppAMD64RMI ( AMD64RMI* ); 1909cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardjextern void ppAMD64RMI_lo32 ( AMD64RMI* ); 191c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 192c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 193c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Operand, which can be reg or immediate only. --------- */ 194c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 195c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 196c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 197c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ari_Imm, 198c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ari_Reg 199c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 200c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RITag; 201c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 202c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 203c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 204c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RITag tag; 205c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 206c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 207c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm32; 208c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Imm; 209c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 210c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 211c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Reg; 212c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 213c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ari; 214c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 215c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RI; 216c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 217c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RI* AMD64RI_Imm ( UInt ); 218c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RI* AMD64RI_Reg ( HReg ); 219c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 220c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64RI ( AMD64RI* ); 221c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 222c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 223c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Operand, which can be reg or memory only. --------- */ 224c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 225c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 226c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 227c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Arm_Reg, 228c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Arm_Mem 229c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 230c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMTag; 231c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 232c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 233c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 234c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMTag tag; 235c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 236c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 237c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 238c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Reg; 239c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 240c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AMode* am; 241c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Mem; 242c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 243c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Arm; 244c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 245c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RM; 246c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 247c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RM* AMD64RM_Reg ( HReg ); 248c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RM* AMD64RM_Mem ( AMD64AMode* ); 249c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 250c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64RM ( AMD64RM* ); 251c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 252c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 253d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj/* --------- Instructions. --------- */ 254d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj 255d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj/* --------- */ 256d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardjtypedef 257d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj enum { 258d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj Aun_NEG, 259d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj Aun_NOT 260d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj } 261d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj AMD64UnaryOp; 262d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj 26355085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar* showAMD64UnaryOp ( AMD64UnaryOp ); 264614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 265614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 266614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj/* --------- */ 267614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardjtypedef 268614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj enum { 269614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_INVALID, 270614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_MOV, 271614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_CMP, 272614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB, 273614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_AND, Aalu_OR, Aalu_XOR, 274614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_MUL 275614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } 276614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AluOp; 277614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 27855085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar* showAMD64AluOp ( AMD64AluOp ); 279614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 280614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 2818258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj/* --------- */ 2828258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardjtypedef 2838258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj enum { 2848258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Ash_INVALID, 2858258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Ash_SHL, Ash_SHR, Ash_SAR 2868258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj } 2878258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64ShiftOp; 2888258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj 28955085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar* showAMD64ShiftOp ( AMD64ShiftOp ); 2908258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj 2918258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj 29225a858136df4cbea0055c20aa7035d25fd40ee89sewardj/* --------- */ 29325a858136df4cbea0055c20aa7035d25fd40ee89sewardjtypedef 29425a858136df4cbea0055c20aa7035d25fd40ee89sewardj enum { 29525a858136df4cbea0055c20aa7035d25fd40ee89sewardj Afp_INVALID, 29625a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* Binary */ 2974970e4e219cb92ef15de742d102c537ea33d5430sewardj Afp_SCALE, Afp_ATAN, Afp_YL2X, Afp_YL2XP1, Afp_PREM, Afp_PREM1, 29825a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* Unary */ 2994796d668897d3b2108831df2de2c16b9bed5ead8sewardj Afp_SQRT, 3005e205372f0023f11eb756ee38de40a065b0681c1sewardj Afp_SIN, Afp_COS, Afp_TAN, 30125a858136df4cbea0055c20aa7035d25fd40ee89sewardj Afp_ROUND, Afp_2XM1 30225a858136df4cbea0055c20aa7035d25fd40ee89sewardj } 30325a858136df4cbea0055c20aa7035d25fd40ee89sewardj A87FpOp; 30425a858136df4cbea0055c20aa7035d25fd40ee89sewardj 30555085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar* showA87FpOp ( A87FpOp ); 3061001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj 3071001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj 3081001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj/* --------- */ 3091001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjtypedef 3101001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj enum { 3111001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_INVALID, 3121001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* mov */ 3131001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_MOV, 3141001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* Floating point binary */ 3151001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF, 3161a01e65f9993d97095c2af463e98674a091834casewardj Asse_MAXF, Asse_MINF, 3178d965316c72c2392f670dcdfa127547ec77c7e56sewardj Asse_CMPEQF, Asse_CMPLTF, Asse_CMPLEF, Asse_CMPUNF, 3181001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* Floating point unary */ 3191001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_RCPF, Asse_RSQRTF, Asse_SQRTF, 3201001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* Bitwise */ 3211001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN, 322976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_ADD8, Asse_ADD16, Asse_ADD32, Asse_ADD64, 3235992bd07a3237cae1c22f6c93c43730e6447350csewardj Asse_QADD8U, Asse_QADD16U, 3245992bd07a3237cae1c22f6c93c43730e6447350csewardj Asse_QADD8S, Asse_QADD16S, 325976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_SUB8, Asse_SUB16, Asse_SUB32, Asse_SUB64, 326976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_QSUB8U, Asse_QSUB16U, 327976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_QSUB8S, Asse_QSUB16S, 328adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MUL16, 329adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MULHI16U, 330adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MULHI16S, 3315992bd07a3237cae1c22f6c93c43730e6447350csewardj Asse_AVG8U, Asse_AVG16U, 332adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MAX16S, 333adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MAX8U, 334adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MIN16S, 335adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_MIN8U, 3365992bd07a3237cae1c22f6c93c43730e6447350csewardj Asse_CMPEQ8, Asse_CMPEQ16, Asse_CMPEQ32, 3375992bd07a3237cae1c22f6c93c43730e6447350csewardj Asse_CMPGT8S, Asse_CMPGT16S, Asse_CMPGT32S, 338adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_SHL16, Asse_SHL32, Asse_SHL64, 339adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_SHR16, Asse_SHR32, Asse_SHR64, 340adffcef004712e8afc6a7d87b30ef90e4685df40sewardj Asse_SAR16, Asse_SAR32, 341976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_PACKSSD, Asse_PACKSSW, Asse_PACKUSW, 342976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_UNPCKHB, Asse_UNPCKHW, Asse_UNPCKHD, Asse_UNPCKHQ, 343976285992e00e9b3656f08d0e08e62e65ec6a29fsewardj Asse_UNPCKLB, Asse_UNPCKLW, Asse_UNPCKLD, Asse_UNPCKLQ 3441001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } 3451001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64SseOp; 3461001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj 34755085f8680acc89d727e321f3b34cae1a8c4093aflorianextern const HChar* showAMD64SseOp ( AMD64SseOp ); 348c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 349c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 350c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- */ 351c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 352c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 35325a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Imm64, /* Generate 64-bit literal to register */ 35425a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Alu64R, /* 64-bit mov/arith/logical, dst=REG */ 35525a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Alu64M, /* 64-bit mov/arith/logical, dst=MEM */ 35625a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Sh64, /* 64-bit shift/rotate, dst=REG or MEM */ 35725a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Test64, /* 64-bit test (AND, set flags, discard result) */ 35825a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Unary64, /* 64-bit not and neg */ 3596ce1a23b27d1729da9d705abd15b2007dce8daecsewardj Ain_Lea64, /* 64-bit compute EA into a reg */ 3609cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj Ain_Alu32R, /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */ 36125a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_MulL, /* widening multiply */ 36225a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Div, /* div and mod */ 36325a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Push, /* push 64-bit value on stack */ 36425a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Call, /* call to address in register */ 365c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Ain_XDirect, /* direct transfer to GA */ 366c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Ain_XIndir, /* indirect transfer to GA */ 367c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Ain_XAssisted, /* assisted transfer to GA */ 368e357c67787b7429f85a030ee5fbedf33173b5656sewardj Ain_CMov64, /* conditional move, 64-bit reg-reg only */ 369bdea5508b371d394c81b91464fa8df767010d4dasewardj Ain_CLoad, /* cond. load to int reg, 32 bit ZX or 64 bit only */ 3706f1ec58d9806064dea0000e4b543aacded9b11easewardj Ain_CStore, /* cond. store from int reg, 32 or 64 bit only */ 371ca257bc572147c1a9c7d9a2e81237125a35ff25dsewardj Ain_MovxLQ, /* reg-reg move, zx-ing/sx-ing top half */ 37225a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ 37325a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Store, /* store 32/16/8 bit value in memory */ 37425a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Set64, /* convert condition code to 64-bit value */ 37525a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Bsfr64, /* 64-bit bsf/bsr */ 37625a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_MFence, /* mem fence */ 377e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj Ain_ACAS, /* 8/16/32/64-bit lock;cmpxchg */ 378e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj Ain_DACAS, /* lock;cmpxchg8b/16b (doubleword ACAS, 2 x 379e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj 32-bit or 2 x 64-bit only) */ 38025a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_A87Free, /* free up x87 registers */ 38125a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_A87PushPop, /* x87 loads/stores */ 38225a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_A87FpOp, /* x87 operations */ 38325a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_A87LdCW, /* load x87 control word */ 384f4c803b0947e7534809589cba8007851d78c7a2esewardj Ain_A87StSW, /* store x87 status word */ 38525a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_LdMXCSR, /* load %mxcsr */ 38625a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int 38725a858136df4cbea0055c20aa7035d25fd40ee89sewardj register */ 38825a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseSI2SF, /* scalar 32/64 int to 32/64 float conversion */ 38925a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseSF2SI, /* scalar 32/64 float to 32/64 int conversion */ 39025a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseSDSS, /* scalar float32 to/from float64 */ 39125a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment 39225a858136df4cbea0055c20aa7035d25fd40ee89sewardj constraints, upper 96/64/0 bits arbitrary */ 39325a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ 39425a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Sse32Fx4, /* SSE binary, 32Fx4 */ 39525a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Sse32FLo, /* SSE binary, 32F in lowest lane only */ 39625a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Sse64Fx2, /* SSE binary, 64Fx2 */ 39725a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */ 39825a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */ 39925a858136df4cbea0055c20aa7035d25fd40ee89sewardj Ain_SseCMov, /* SSE conditional move */ 400c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Ain_SseShuf, /* SSE2 shuffle (pshufd) */ 4013616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu Ain_AvxLdSt, /* AVX load/store 256 bits, 4023616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu no alignment constraints */ 4033616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu Ain_AvxReRg, /* AVX binary general reg-reg, Re, Rg */ 404c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Ain_EvCheck, /* Event check */ 405c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Ain_ProfInc /* 64-bit profile counter increment */ 406c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 407c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64InstrTag; 408c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 409c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* Destinations are on the RIGHT (second operand) */ 410c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 411c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 412c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 413c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64InstrTag tag; 414614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj union { 415614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj struct { 41653df0616a3a742eac96754b692e42c1d8610e10esewardj ULong imm64; 41753df0616a3a742eac96754b692e42c1d8610e10esewardj HReg dst; 41853df0616a3a742eac96754b692e42c1d8610e10esewardj } Imm64; 41953df0616a3a742eac96754b692e42c1d8610e10esewardj struct { 420614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AluOp op; 421614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64RMI* src; 422614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj HReg dst; 423614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } Alu64R; 424614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj struct { 425614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AluOp op; 426614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64RI* src; 427614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AMode* dst; 428614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } Alu64M; 4298258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj struct { 4308258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64ShiftOp op; 4318258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj UInt src; /* shift amount, or 0 means %cl */ 432501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardj HReg dst; 4338258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj } Sh64; 43405b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj struct { 435501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardj UInt imm32; 436501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardj HReg dst; 43705b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj } Test64; 438d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj /* Not and Neg */ 439d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj struct { 440d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj AMD64UnaryOp op; 441501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardj HReg dst; 442d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj } Unary64; 4436ce1a23b27d1729da9d705abd15b2007dce8daecsewardj /* 64-bit compute EA into a reg */ 4446ce1a23b27d1729da9d705abd15b2007dce8daecsewardj struct { 4456ce1a23b27d1729da9d705abd15b2007dce8daecsewardj AMD64AMode* am; 4466ce1a23b27d1729da9d705abd15b2007dce8daecsewardj HReg dst; 4476ce1a23b27d1729da9d705abd15b2007dce8daecsewardj } Lea64; 4489cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj /* 32-bit add/sub/and/or/xor/cmp, dst=REG (a la Alu64R) */ 4499cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj struct { 4509cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj AMD64AluOp op; 4519cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj AMD64RMI* src; 4529cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj HReg dst; 4539cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardj } Alu32R; 454501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardj /* 64 x 64 -> 128 bit widening multiply: RDX:RAX = RAX *s/u 455501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardj r/m64 */ 4569b96767debeeb1f78378f0e7e295fe6762c64002sewardj struct { 4579b96767debeeb1f78378f0e7e295fe6762c64002sewardj Bool syned; 4589b96767debeeb1f78378f0e7e295fe6762c64002sewardj AMD64RM* src; 4599b96767debeeb1f78378f0e7e295fe6762c64002sewardj } MulL; 4607de0d3c800437fbd82c59d57d156f4823d67609fsewardj /* amd64 div/idiv instruction. Modifies RDX and RAX and 4617de0d3c800437fbd82c59d57d156f4823d67609fsewardj reads src. */ 4627de0d3c800437fbd82c59d57d156f4823d67609fsewardj struct { 4637de0d3c800437fbd82c59d57d156f4823d67609fsewardj Bool syned; 4647de0d3c800437fbd82c59d57d156f4823d67609fsewardj Int sz; /* 4 or 8 only */ 4657de0d3c800437fbd82c59d57d156f4823d67609fsewardj AMD64RM* src; 4667de0d3c800437fbd82c59d57d156f4823d67609fsewardj } Div; 4671001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 4681001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64RMI* src; 4691001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } Push; 47005b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj /* Pseudo-insn. Call target (an absolute address), on given 47105b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj condition (which could be Xcc_ALWAYS). */ 47205b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj struct { 47305b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64CondCode cond; 47405b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Addr64 target; 47505b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Int regparms; /* 0 .. 6 */ 476cfe046e178666280b87da998b1b52ecda03ecd89sewardj RetLoc rloc; /* where the return value will be */ 47705b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj } Call; 478c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj /* Update the guest RIP value, then exit requesting to chain 479c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj to it. May be conditional. */ 480c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj struct { 481c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Addr64 dstGA; /* next guest address */ 482c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64AMode* amRIP; /* amode in guest state for RIP */ 483c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64CondCode cond; /* can be Acc_ALWAYS */ 484c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Bool toFastEP; /* chain to the slow or fast point? */ 485c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj } XDirect; 486c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj /* Boring transfer to a guest address not known at JIT time. 487c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Not chainable. May be conditional. */ 488c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj struct { 489c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj HReg dstGA; 490c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64AMode* amRIP; 491c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64CondCode cond; /* can be Acc_ALWAYS */ 492c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj } XIndir; 493c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj /* Assisted transfer to a guest address, most general case. 494c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Not chainable. May be conditional. */ 495c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj struct { 496c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj HReg dstGA; 497c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64AMode* amRIP; 498c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64CondCode cond; /* can be Acc_ALWAYS */ 499f67eadf04f5150178e589060f03381300d28e540sewardj IRJumpKind jk; 500c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj } XAssisted; 50105b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj /* Mov src to dst on the given condition, which may not 50205b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj be the bogus Acc_ALWAYS. */ 50305b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj struct { 50405b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64CondCode cond; 505e357c67787b7429f85a030ee5fbedf33173b5656sewardj HReg src; 50605b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj HReg dst; 50705b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj } CMov64; 508bdea5508b371d394c81b91464fa8df767010d4dasewardj /* conditional load to int reg, 32 bit ZX or 64 bit only. 509bdea5508b371d394c81b91464fa8df767010d4dasewardj cond may not be Acc_ALWAYS. */ 510bdea5508b371d394c81b91464fa8df767010d4dasewardj struct { 511bdea5508b371d394c81b91464fa8df767010d4dasewardj AMD64CondCode cond; 512bdea5508b371d394c81b91464fa8df767010d4dasewardj UChar szB; /* 4 or 8 only */ 513bdea5508b371d394c81b91464fa8df767010d4dasewardj AMD64AMode* addr; 514bdea5508b371d394c81b91464fa8df767010d4dasewardj HReg dst; 515bdea5508b371d394c81b91464fa8df767010d4dasewardj } CLoad; 5166f1ec58d9806064dea0000e4b543aacded9b11easewardj /* cond. store from int reg, 32 or 64 bit only. 5176f1ec58d9806064dea0000e4b543aacded9b11easewardj cond may not be Acc_ALWAYS. */ 5186f1ec58d9806064dea0000e4b543aacded9b11easewardj struct { 5196f1ec58d9806064dea0000e4b543aacded9b11easewardj AMD64CondCode cond; 5206f1ec58d9806064dea0000e4b543aacded9b11easewardj UChar szB; /* 4 or 8 only */ 5216f1ec58d9806064dea0000e4b543aacded9b11easewardj HReg src; 5226f1ec58d9806064dea0000e4b543aacded9b11easewardj AMD64AMode* addr; 5236f1ec58d9806064dea0000e4b543aacded9b11easewardj } CStore; 524ca257bc572147c1a9c7d9a2e81237125a35ff25dsewardj /* reg-reg move, sx-ing/zx-ing top half */ 525f67eadf04f5150178e589060f03381300d28e540sewardj struct { 526ca257bc572147c1a9c7d9a2e81237125a35ff25dsewardj Bool syned; 527f67eadf04f5150178e589060f03381300d28e540sewardj HReg src; 528f67eadf04f5150178e589060f03381300d28e540sewardj HReg dst; 529ca257bc572147c1a9c7d9a2e81237125a35ff25dsewardj } MovxLQ; 5308258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj /* Sign/Zero extending loads. Dst size is always 64 bits. */ 5318258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj struct { 5321830386e7b10430c0c3630123a82d8bcf0a071e7sewardj UChar szSmall; /* only 1, 2 or 4 */ 5338258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Bool syned; 5348258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64AMode* src; 5358258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj HReg dst; 5368258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj } LoadEX; 537f67eadf04f5150178e589060f03381300d28e540sewardj /* 32/16/8 bit stores. */ 538f67eadf04f5150178e589060f03381300d28e540sewardj struct { 539f67eadf04f5150178e589060f03381300d28e540sewardj UChar sz; /* only 1, 2 or 4 */ 540f67eadf04f5150178e589060f03381300d28e540sewardj HReg src; 541f67eadf04f5150178e589060f03381300d28e540sewardj AMD64AMode* dst; 542f67eadf04f5150178e589060f03381300d28e540sewardj } Store; 543a5bd0aff6eda3e7c312f51ae6bc742ea62b5d404sewardj /* Convert an amd64 condition code to a 64-bit value (0 or 1). */ 544a5bd0aff6eda3e7c312f51ae6bc742ea62b5d404sewardj struct { 545a5bd0aff6eda3e7c312f51ae6bc742ea62b5d404sewardj AMD64CondCode cond; 546a5bd0aff6eda3e7c312f51ae6bc742ea62b5d404sewardj HReg dst; 547a5bd0aff6eda3e7c312f51ae6bc742ea62b5d404sewardj } Set64; 548f53b7359a342e7d79090615169c6583a1a75fbcesewardj /* 64-bit bsf or bsr. */ 549f53b7359a342e7d79090615169c6583a1a75fbcesewardj struct { 550f53b7359a342e7d79090615169c6583a1a75fbcesewardj Bool isFwds; 551f53b7359a342e7d79090615169c6583a1a75fbcesewardj HReg src; 552f53b7359a342e7d79090615169c6583a1a75fbcesewardj HReg dst; 553f53b7359a342e7d79090615169c6583a1a75fbcesewardj } Bsfr64; 554d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj /* Mem fence. In short, an insn which flushes all preceding 555d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj loads and stores as much as possible before continuing. 556d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj On AMD64 we emit a real "mfence". */ 557d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj struct { 558d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj } MFence; 559e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj struct { 560e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj AMD64AMode* addr; 561e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj UChar sz; /* 1, 2, 4 or 8 */ 562e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj } ACAS; 563e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj struct { 564e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj AMD64AMode* addr; 565e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj UChar sz; /* 4 or 8 only */ 566e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj } DACAS; 567d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj 56825a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* --- X87 --- */ 56925a858136df4cbea0055c20aa7035d25fd40ee89sewardj 57025a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* A very minimal set of x87 insns, that operate exactly in a 57125a858136df4cbea0055c20aa7035d25fd40ee89sewardj stack-like way so no need to think about x87 registers. */ 57225a858136df4cbea0055c20aa7035d25fd40ee89sewardj 57325a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* Do 'ffree' on %st(7) .. %st(7-nregs) */ 57425a858136df4cbea0055c20aa7035d25fd40ee89sewardj struct { 57525a858136df4cbea0055c20aa7035d25fd40ee89sewardj Int nregs; /* 1 <= nregs <= 7 */ 57625a858136df4cbea0055c20aa7035d25fd40ee89sewardj } A87Free; 57725a858136df4cbea0055c20aa7035d25fd40ee89sewardj 578d15b597a8a006b3fe136cbf6cdf5b46ed532a4d8sewardj /* Push a 32- or 64-bit FP value from memory onto the stack, 579d15b597a8a006b3fe136cbf6cdf5b46ed532a4d8sewardj or move a value from the stack to memory and remove it 580d15b597a8a006b3fe136cbf6cdf5b46ed532a4d8sewardj from the stack. */ 58125a858136df4cbea0055c20aa7035d25fd40ee89sewardj struct { 58225a858136df4cbea0055c20aa7035d25fd40ee89sewardj AMD64AMode* addr; 58325a858136df4cbea0055c20aa7035d25fd40ee89sewardj Bool isPush; 584d15b597a8a006b3fe136cbf6cdf5b46ed532a4d8sewardj UChar szB; /* 4 or 8 */ 58525a858136df4cbea0055c20aa7035d25fd40ee89sewardj } A87PushPop; 58625a858136df4cbea0055c20aa7035d25fd40ee89sewardj 58725a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* Do an operation on the top-of-stack. This can be unary, in 58825a858136df4cbea0055c20aa7035d25fd40ee89sewardj which case it is %st0 = OP( %st0 ), or binary: %st0 = OP( 58925a858136df4cbea0055c20aa7035d25fd40ee89sewardj %st0, %st1 ). */ 59025a858136df4cbea0055c20aa7035d25fd40ee89sewardj struct { 59125a858136df4cbea0055c20aa7035d25fd40ee89sewardj A87FpOp op; 59225a858136df4cbea0055c20aa7035d25fd40ee89sewardj } A87FpOp; 59325a858136df4cbea0055c20aa7035d25fd40ee89sewardj 59425a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* Load the FPU control word. */ 59525a858136df4cbea0055c20aa7035d25fd40ee89sewardj struct { 59625a858136df4cbea0055c20aa7035d25fd40ee89sewardj AMD64AMode* addr; 59725a858136df4cbea0055c20aa7035d25fd40ee89sewardj } A87LdCW; 59825a858136df4cbea0055c20aa7035d25fd40ee89sewardj 599f4c803b0947e7534809589cba8007851d78c7a2esewardj /* Store the FPU status word (fstsw m16) */ 600f4c803b0947e7534809589cba8007851d78c7a2esewardj struct { 601f4c803b0947e7534809589cba8007851d78c7a2esewardj AMD64AMode* addr; 602f4c803b0947e7534809589cba8007851d78c7a2esewardj } A87StSW; 603f4c803b0947e7534809589cba8007851d78c7a2esewardj 60425a858136df4cbea0055c20aa7035d25fd40ee89sewardj /* --- SSE --- */ 60525a858136df4cbea0055c20aa7035d25fd40ee89sewardj 6061a01e65f9993d97095c2af463e98674a091834casewardj /* Load 32 bits into %mxcsr. */ 6071a01e65f9993d97095c2af463e98674a091834casewardj struct { 6081a01e65f9993d97095c2af463e98674a091834casewardj AMD64AMode* addr; 6091a01e65f9993d97095c2af463e98674a091834casewardj } 6101a01e65f9993d97095c2af463e98674a091834casewardj LdMXCSR; 6111830386e7b10430c0c3630123a82d8bcf0a071e7sewardj /* ucomisd/ucomiss, then get %rflags into int register */ 6121830386e7b10430c0c3630123a82d8bcf0a071e7sewardj struct { 6131830386e7b10430c0c3630123a82d8bcf0a071e7sewardj UChar sz; /* 4 or 8 only */ 6141830386e7b10430c0c3630123a82d8bcf0a071e7sewardj HReg srcL; /* xmm */ 6151830386e7b10430c0c3630123a82d8bcf0a071e7sewardj HReg srcR; /* xmm */ 6161830386e7b10430c0c3630123a82d8bcf0a071e7sewardj HReg dst; /* int */ 6171830386e7b10430c0c3630123a82d8bcf0a071e7sewardj } SseUComIS; 6181a01e65f9993d97095c2af463e98674a091834casewardj /* scalar 32/64 int to 32/64 float conversion */ 6191a01e65f9993d97095c2af463e98674a091834casewardj struct { 6201a01e65f9993d97095c2af463e98674a091834casewardj UChar szS; /* 4 or 8 */ 6211a01e65f9993d97095c2af463e98674a091834casewardj UChar szD; /* 4 or 8 */ 6221a01e65f9993d97095c2af463e98674a091834casewardj HReg src; /* i class */ 6231a01e65f9993d97095c2af463e98674a091834casewardj HReg dst; /* v class */ 6241a01e65f9993d97095c2af463e98674a091834casewardj } SseSI2SF; 6251a01e65f9993d97095c2af463e98674a091834casewardj /* scalar 32/64 float to 32/64 int conversion */ 6261a01e65f9993d97095c2af463e98674a091834casewardj struct { 6271a01e65f9993d97095c2af463e98674a091834casewardj UChar szS; /* 4 or 8 */ 6281a01e65f9993d97095c2af463e98674a091834casewardj UChar szD; /* 4 or 8 */ 6291a01e65f9993d97095c2af463e98674a091834casewardj HReg src; /* v class */ 6301a01e65f9993d97095c2af463e98674a091834casewardj HReg dst; /* i class */ 6311a01e65f9993d97095c2af463e98674a091834casewardj } SseSF2SI; 6328d965316c72c2392f670dcdfa127547ec77c7e56sewardj /* scalar float32 to/from float64 */ 6338d965316c72c2392f670dcdfa127547ec77c7e56sewardj struct { 6348d965316c72c2392f670dcdfa127547ec77c7e56sewardj Bool from64; /* True: 64->32; False: 32->64 */ 6358d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg src; 6368d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg dst; 6378d965316c72c2392f670dcdfa127547ec77c7e56sewardj } SseSDSS; 6381001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 6391001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Bool isLoad; 6401830386e7b10430c0c3630123a82d8bcf0a071e7sewardj UChar sz; /* 4, 8 or 16 only */ 6411001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg reg; 6421001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64AMode* addr; 6431001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } SseLdSt; 6441001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 6451001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Int sz; /* 4 or 8 only */ 6461001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg reg; 6471001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64AMode* addr; 6481001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } SseLdzLO; 6498d965316c72c2392f670dcdfa127547ec77c7e56sewardj struct { 6508d965316c72c2392f670dcdfa127547ec77c7e56sewardj AMD64SseOp op; 6518d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg src; 6528d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg dst; 6538d965316c72c2392f670dcdfa127547ec77c7e56sewardj } Sse32Fx4; 6548d965316c72c2392f670dcdfa127547ec77c7e56sewardj struct { 6558d965316c72c2392f670dcdfa127547ec77c7e56sewardj AMD64SseOp op; 6568d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg src; 6578d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg dst; 6588d965316c72c2392f670dcdfa127547ec77c7e56sewardj } Sse32FLo; 6594c328cf28ebd12977fbf837c44a614c5aac660f3sewardj struct { 6604c328cf28ebd12977fbf837c44a614c5aac660f3sewardj AMD64SseOp op; 6614c328cf28ebd12977fbf837c44a614c5aac660f3sewardj HReg src; 6624c328cf28ebd12977fbf837c44a614c5aac660f3sewardj HReg dst; 6634c328cf28ebd12977fbf837c44a614c5aac660f3sewardj } Sse64Fx2; 6641001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 6651001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64SseOp op; 6661001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg src; 6671001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg dst; 6681001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } Sse64FLo; 6691001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 6701001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64SseOp op; 6711001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg src; 6721001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg dst; 6731001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } SseReRg; 6748d965316c72c2392f670dcdfa127547ec77c7e56sewardj /* Mov src to dst on the given condition, which may not 6758d965316c72c2392f670dcdfa127547ec77c7e56sewardj be the bogus Xcc_ALWAYS. */ 6768d965316c72c2392f670dcdfa127547ec77c7e56sewardj struct { 6778d965316c72c2392f670dcdfa127547ec77c7e56sewardj AMD64CondCode cond; 6788d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg src; 6798d965316c72c2392f670dcdfa127547ec77c7e56sewardj HReg dst; 6808d965316c72c2392f670dcdfa127547ec77c7e56sewardj } SseCMov; 68109717341a0c364814e35bf405e61399d0e45fa7csewardj struct { 68209717341a0c364814e35bf405e61399d0e45fa7csewardj Int order; /* 0 <= order <= 0xFF */ 68309717341a0c364814e35bf405e61399d0e45fa7csewardj HReg src; 68409717341a0c364814e35bf405e61399d0e45fa7csewardj HReg dst; 68509717341a0c364814e35bf405e61399d0e45fa7csewardj } SseShuf; 6863616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu struct { 6873616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu Bool isLoad; 6883616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu HReg reg; 6893616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu AMD64AMode* addr; 6903616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu } AvxLdSt; 6913616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu struct { 6923616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu AMD64SseOp op; 6933616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu HReg src; 6943616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu HReg dst; 6953616a2ec4af166a3917810e4fdbe910ed80bd278sewardj //uu } AvxReRg; 696c4530ae9079b0c3f8d4e8df35073613d718cadecsewardj struct { 697c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64AMode* amCounter; 698c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64AMode* amFailAddr; 699c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj } EvCheck; 700c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj struct { 701c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj /* No fields. The address of the counter to inc is 702c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj installed later, post-translation, by patching it in, 703c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj as it is not known at translation time. */ 704c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj } ProfInc; 705614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 706614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } Ain; 707c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 708c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64Instr; 709c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 71025a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ); 71125a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg ); 71225a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64AMode* ); 713501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardjextern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, HReg dst ); 7146ce1a23b27d1729da9d705abd15b2007dce8daecsewardjextern AMD64Instr* AMD64Instr_Lea64 ( AMD64AMode* am, HReg dst ); 7159cc2bbf8496403cf998aec6152c086cd66b8bcdfsewardjextern AMD64Instr* AMD64Instr_Alu32R ( AMD64AluOp, AMD64RMI*, HReg ); 716501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardjextern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, HReg ); 717501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardjextern AMD64Instr* AMD64Instr_Test64 ( UInt imm32, HReg dst ); 718501a339ba08d28f30eb96d17b3f5bbe996ca6a4dsewardjextern AMD64Instr* AMD64Instr_MulL ( Bool syned, AMD64RM* ); 71925a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* ); 72025a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); 721cfe046e178666280b87da998b1b52ecda03ecd89sewardjextern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int, RetLoc ); 722c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern AMD64Instr* AMD64Instr_XDirect ( Addr64 dstGA, AMD64AMode* amRIP, 723c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64CondCode cond, Bool toFastEP ); 724c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern AMD64Instr* AMD64Instr_XIndir ( HReg dstGA, AMD64AMode* amRIP, 725c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64CondCode cond ); 726c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern AMD64Instr* AMD64Instr_XAssisted ( HReg dstGA, AMD64AMode* amRIP, 727c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64CondCode cond, IRJumpKind jk ); 728e357c67787b7429f85a030ee5fbedf33173b5656sewardjextern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, HReg src, HReg dst ); 729bdea5508b371d394c81b91464fa8df767010d4dasewardjextern AMD64Instr* AMD64Instr_CLoad ( AMD64CondCode cond, UChar szB, 730bdea5508b371d394c81b91464fa8df767010d4dasewardj AMD64AMode* addr, HReg dst ); 7316f1ec58d9806064dea0000e4b543aacded9b11easewardjextern AMD64Instr* AMD64Instr_CStore ( AMD64CondCode cond, UChar szB, 7326f1ec58d9806064dea0000e4b543aacded9b11easewardj HReg src, AMD64AMode* addr ); 733ca257bc572147c1a9c7d9a2e81237125a35ff25dsewardjextern AMD64Instr* AMD64Instr_MovxLQ ( Bool syned, HReg src, HReg dst ); 73425a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, 73525a858136df4cbea0055c20aa7035d25fd40ee89sewardj AMD64AMode* src, HReg dst ); 73625a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); 73725a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Set64 ( AMD64CondCode cond, HReg dst ); 73825a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Bsfr64 ( Bool isFwds, HReg src, HReg dst ); 73925a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_MFence ( void ); 740e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardjextern AMD64Instr* AMD64Instr_ACAS ( AMD64AMode* addr, UChar sz ); 741e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardjextern AMD64Instr* AMD64Instr_DACAS ( AMD64AMode* addr, UChar sz ); 742e9d8a26b690c2561ac54ab0cd6ad83ecbadcbe76sewardj 74325a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_A87Free ( Int nregs ); 744d15b597a8a006b3fe136cbf6cdf5b46ed532a4d8sewardjextern AMD64Instr* AMD64Instr_A87PushPop ( AMD64AMode* addr, Bool isPush, UChar szB ); 74525a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_A87FpOp ( A87FpOp op ); 74625a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_A87LdCW ( AMD64AMode* addr ); 747f4c803b0947e7534809589cba8007851d78c7a2esewardjextern AMD64Instr* AMD64Instr_A87StSW ( AMD64AMode* addr ); 74825a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_LdMXCSR ( AMD64AMode* ); 74925a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ); 75025a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseSI2SF ( Int szS, Int szD, HReg src, HReg dst ); 75125a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseSF2SI ( Int szS, Int szD, HReg src, HReg dst ); 75225a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseSDSS ( Bool from64, HReg src, HReg dst ); 75325a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* ); 75425a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* ); 75525a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg ); 75625a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg ); 75725a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg ); 75825a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg ); 75925a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg ); 76025a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst ); 76125a858136df4cbea0055c20aa7035d25fd40ee89sewardjextern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ); 7623616a2ec4af166a3917810e4fdbe910ed80bd278sewardj//uu extern AMD64Instr* AMD64Instr_AvxLdSt ( Bool isLoad, HReg, AMD64AMode* ); 7633616a2ec4af166a3917810e4fdbe910ed80bd278sewardj//uu extern AMD64Instr* AMD64Instr_AvxReRg ( AMD64SseOp, HReg, HReg ); 764c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern AMD64Instr* AMD64Instr_EvCheck ( AMD64AMode* amCounter, 765c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj AMD64AMode* amFailAddr ); 766c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardjextern AMD64Instr* AMD64Instr_ProfInc ( void ); 767c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 768c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 769d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern void ppAMD64Instr ( const AMD64Instr*, Bool ); 770c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 771c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* Some functions that insulate the register allocator from details 772c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj of the underlying instruction set. */ 773d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern void getRegUsage_AMD64Instr ( HRegUsage*, const AMD64Instr*, Bool ); 774d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr*, Bool ); 775d8c64e082224b2e688abdef9219cc76fd82b373bflorianextern Bool isMove_AMD64Instr ( const AMD64Instr*, HReg*, HReg* ); 7768462d113e3efeacceb304222dada8d85f748295aflorianextern Int emit_AMD64Instr ( /*MB_MOD*/Bool* is_profInc, 7778462d113e3efeacceb304222dada8d85f748295aflorian UChar* buf, Int nbuf, 778d8c64e082224b2e688abdef9219cc76fd82b373bflorian const AMD64Instr* i, 7798462d113e3efeacceb304222dada8d85f748295aflorian Bool mode64, 7808462d113e3efeacceb304222dada8d85f748295aflorian VexEndness endness_host, 7818462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_chain_me_to_slowEP, 7828462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_chain_me_to_fastEP, 7838462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_xindir, 7848462d113e3efeacceb304222dada8d85f748295aflorian const void* disp_cp_xassisted ); 7852a1ed8e417440976e0c8059715ee0c87d3e2f5ccsewardj 7862a1ed8e417440976e0c8059715ee0c87d3e2f5ccsewardjextern void genSpill_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 7872a1ed8e417440976e0c8059715ee0c87d3e2f5ccsewardj HReg rreg, Int offset, Bool ); 7882a1ed8e417440976e0c8059715ee0c87d3e2f5ccsewardjextern void genReload_AMD64 ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 7892a1ed8e417440976e0c8059715ee0c87d3e2f5ccsewardj HReg rreg, Int offset, Bool ); 7902a1ed8e417440976e0c8059715ee0c87d3e2f5ccsewardj 791a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardjextern const RRegUniverse* getRRegUniverse_AMD64 ( void ); 792a5b502299bfc9d97f4c2c9f61cdc1a0a65e1da61sewardj 793cacba8e675988fbf21b08feea1f317a9c896c053florianextern HInstrArray* iselSB_AMD64 ( const IRSB*, 794c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj VexArch, 795d8c64e082224b2e688abdef9219cc76fd82b373bflorian const VexArchInfo*, 796d8c64e082224b2e688abdef9219cc76fd82b373bflorian const VexAbiInfo*, 797c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Int offs_Host_EvC_Counter, 798c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Int offs_Host_EvC_FailAddr, 799c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Bool chainingAllowed, 800c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj Bool addProfInc, 801dcd6d236c9aef7d4c84369d4c51f6b92ac910127florian Addr max_ga ); 802c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 803c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* How big is an event check? This is kind of a kludge because it 804c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj depends on the offsets of host_EvC_FAILADDR and host_EvC_COUNTER, 805c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj and so assumes that they are both <= 128, and so can use the short 806c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj offset encoding. This is all checked with assertions, so in the 807c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj worst case we will merely assert at startup. */ 8087ce2cc883c5b36586babec833838951ecf9f2a76florianextern Int evCheckSzB_AMD64 (void); 809c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 810c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* Perform a chaining and unchaining of an XDirect jump. */ 8119b76916dcc1628e133d57db001563429c6e3a590sewardjextern VexInvalRange chainXDirect_AMD64 ( VexEndness endness_host, 8129b76916dcc1628e133d57db001563429c6e3a590sewardj void* place_to_chain, 8137d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* disp_cp_chain_me_EXPECTED, 8147d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* place_to_jump_to ); 815c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 8169b76916dcc1628e133d57db001563429c6e3a590sewardjextern VexInvalRange unchainXDirect_AMD64 ( VexEndness endness_host, 8179b76916dcc1628e133d57db001563429c6e3a590sewardj void* place_to_unchain, 8187d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* place_to_jump_to_EXPECTED, 8197d6f81de12e6d8deb3e119ab318f361d97a10a65florian const void* disp_cp_chain_me ); 820c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 821c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj/* Patch the counter location into an existing ProfInc point. */ 8229b76916dcc1628e133d57db001563429c6e3a590sewardjextern VexInvalRange patchProfInc_AMD64 ( VexEndness endness_host, 8239b76916dcc1628e133d57db001563429c6e3a590sewardj void* place_to_patch, 8247d6f81de12e6d8deb3e119ab318f361d97a10a65florian const ULong* location_of_counter ); 825c6f970f1fadb640d69c78ac2669efab5c08f1e8dsewardj 826a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 827cef7d3e3df4796e35b4521158d9dc058f034aa87sewardj#endif /* ndef __VEX_HOST_AMD64_DEFS_H */ 828a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 829a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 830cef7d3e3df4796e35b4521158d9dc058f034aa87sewardj/*--- end host_amd64_defs.h ---*/ 831a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 832