host_amd64_defs.h revision 1830386e7b10430c0c3630123a82d8bcf0a071e7
1a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 2a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 3a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*--- ---*/ 4a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*--- This file (host-amd64/hdefs.h) is ---*/ 5a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*--- Copyright (c) 2005 OpenWorks LLP. All rights reserved. ---*/ 6a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*--- ---*/ 7a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 8a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 9a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/* 10a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj This file is part of LibVEX, a library for dynamic binary 11a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj instrumentation and translation. 12a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 13a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj Copyright (C) 2004-2005 OpenWorks, LLP. 14a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 15a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj This program is free software; you can redistribute it and/or modify 16a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj it under the terms of the GNU General Public License as published by 17a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj the Free Software Foundation; Version 2 dated June 1991 of the 18a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj license. 19a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 20a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj This program is distributed in the hope that it will be useful, 21a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj but WITHOUT ANY WARRANTY; without even the implied warranty of 22a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, or liability 23a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj for damages. See the GNU General Public License for more details. 24a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 25a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj Neither the names of the U.S. Department of Energy nor the 26a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj University of California nor the names of its contributors may be 27a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj used to endorse or promote products derived from this software 28a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj without prior written permission. 29a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 30a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj You should have received a copy of the GNU General Public License 31a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj along with this program; if not, write to the Free Software 32a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 33a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj USA. 34a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj*/ 35a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 36a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj#ifndef __LIBVEX_HOST_AMD64_HDEFS_H 37a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj#define __LIBVEX_HOST_AMD64_HDEFS_H 38a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 39c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 40c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Registers. --------- */ 41c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 42c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* The usual HReg abstraction. There are 16 real int regs, 6 real 43c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj float regs, and 16 real vector regs. 44c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj*/ 45c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 46c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppHRegAMD64 ( HReg ); 47c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 48c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RAX ( void ); 49c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RBX ( void ); 50c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RCX ( void ); 51c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RDX ( void ); 52c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RSP ( void ); 53c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RBP ( void ); 54c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RSI ( void ); 55c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_RDI ( void ); 56c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R8 ( void ); 57c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R9 ( void ); 58c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R10 ( void ); 59c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R11 ( void ); 60c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R12 ( void ); 61c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R13 ( void ); 62c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R14 ( void ); 63c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_R15 ( void ); 64c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 65c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_FAKE0 ( void ); 66c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_FAKE1 ( void ); 67c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_FAKE2 ( void ); 68c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_FAKE3 ( void ); 69c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_FAKE4 ( void ); 70c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_FAKE5 ( void ); 71c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 72c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM0 ( void ); 73c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM1 ( void ); 7453df0616a3a742eac96754b692e42c1d8610e10esewardjextern HReg hregAMD64_XMM2 ( void ); 75c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM3 ( void ); 76c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM4 ( void ); 77c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM5 ( void ); 78c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM6 ( void ); 79c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM7 ( void ); 80c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM8 ( void ); 81c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM9 ( void ); 82c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM10 ( void ); 83c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM11 ( void ); 84c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM12 ( void ); 85c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM13 ( void ); 86c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM14 ( void ); 87c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HReg hregAMD64_XMM15 ( void ); 88c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 89c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 90c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Condition codes, AMD encoding. --------- */ 91c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 92c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 93c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 94c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_O = 0, /* overflow */ 95c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NO = 1, /* no overflow */ 96c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 97c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_B = 2, /* below */ 98c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NB = 3, /* not below */ 99c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 100c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_Z = 4, /* zero */ 101c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NZ = 5, /* not zero */ 102c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 103c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_BE = 6, /* below or equal */ 104c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NBE = 7, /* not below or equal */ 105c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 106c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_S = 8, /* negative */ 107c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NS = 9, /* not negative */ 108c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 109c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_P = 10, /* parity even */ 110c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NP = 11, /* not parity even */ 111c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 112c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_L = 12, /* jump less */ 113c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NL = 13, /* not less */ 114c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 115c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_LE = 14, /* less or equal */ 116c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_NLE = 15, /* not less or equal */ 117c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 118c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Acc_ALWAYS = 16 /* the usual hack */ 119c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 120c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64CondCode; 121c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 122c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HChar* showAMD64CondCode ( AMD64CondCode ); 123c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 124c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 125c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Memory address expressions (amodes). --------- */ 126c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 127c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 128c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 129c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Aam_IR, /* Immediate + Reg */ 130c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Aam_IRRS /* Immediate + Reg1 + (Reg2 << Shift) */ 131c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 132c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AModeTag; 133c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 134c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 135c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 136c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AModeTag tag; 137c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 138c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 139c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm; 140c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 141c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } IR; 142c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 143c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm; 144c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg base; 145c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg index; 146c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Int shift; /* 0, 1, 2 or 3 only */ 147c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } IRRS; 148c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Aam; 149c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 150c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AMode; 151c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 152c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64AMode* AMD64AMode_IR ( UInt, HReg ); 153c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64AMode* AMD64AMode_IRRS ( UInt, HReg, HReg, Int ); 154c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 155c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64AMode* dopyAMD64AMode ( AMD64AMode* ); 156c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 157c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64AMode ( AMD64AMode* ); 158c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 159c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 160c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Operand, which can be reg, immediate or memory. --------- */ 161c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 162c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 163c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 164c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi_Imm, 165c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi_Reg, 166c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi_Mem 167c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 168c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMITag; 169c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 170c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 171c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 172c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMITag tag; 173c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 174c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 175c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm32; 176c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Imm; 177c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 178c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 179c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Reg; 180c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 181c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AMode* am; 182c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Mem; 183c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 184c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Armi; 185c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 186c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMI; 187c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 188c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RMI* AMD64RMI_Imm ( UInt ); 189c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RMI* AMD64RMI_Reg ( HReg ); 190c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RMI* AMD64RMI_Mem ( AMD64AMode* ); 191c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 192c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64RMI ( AMD64RMI* ); 193c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 194c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 195c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Operand, which can be reg or immediate only. --------- */ 196c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 197c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 198c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 199c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ari_Imm, 200c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ari_Reg 201c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 202c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RITag; 203c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 204c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 205c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 206c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RITag tag; 207c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 208c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 209c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj UInt imm32; 210c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Imm; 211c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 212c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 213c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Reg; 214c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 215c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ari; 216c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 217c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RI; 218c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 219c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RI* AMD64RI_Imm ( UInt ); 220c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RI* AMD64RI_Reg ( HReg ); 221c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 222c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64RI ( AMD64RI* ); 223c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 224c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 225c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- Operand, which can be reg or memory only. --------- */ 226c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 227c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 228c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 229c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Arm_Reg, 230c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Arm_Mem 231c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 232c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMTag; 233c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 234c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 235c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 236c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RMTag tag; 237c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj union { 238c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 239c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj HReg reg; 240c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Reg; 241c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 242c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64AMode* am; 243c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } Mem; 244c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 245c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Arm; 246c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 247c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64RM; 248c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 249c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RM* AMD64RM_Reg ( HReg ); 250c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64RM* AMD64RM_Mem ( AMD64AMode* ); 251c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 252c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64RM ( AMD64RM* ); 253c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 254c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 255d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj/* --------- Instructions. --------- */ 256d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj 257d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj/* --------- */ 258d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardjtypedef 259d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj enum { 260d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj Aun_NEG, 261d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj Aun_NOT 262d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj } 263d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj AMD64UnaryOp; 264d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj 265d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardjextern HChar* showAMD64UnaryOp ( AMD64UnaryOp ); 266614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 267614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 268614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj/* --------- */ 269614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardjtypedef 270614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj enum { 271614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_INVALID, 272614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_MOV, 273614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_CMP, 274614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_ADD, Aalu_SUB, Aalu_ADC, Aalu_SBB, 275614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_AND, Aalu_OR, Aalu_XOR, 276614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj Aalu_MUL 277614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } 278614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AluOp; 279614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 280614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardjextern HChar* showAMD64AluOp ( AMD64AluOp ); 281614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 282614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 2838258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj/* --------- */ 2848258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardjtypedef 2858258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj enum { 2868258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Ash_INVALID, 2878258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Ash_SHL, Ash_SHR, Ash_SAR 2888258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj } 2898258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64ShiftOp; 2908258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj 2918258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardjextern HChar* showAMD64ShiftOp ( AMD64ShiftOp ); 2928258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj 2938258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj 294a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* --------- */ 295a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. typedef 296a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. enum { 297a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xfp_INVALID, 298a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Binary */ 299a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xfp_ADD, Xfp_SUB, Xfp_MUL, Xfp_DIV, 300a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xfp_SCALE, Xfp_ATAN, Xfp_YL2X, Xfp_YL2XP1, Xfp_PREM, Xfp_PREM1, 301a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Unary */ 302a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xfp_SQRT, Xfp_ABS, Xfp_NEG, Xfp_MOV, Xfp_SIN, Xfp_COS, Xfp_TAN, 303a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xfp_ROUND, Xfp_2XM1 304a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } 305a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86FpOp; 306a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. 307a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. extern HChar* showX86FpOp ( X86FpOp ); 3081001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj 3091001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj 3101001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj/* --------- */ 3111001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjtypedef 3121001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj enum { 3131001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_INVALID, 3141001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* mov */ 3151001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_MOV, 3161001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* Floating point binary */ 3171001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_ADDF, Asse_SUBF, Asse_MULF, Asse_DIVF, 318a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MAXF, Xsse_MINF, 319a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_CMPEQF, Xsse_CMPLTF, Xsse_CMPLEF, Xsse_CMPUNF, 3201001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* Floating point unary */ 3211001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_RCPF, Asse_RSQRTF, Asse_SQRTF, 3221001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj /* Bitwise */ 3231001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Asse_AND, Asse_OR, Asse_XOR, Asse_ANDN, 324a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Integer binary */ 325a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_ADD8, Xsse_ADD16, Xsse_ADD32, Xsse_ADD64, 326a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_QADD8U, Xsse_QADD16U, 327a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_QADD8S, Xsse_QADD16S, 328a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_SUB8, Xsse_SUB16, Xsse_SUB32, Xsse_SUB64, 329a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_QSUB8U, Xsse_QSUB16U, 330a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_QSUB8S, Xsse_QSUB16S, 331a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MUL16, 332a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MULHI16U, 333a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MULHI16S, 334a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_AVG8U, Xsse_AVG16U, 335a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MAX16S, 336a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MAX8U, 337a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MIN16S, 338a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_MIN8U, 339a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_CMPEQ8, Xsse_CMPEQ16, Xsse_CMPEQ32, 340a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_CMPGT8S, Xsse_CMPGT16S, Xsse_CMPGT32S, 341a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_SHL16, Xsse_SHL32, Xsse_SHL64, 342a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_SHR16, Xsse_SHR32, Xsse_SHR64, 343a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_SAR16, Xsse_SAR32, 344a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_PACKSSD, Xsse_PACKSSW, Xsse_PACKUSW, 345a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_UNPCKHB, Xsse_UNPCKHW, Xsse_UNPCKHD, Xsse_UNPCKHQ, 346a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xsse_UNPCKLB, Xsse_UNPCKLW, Xsse_UNPCKLD, Xsse_UNPCKLQ 3471001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } 3481001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64SseOp; 3491001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj 3501001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjextern HChar* showAMD64SseOp ( AMD64SseOp ); 351c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 352c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 353c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* --------- */ 354c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 355c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj enum { 35653df0616a3a742eac96754b692e42c1d8610e10esewardj Ain_Imm64, /* Generate 64-bit literal to register */ 357c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ain_Alu64R, /* 64-bit mov/arith/logical, dst=REG */ 358c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj Ain_Alu64M, /* 64-bit mov/arith/logical, dst=MEM */ 3598258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Ain_Sh64, /* 64-bit shift/rotate, dst=REG or MEM */ 36005b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Ain_Test64, /* 64-bit test (AND, set flags, discard result) */ 361d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj Ain_Unary64, /* 64-bit not and neg */ 3629b96767debeeb1f78378f0e7e295fe6762c64002sewardj Ain_MulL, /* widening multiply */ 3637de0d3c800437fbd82c59d57d156f4823d67609fsewardj Ain_Div, /* div and mod */ 364a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Sh3232, /* shldl or shrdl */ 3651001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Ain_Push, /* push 64-bit value on stack */ 36605b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Ain_Call, /* call to address in register */ 367f67eadf04f5150178e589060f03381300d28e540sewardj Ain_Goto, /* conditional/unconditional jmp to dst */ 36805b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Ain_CMov64, /* conditional move */ 369f67eadf04f5150178e589060f03381300d28e540sewardj Ain_MovZLQ, /* reg-reg move, zeroing out top half */ 3708258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Ain_LoadEX, /* mov{s,z}{b,w,l}q from mem to reg */ 371f67eadf04f5150178e589060f03381300d28e540sewardj Ain_Store, /* store 32/16/8 bit value in memory */ 372a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Set32, /* convert condition code to 32-bit value */ 373a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Bsfr32, /* 32-bit bsf/bsr */ 374d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj Ain_MFence, /* mem fence */ 375a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. 376a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpUnary, /* FP fake unary op */ 377a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpBinary, /* FP fake binary op */ 378a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpLdSt, /* FP fake load/store */ 379a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpLdStI, /* FP fake load/store, converting to/from Int */ 380a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Fp64to32, /* FP round IEEE754 double to IEEE754 single */ 381a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpCMov, /* FP fake floating point conditional move */ 382a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpLdStCW, /* fldcw / fstcw */ 383a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_FpStSW_AX, /* fstsw %ax */ 3841830386e7b10430c0c3630123a82d8bcf0a071e7sewardj Ain_SseUComIS, /* ucomisd/ucomiss, then get %rflags into int 3851830386e7b10430c0c3630123a82d8bcf0a071e7sewardj register */ 386a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. 387a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_SseConst, /* Generate restricted SSE literal */ 3881830386e7b10430c0c3630123a82d8bcf0a071e7sewardj Ain_SseLdSt, /* SSE load/store 32/64/128 bits, no alignment 3891830386e7b10430c0c3630123a82d8bcf0a071e7sewardj constraints, upper 96/64/0 bits arbitrary */ 3901001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Ain_SseLdzLO, /* SSE load low 32/64 bits, zero remainder of reg */ 391a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Sse32Fx4, /* SSE binary, 32Fx4 */ 392a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Sse32FLo, /* SSE binary, 32F in lowest lane only */ 393a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_Sse64Fx2, /* SSE binary, 64Fx2 */ 3941001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Ain_Sse64FLo, /* SSE binary, 64F in lowest lane only */ 3951001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Ain_SseReRg, /* SSE binary general reg-reg, Re, Rg */ 396a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_SseCMov, /* SSE conditional move */ 397a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Xin_SseShuf /* SSE2 shuffle (pshufd) */ 398c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 399c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64InstrTag; 400c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 401c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* Destinations are on the RIGHT (second operand) */ 402c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 403c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjtypedef 404c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj struct { 405c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64InstrTag tag; 406614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj union { 407614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj struct { 40853df0616a3a742eac96754b692e42c1d8610e10esewardj ULong imm64; 40953df0616a3a742eac96754b692e42c1d8610e10esewardj HReg dst; 41053df0616a3a742eac96754b692e42c1d8610e10esewardj } Imm64; 41153df0616a3a742eac96754b692e42c1d8610e10esewardj struct { 412614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AluOp op; 413614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64RMI* src; 414614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj HReg dst; 415614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } Alu64R; 416614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj struct { 417614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AluOp op; 418614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64RI* src; 419614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj AMD64AMode* dst; 420614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } Alu64M; 4218258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj struct { 4228258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64ShiftOp op; 4238258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj UInt src; /* shift amount, or 0 means %cl */ 4248258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64RM* dst; 4258258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj } Sh64; 42605b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj struct { 42705b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64RI* src; 42805b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64RM* dst; 42905b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj } Test64; 430d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj /* Not and Neg */ 431d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj struct { 432d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj AMD64UnaryOp op; 433d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj AMD64RM* dst; 434d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj } Unary64; 4359b96767debeeb1f78378f0e7e295fe6762c64002sewardj /* DX:AX = AX *s/u r/m16, or EDX:EAX = EAX *s/u r/m32, 4369b96767debeeb1f78378f0e7e295fe6762c64002sewardj or RDX:RAX = RAX *s/u r/m64 */ 4379b96767debeeb1f78378f0e7e295fe6762c64002sewardj struct { 4389b96767debeeb1f78378f0e7e295fe6762c64002sewardj Bool syned; 4399b96767debeeb1f78378f0e7e295fe6762c64002sewardj Int sz; /* 2, 4 or 8 only */ 4409b96767debeeb1f78378f0e7e295fe6762c64002sewardj AMD64RM* src; 4419b96767debeeb1f78378f0e7e295fe6762c64002sewardj } MulL; 4427de0d3c800437fbd82c59d57d156f4823d67609fsewardj /* amd64 div/idiv instruction. Modifies RDX and RAX and 4437de0d3c800437fbd82c59d57d156f4823d67609fsewardj reads src. */ 4447de0d3c800437fbd82c59d57d156f4823d67609fsewardj struct { 4457de0d3c800437fbd82c59d57d156f4823d67609fsewardj Bool syned; 4467de0d3c800437fbd82c59d57d156f4823d67609fsewardj Int sz; /* 4 or 8 only */ 4477de0d3c800437fbd82c59d57d156f4823d67609fsewardj AMD64RM* src; 4487de0d3c800437fbd82c59d57d156f4823d67609fsewardj } Div; 449a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* shld/shrd. op may only be Xsh_SHL or Xsh_SHR */ 450a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 451a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86ShiftOp op; 452a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. UInt amt; /* shift amount, or 0 means %cl */ 453a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 454a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 455a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Sh3232; 4561001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 4571001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64RMI* src; 4581001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } Push; 45905b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj /* Pseudo-insn. Call target (an absolute address), on given 46005b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj condition (which could be Xcc_ALWAYS). */ 46105b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj struct { 46205b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64CondCode cond; 46305b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Addr64 target; 46405b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj Int regparms; /* 0 .. 6 */ 46505b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj } Call; 466f67eadf04f5150178e589060f03381300d28e540sewardj /* Pseudo-insn. Goto dst, on given condition (which could be 467f67eadf04f5150178e589060f03381300d28e540sewardj Acc_ALWAYS). */ 468f67eadf04f5150178e589060f03381300d28e540sewardj struct { 469f67eadf04f5150178e589060f03381300d28e540sewardj IRJumpKind jk; 470f67eadf04f5150178e589060f03381300d28e540sewardj AMD64CondCode cond; 471f67eadf04f5150178e589060f03381300d28e540sewardj AMD64RI* dst; 472f67eadf04f5150178e589060f03381300d28e540sewardj } Goto; 47305b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj /* Mov src to dst on the given condition, which may not 47405b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj be the bogus Acc_ALWAYS. */ 47505b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj struct { 47605b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64CondCode cond; 47705b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj AMD64RM* src; 47805b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj HReg dst; 47905b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardj } CMov64; 480f67eadf04f5150178e589060f03381300d28e540sewardj /* reg-reg move, zeroing out top half */ 481f67eadf04f5150178e589060f03381300d28e540sewardj struct { 482f67eadf04f5150178e589060f03381300d28e540sewardj HReg src; 483f67eadf04f5150178e589060f03381300d28e540sewardj HReg dst; 484f67eadf04f5150178e589060f03381300d28e540sewardj } MovZLQ; 4858258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj /* Sign/Zero extending loads. Dst size is always 64 bits. */ 4868258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj struct { 4871830386e7b10430c0c3630123a82d8bcf0a071e7sewardj UChar szSmall; /* only 1, 2 or 4 */ 4888258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj Bool syned; 4898258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64AMode* src; 4908258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj HReg dst; 4918258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj } LoadEX; 492f67eadf04f5150178e589060f03381300d28e540sewardj /* 32/16/8 bit stores. */ 493f67eadf04f5150178e589060f03381300d28e540sewardj struct { 494f67eadf04f5150178e589060f03381300d28e540sewardj UChar sz; /* only 1, 2 or 4 */ 495f67eadf04f5150178e589060f03381300d28e540sewardj HReg src; 496f67eadf04f5150178e589060f03381300d28e540sewardj AMD64AMode* dst; 497f67eadf04f5150178e589060f03381300d28e540sewardj } Store; 498a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Convert a x86 condition code to a 32-bit value (0 or 1). */ 499a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 500a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86CondCode cond; 501a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 502a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Set32; 503a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* 32-bit bsf or bsr. */ 504a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 505a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Bool isFwds; 506a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 507a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 508a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Bsfr32; 509d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj /* Mem fence. In short, an insn which flushes all preceding 510d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj loads and stores as much as possible before continuing. 511d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj On AMD64 we emit a real "mfence". */ 512d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj struct { 513d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj } MFence; 514d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardj 515a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* X86 Floating point (fake 3-operand, "flat reg file" insns) */ 516a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 517a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86FpOp op; 518a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 519a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 520a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } FpUnary; 521a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 522a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86FpOp op; 523a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg srcL; 524a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg srcR; 525a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 526a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } FpBinary; 527a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 528a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Bool isLoad; 529a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ 530a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg reg; 531a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86AMode* addr; 532a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } FpLdSt; 533a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Move 64-bit float to/from memory, converting to/from 534a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. signed int on the way. Note the conversions will observe 535a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. the host FPU rounding mode currently in force. */ 536a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 537a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Bool isLoad; 538a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. UChar sz; /* only 2, 4 or 8 */ 539a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg reg; 540a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86AMode* addr; 541a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } FpLdStI; 542a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* By observing the current FPU rounding mode, round (etc) 543a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. src into dst given that dst should be interpreted as an 544a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. IEEE754 32-bit (float) type. */ 545a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 546a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 547a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 548a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Fp64to32; 549a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Mov src to dst on the given condition, which may not 550a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. be the bogus Xcc_ALWAYS. */ 551a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 552a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86CondCode cond; 553a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 554a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 555a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } FpCMov; 556a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Load/store the FPU's 16-bit control word (fldcw/fstcw) */ 557a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 558a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Bool isLoad; 559a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86AMode* addr; 560a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } 561a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. FpLdStCW; 562a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* fstsw %ax */ 563a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 564a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* no fields */ 565a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } 566a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. FpStSW_AX; 5671830386e7b10430c0c3630123a82d8bcf0a071e7sewardj /* ucomisd/ucomiss, then get %rflags into int register */ 5681830386e7b10430c0c3630123a82d8bcf0a071e7sewardj struct { 5691830386e7b10430c0c3630123a82d8bcf0a071e7sewardj UChar sz; /* 4 or 8 only */ 5701830386e7b10430c0c3630123a82d8bcf0a071e7sewardj HReg srcL; /* xmm */ 5711830386e7b10430c0c3630123a82d8bcf0a071e7sewardj HReg srcR; /* xmm */ 5721830386e7b10430c0c3630123a82d8bcf0a071e7sewardj HReg dst; /* int */ 5731830386e7b10430c0c3630123a82d8bcf0a071e7sewardj } SseUComIS; 574a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. 575a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Simplistic SSE[123] */ 576a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 577a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. UShort con; 578a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 579a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } SseConst; 5801001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 5811001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Bool isLoad; 5821830386e7b10430c0c3630123a82d8bcf0a071e7sewardj UChar sz; /* 4, 8 or 16 only */ 5831001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg reg; 5841001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64AMode* addr; 5851001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } SseLdSt; 5861001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 5871001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj Int sz; /* 4 or 8 only */ 5881001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg reg; 5891001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64AMode* addr; 5901001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } SseLdzLO; 591a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 592a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86SseOp op; 593a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 594a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 595a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Sse32Fx4; 596a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 597a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86SseOp op; 598a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 599a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 600a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Sse32FLo; 601a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 602a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86SseOp op; 603a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 604a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 605a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } Sse64Fx2; 6061001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 6071001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64SseOp op; 6081001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg src; 6091001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg dst; 6101001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } Sse64FLo; 6111001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj struct { 6121001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj AMD64SseOp op; 6131001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg src; 6141001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj HReg dst; 6151001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardj } SseReRg; 616a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. /* Mov src to dst on the given condition, which may not 617a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. be the bogus Xcc_ALWAYS. */ 618a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 619a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. X86CondCode cond; 620a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 621a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 622a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } SseCMov; 623a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. struct { 624a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. Int order; /* 0 <= order <= 0xFF */ 625a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg src; 626a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. HReg dst; 627a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. } SseShuf; 628614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj 629614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj } Ain; 630c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj } 631c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj AMD64Instr; 632c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 63353df0616a3a742eac96754b692e42c1d8610e10esewardjextern AMD64Instr* AMD64Instr_Imm64 ( ULong imm64, HReg dst ); 634614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardjextern AMD64Instr* AMD64Instr_Alu64R ( AMD64AluOp, AMD64RMI*, HReg ); 635f67eadf04f5150178e589060f03381300d28e540sewardjextern AMD64Instr* AMD64Instr_Alu64M ( AMD64AluOp, AMD64RI*, AMD64AMode* ); 636d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardjextern AMD64Instr* AMD64Instr_Unary64 ( AMD64UnaryOp op, AMD64RM* dst ); 6378258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardjextern AMD64Instr* AMD64Instr_Sh64 ( AMD64ShiftOp, UInt, AMD64RM* ); 63805b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardjextern AMD64Instr* AMD64Instr_Test64 ( AMD64RI* src, AMD64RM* dst ); 6399b96767debeeb1f78378f0e7e295fe6762c64002sewardjextern AMD64Instr* AMD64Instr_MulL ( Bool syned, Int sz, AMD64RM* ); 6407de0d3c800437fbd82c59d57d156f4823d67609fsewardjextern AMD64Instr* AMD64Instr_Div ( Bool syned, Int sz, AMD64RM* ); 641614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Sh3232 ( AMD64ShiftOp, UInt amt, HReg src, HReg dst ); 6421001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjextern AMD64Instr* AMD64Instr_Push ( AMD64RMI* ); 64305b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardjextern AMD64Instr* AMD64Instr_Call ( AMD64CondCode, Addr64, Int ); 644f67eadf04f5150178e589060f03381300d28e540sewardjextern AMD64Instr* AMD64Instr_Goto ( IRJumpKind, AMD64CondCode cond, AMD64RI* dst ); 64505b3b6a0474ba57b4dbd15ac26d857197cdc87fcsewardjextern AMD64Instr* AMD64Instr_CMov64 ( AMD64CondCode, AMD64RM* src, HReg dst ); 646f67eadf04f5150178e589060f03381300d28e540sewardjextern AMD64Instr* AMD64Instr_MovZLQ ( HReg src, HReg dst ); 6478258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardjextern AMD64Instr* AMD64Instr_LoadEX ( UChar szSmall, Bool syned, 6488258a8c9f2e0ba23e79e322102fa6d0c354436f1sewardj AMD64AMode* src, HReg dst ); 649f67eadf04f5150178e589060f03381300d28e540sewardjextern AMD64Instr* AMD64Instr_Store ( UChar sz, HReg src, AMD64AMode* dst ); 650614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Set32 ( AMD64CondCode cond, HReg dst ); 651614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Bsfr32 ( Bool isFwds, HReg src, HReg dst ); 652d0a12df66280288ed336f61b4b9a0c769b2ecef8sewardjextern AMD64Instr* AMD64Instr_MFence ( void ); 653a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. 654614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpUnary ( AMD64FpOp op, HReg src, HReg dst ); 655614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpBinary ( AMD64FpOp op, HReg srcL, HReg srcR, HReg dst ); 656614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpLdSt ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* ); 657614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpLdStI ( Bool isLoad, UChar sz, HReg reg, AMD64AMode* ); 658614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Fp64to32 ( HReg src, HReg dst ); 659614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpCMov ( AMD64CondCode, HReg src, HReg dst ); 660614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpLdStCW ( Bool isLoad, AMD64AMode* ); 661614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_FpStSW_AX ( void ); 6621830386e7b10430c0c3630123a82d8bcf0a071e7sewardjextern AMD64Instr* AMD64Instr_SseUComIS ( Int sz, HReg srcL, HReg srcR, HReg dst ); 663a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj//.. 664614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_SseConst ( UShort con, HReg dst ); 6651830386e7b10430c0c3630123a82d8bcf0a071e7sewardjextern AMD64Instr* AMD64Instr_SseLdSt ( Bool isLoad, Int sz, HReg, AMD64AMode* ); 6661001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjextern AMD64Instr* AMD64Instr_SseLdzLO ( Int sz, HReg, AMD64AMode* ); 667614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Sse32Fx4 ( AMD64SseOp, HReg, HReg ); 668614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Sse32FLo ( AMD64SseOp, HReg, HReg ); 669614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_Sse64Fx2 ( AMD64SseOp, HReg, HReg ); 6701001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjextern AMD64Instr* AMD64Instr_Sse64FLo ( AMD64SseOp, HReg, HReg ); 6711001dc4dbf8f684e2afeaaea169e37a7ddeb5934sewardjextern AMD64Instr* AMD64Instr_SseReRg ( AMD64SseOp, HReg, HReg ); 672614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_SseCMov ( AMD64CondCode, HReg src, HReg dst ); 673614b3fb2b4b226c487bf7f4c85c719c31527bc89sewardj//.. extern AMD64Instr* AMD64Instr_SseShuf ( Int order, HReg src, HReg dst ); 674c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 675c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 676c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void ppAMD64Instr ( AMD64Instr* ); 677c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj 678c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj/* Some functions that insulate the register allocator from details 679c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardj of the underlying instruction set. */ 680c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void getRegUsage_AMD64Instr ( HRegUsage*, AMD64Instr* ); 681c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void mapRegs_AMD64Instr ( HRegRemap*, AMD64Instr* ); 682c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern Bool isMove_AMD64Instr ( AMD64Instr*, HReg*, HReg* ); 683c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr* ); 684c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset ); 685c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset ); 686c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern void getAllocableRegs_AMD64 ( Int*, HReg** ); 687c33671d7b0e21edb1d1015e4cbccbc6ca139e6d8sewardjextern HInstrArray* iselBB_AMD64 ( IRBB*, VexSubArch ); 688a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 689a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj#endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */ 690a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj 691a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 692a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*--- end host-amd64/hdefs.h ---*/ 693a3e9830f0ab418d41a9c8484216b563d438cf2dcsewardj/*---------------------------------------------------------------*/ 694