10c3074e4f8001732373fcffc7e310bce2738907fcarll#include <stdio.h> 20c3074e4f8001732373fcffc7e310bce2738907fcarll#include <config.h> 30c3074e4f8001732373fcffc7e310bce2738907fcarll 40c3074e4f8001732373fcffc7e310bce2738907fcarlldouble foo = -1.0; 50c3074e4f8001732373fcffc7e310bce2738907fcarlldouble FRT1; 60c3074e4f8001732373fcffc7e310bce2738907fcarlldouble FRT2; 70c3074e4f8001732373fcffc7e310bce2738907fcarll 80c3074e4f8001732373fcffc7e310bce2738907fcarll#ifdef HAS_ISA_2_07 90c3074e4f8001732373fcffc7e310bce2738907fcarll 100c3074e4f8001732373fcffc7e310bce2738907fcarll/* b0 may be non-zero in lwarx/ldarx Power6 instrs */ 110c3074e4f8001732373fcffc7e310bce2738907fcarllvoid test_reservation() 120c3074e4f8001732373fcffc7e310bce2738907fcarll{ 130c3074e4f8001732373fcffc7e310bce2738907fcarll 140c3074e4f8001732373fcffc7e310bce2738907fcarll unsigned RT; 150c3074e4f8001732373fcffc7e310bce2738907fcarll unsigned base; 160c3074e4f8001732373fcffc7e310bce2738907fcarll unsigned offset; 170c3074e4f8001732373fcffc7e310bce2738907fcarll unsigned arrB[] = { 0x00112233U, 0x44556677U, 0x8899aabbU, 0xccddeeffU }; 180c3074e4f8001732373fcffc7e310bce2738907fcarll int arrH[] __attribute__ ((aligned (2))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad }; 190c3074e4f8001732373fcffc7e310bce2738907fcarll 200c3074e4f8001732373fcffc7e310bce2738907fcarll /* The lbarx and lharx instructions were "phased in" in ISA 2.06. That 210c3074e4f8001732373fcffc7e310bce2738907fcarll * means it they may show up in some implementations but not others. They 220c3074e4f8001732373fcffc7e310bce2738907fcarll * are in all ISA 2.08 implementations. 230c3074e4f8001732373fcffc7e310bce2738907fcarll */ 240c3074e4f8001732373fcffc7e310bce2738907fcarll base = (unsigned) &arrB; 250c3074e4f8001732373fcffc7e310bce2738907fcarll offset = ((unsigned ) &arrB[1]) - base; 260c3074e4f8001732373fcffc7e310bce2738907fcarll __asm__ volatile ("ori 20, %0, 0"::"r" (base)); 270c3074e4f8001732373fcffc7e310bce2738907fcarll __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); 280c3074e4f8001732373fcffc7e310bce2738907fcarll __asm__ volatile ("lbarx %0, 20, 21, 1":"=r" (RT)); 290c3074e4f8001732373fcffc7e310bce2738907fcarll printf("lbarx => 0x%x\n", RT); 300c3074e4f8001732373fcffc7e310bce2738907fcarll 310c3074e4f8001732373fcffc7e310bce2738907fcarll base = (unsigned) &arrH; 320c3074e4f8001732373fcffc7e310bce2738907fcarll offset = ((unsigned) &arrH[1]) - base; 330c3074e4f8001732373fcffc7e310bce2738907fcarll __asm__ volatile ("ori 20, %0, 0"::"r" (base)); 340c3074e4f8001732373fcffc7e310bce2738907fcarll __asm__ volatile ("ori 21, %0, 0"::"r" (offset)); 350c3074e4f8001732373fcffc7e310bce2738907fcarll __asm__ volatile ("lharx %0, 20, 21, 1":"=r" (RT)); 360c3074e4f8001732373fcffc7e310bce2738907fcarll printf("lharx => 0x%x\n", RT); 370c3074e4f8001732373fcffc7e310bce2738907fcarll 380c3074e4f8001732373fcffc7e310bce2738907fcarll} 390c3074e4f8001732373fcffc7e310bce2738907fcarll#endif 400c3074e4f8001732373fcffc7e310bce2738907fcarll 410c3074e4f8001732373fcffc7e310bce2738907fcarllint main(void) 420c3074e4f8001732373fcffc7e310bce2738907fcarll{ 430c3074e4f8001732373fcffc7e310bce2738907fcarll#ifdef HAS_ISA_2_07 440c3074e4f8001732373fcffc7e310bce2738907fcarll (void) test_reservation(); 450c3074e4f8001732373fcffc7e310bce2738907fcarll#endif 460c3074e4f8001732373fcffc7e310bce2738907fcarll 470c3074e4f8001732373fcffc7e310bce2738907fcarll return 0; 480c3074e4f8001732373fcffc7e310bce2738907fcarll} 49