Cross Reference: /art/compiler/optimizing/code_generator

Lines Matching refs:dst
807 void CodeGeneratorMIPS::MoveLocation(Location dst, Location src, Primitive::Type dst_type) {
808   if (src.Equals(dst)) {
813     MoveConstant(dst, src.GetConstant());
816       Move64(dst, src);
818       Move32(dst, src);
883       FRegister dst = destination.AsFpuRegister<FRegister>();
886       __ Mtc1(src_low, dst);
887       __ MoveToFpuHigh(src_high, dst);
916       Register dst = destination.AsRegister<Register>();
917       __ LoadConst32(dst, value);
962   Register dst = destination.AsRegister<Register>();
963   __ LoadConst32(dst, value);
1190       Register dst = locations->Out().AsRegister<Register>();
1205           __ Andi(dst, lhs, rhs_imm);
1207           __ And(dst, lhs, rhs_reg);
1210           __ Ori(dst, lhs, rhs_imm);
1212           __ Or(dst, lhs, rhs_reg);
1215           __ Xori(dst, lhs, rhs_imm);
1217           __ Xor(dst, lhs, rhs_reg);
1220           __ Addiu(dst, lhs, rhs_imm);
1222           __ Addu(dst, lhs, rhs_reg);
1226           __ Addiu(dst, lhs, -rhs_imm);
1228           __ Subu(dst, lhs, rhs_reg);
1376       FRegister dst = locations->Out().AsFpuRegister<FRegister>();
1381           __ AddS(dst, lhs, rhs);
1383           __ AddD(dst, lhs, rhs);
1388           __ SubS(dst, lhs, rhs);
1390           __ SubD(dst, lhs, rhs);
1441       Register dst = locations->Out().AsRegister<Register>();
1445           if (dst != lhs) {
1446             __ Move(dst, lhs);
1449           __ Sll(dst, lhs, shift_value);
1451           __ Sra(dst, lhs, shift_value);
1453           __ Srl(dst, lhs, shift_value);
1456             __ Rotr(dst, lhs, shift_value);
1459             __ Srl(dst, lhs, shift_value);
1460             __ Or(dst, dst, TMP);
1465           __ Sllv(dst, lhs, rhs_reg);
1467           __ Srav(dst, lhs, rhs_reg);
1469           __ Srlv(dst, lhs, rhs_reg);
1472             __ Rotrv(dst, lhs, rhs_reg);
1481             __ Srlv(dst, lhs, rhs_reg);
1482             __ Or(dst, dst, TMP);
2224   Register dst = locations->Out().AsRegister<Register>();
2253   __ LoadConst32(dst, 0);
2258   __ LoadConst32(dst, 1);
2482       FRegister dst = locations->Out().AsFpuRegister<FRegister>();
2486         __ DivS(dst, lhs, rhs);
2488         __ DivD(dst, lhs, rhs);
2620   Register dst = locations->Out().AsRegister<Register>();
2636         __ Xori(dst, lhs, rhs_imm);
2642         __ Xor(dst, lhs, rhs_reg);
2645         __ Sltiu(dst, dst, 1);
2647         __ Sltu(dst, ZERO, dst);
2654         __ Slti(dst, lhs, rhs_imm);
2660         __ Slt(dst, lhs, rhs_reg);
2665         __ Xori(dst, dst, 1);
2673         __ Slti(dst, lhs, rhs_imm + 1);
2677           __ Xori(dst, dst, 1);
2684         __ Slt(dst, rhs_reg, lhs);
2688           __ Xori(dst, dst, 1);
2700         __ Sltiu(dst, lhs, rhs_imm);
2706         __ Sltu(dst, lhs, rhs_reg);
2711         __ Xori(dst, dst, 1);
2725         __ Sltiu(dst, lhs, rhs_imm + 1);
2729           __ Xori(dst, dst, 1);
2736         __ Sltu(dst, rhs_reg, lhs);
2740           __ Xori(dst, dst, 1);
3475       Register dst;
3478         dst = locations->Out().AsRegisterPairLow<Register>();
3480         if (obj == dst) {
3483           __ LoadFromOffset(kLoadWord, dst, obj, offset);
3485           __ LoadFromOffset(kLoadWord, dst, obj, offset);
3491         dst = locations->Out().AsRegister<Register>();
3492         __ LoadFromOffset(load_type, dst, obj, offset);
3496       FRegister dst = locations->Out().AsFpuRegister<FRegister>();
3498         __ LoadSFromOffset(dst, obj, offset);
3500         __ LoadDFromOffset(dst, obj, offset);
4131       Register dst = locations->Out().AsRegister<Register>();
4136         __ MulR6(dst, lhs, rhs);
4138         __ MulR2(dst, lhs, rhs);
4152       // (e.g. lhs=a0_a1, rhs=a2_a3 and dst=a1_a2).
4181       FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4185         __ MulS(dst, lhs, rhs);
4187         __ MulD(dst, lhs, rhs);
4223       Register dst = locations->Out().AsRegister<Register>();
4225       __ Subu(dst, ZERO, src);
4241       FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4244         __ NegS(dst, src);
4246         __ NegD(dst, src);
4327       Register dst = locations->Out().AsRegister<Register>();
4329       __ Nor(dst, src, ZERO);
4769     Register dst = locations->Out().AsRegister<Register>();
4776         __ Andi(dst, src, 0xFFFF);
4780           __ Seb(dst, src);
4782           __ Sll(dst, src, 24);
4783           __ Sra(dst, dst, 24);
4788           __ Seh(dst, src);
4790           __ Sll(dst, src, 16);
4791           __ Sra(dst, dst, 16);
4795         __ Move(dst, src);
4809         FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4813           __ Cvtsl(dst, FTMP);
4815           __ Cvtdl(dst, FTMP);
4835       FRegister dst = locations->Out().AsFpuRegister<FRegister>();
4838         __ Cvtsw(dst, FTMP);
4840         __ Cvtdw(dst, FTMP);
4932       Register dst = locations->Out().AsRegister<Register>();
4972         __ LoadConst32(dst, std::numeric_limits<int32_t>::min());
4974         __ And(dst, dst, TMP);
4988         __ LoadConst32(dst, std::numeric_limits<int32_t>::min());
4989         __ Movf(dst, ZERO, 0);
5001       __ Mfc1(dst, FTMP);
5007     FRegister dst = locations->Out().AsFpuRegister<FRegister>();
5010       __ Cvtsd(dst, src);
5012       __ Cvtds(dst, src);