Cross Reference: /art/compiler/optimizing/code_generator

Lines Matching refs:dst
1066       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1081           __ Andi(dst, lhs, rhs_imm);
1083           __ And(dst, lhs, rhs_reg);
1086           __ Ori(dst, lhs, rhs_imm);
1088           __ Or(dst, lhs, rhs_reg);
1091           __ Xori(dst, lhs, rhs_imm);
1093           __ Xor(dst, lhs, rhs_reg);
1097             __ Addiu(dst, lhs, rhs_imm);
1099             __ Addu(dst, lhs, rhs_reg);
1102             __ Daddiu(dst, lhs, rhs_imm);
1104             __ Daddu(dst, lhs, rhs_reg);
1110             __ Addiu(dst, lhs, -rhs_imm);
1112             __ Subu(dst, lhs, rhs_reg);
1115             __ Daddiu(dst, lhs, -rhs_imm);
1117             __ Dsubu(dst, lhs, rhs_reg);
1124       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
1129           __ AddS(dst, lhs, rhs);
1131           __ AddD(dst, lhs, rhs);
1134           __ SubS(dst, lhs, rhs);
1136           __ SubD(dst, lhs, rhs);
1173       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1191           if (dst != lhs) {
1192             __ Move(dst, lhs);
1196             __ Sll(dst, lhs, shift_value);
1198             __ Sra(dst, lhs, shift_value);
1200             __ Srl(dst, lhs, shift_value);
1202             __ Rotr(dst, lhs, shift_value);
1207               __ Dsll(dst, lhs, shift_value);
1209               __ Dsra(dst, lhs, shift_value);
1211               __ Dsrl(dst, lhs, shift_value);
1213               __ Drotr(dst, lhs, shift_value);
1218               __ Dsll32(dst, lhs, shift_value);
1220               __ Dsra32(dst, lhs, shift_value);
1222               __ Dsrl32(dst, lhs, shift_value);
1224               __ Drotr32(dst, lhs, shift_value);
1231             __ Sllv(dst, lhs, rhs_reg);
1233             __ Srav(dst, lhs, rhs_reg);
1235             __ Srlv(dst, lhs, rhs_reg);
1237             __ Rotrv(dst, lhs, rhs_reg);
1241             __ Dsllv(dst, lhs, rhs_reg);
1243             __ Dsrav(dst, lhs, rhs_reg);
1245             __ Dsrlv(dst, lhs, rhs_reg);
1247             __ Drotrv(dst, lhs, rhs_reg);
1810   GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
1837   __ LoadConst32(dst, 0);
1842   __ LoadConst32(dst, 1);
2125       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
2129         __ DivS(dst, lhs, rhs);
2131         __ DivD(dst, lhs, rhs);
2244   GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2265         __ Xori(dst, lhs, rhs_imm);
2271         __ Xor(dst, lhs, rhs_reg);
2274         __ Sltiu(dst, dst, 1);
2276         __ Sltu(dst, ZERO, dst);
2283         __ Slti(dst, lhs, rhs_imm);
2289         __ Slt(dst, lhs, rhs_reg);
2294         __ Xori(dst, dst, 1);
2302         __ Slti(dst, lhs, rhs_imm_plus_one);
2306           __ Xori(dst, dst, 1);
2313         __ Slt(dst, rhs_reg, lhs);
2317           __ Xori(dst, dst, 1);
2329         __ Sltiu(dst, lhs, rhs_imm);
2335         __ Sltu(dst, lhs, rhs_reg);
2340         __ Xori(dst, dst, 1);
2354         __ Sltiu(dst, lhs, rhs_imm_plus_one);
2358           __ Xori(dst, dst, 1);
2365         __ Sltu(dst, rhs_reg, lhs);
2369           __ Xori(dst, dst, 1);
2760     GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
2761     __ LoadFromOffset(load_type, dst, obj, field_info.GetFieldOffset().Uint32Value());
2764     FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
2765     __ LoadFpuFromOffset(load_type, dst, obj, field_info.GetFieldOffset().Uint32Value());
3349       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
3353         __ MulR6(dst, lhs, rhs);
3355         __ Dmul(dst, lhs, rhs);
3360       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
3364         __ MulS(dst, lhs, rhs);
3366         __ MulD(dst, lhs, rhs);
3402       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
3405         __ Subu(dst, ZERO, src);
3407         __ Dsubu(dst, ZERO, src);
3412       FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
3415         __ NegS(dst, src);
3417         __ NegD(dst, src);
3492       GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
3494       __ Nor(dst, src, ZERO);
3867     GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
3872         __ Andi(dst, src, 0xFFFF);
3879           __ Sll(dst, src, 0);
3880           __ Seb(dst, dst);
3882           __ Seb(dst, src);
3890           __ Sll(dst, src, 0);
3891           __ Seh(dst, dst);
3893           __ Seh(dst, src);
3900         __ Sll(dst, src, 0);
3908     FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
3913         __ Cvtsl(dst, FTMP);
3915         __ Cvtdl(dst, FTMP);
3920         __ Cvtsw(dst, FTMP);
3922         __ Cvtdw(dst, FTMP);
3927     GpuRegister dst = locations->Out().AsRegister<GpuRegister>();
3981       __ LoadConst64(dst, std::numeric_limits<int64_t>::min());
3983       __ LoadConst32(dst, std::numeric_limits<int32_t>::min());
3986     __ And(dst, dst, TMP);
3998       __ Dmfc1(dst, FTMP);
4005       __ Mfc1(dst, FTMP);
4011     FpuRegister dst = locations->Out().AsFpuRegister<FpuRegister>();
4014       __ Cvtsd(dst, src);
4016       __ Cvtds(dst, src);