Lines Matching defs:arm
24 #include "utils/arm/assembler_arm_test.h"
43 class AssemblerArm32Test : public AssemblerArmTest<arm::Arm32Assembler,
44 arm::Register, arm::SRegister,
45 uint32_t, arm::ShifterOperand, arm::Condition,
46 arm::SetCc> {
49 return "arm";
70 new arm::Register(arm::R0),
71 new arm::Register(arm::R1),
72 new arm::Register(arm::R4),
73 new arm::Register(arm::R8),
74 new arm::Register(arm::R11),
75 new arm::Register(arm::R12),
76 new arm::Register(arm::R13),
77 new arm::Register(arm::R14),
78 new arm::Register(arm::R15)
83 new arm::Register(arm::R0),
84 new arm::Register(arm::R1),
85 new arm::Register(arm::R2),
86 new arm::Register(arm::R3),
87 new arm::Register(arm::R4),
88 new arm::Register(arm::R5),
89 new arm::Register(arm::R6),
90 new arm::Register(arm::R7),
91 new arm::Register(arm::R8),
92 new arm::Register(arm::R9),
93 new arm::Register(arm::R10),
94 new arm::Register(arm::R11),
95 new arm::Register(arm::R12),
96 new arm::Register(arm::R13),
97 new arm::Register(arm::R14),
98 new arm::Register(arm::R15)
104 conditions_.push_back(arm::Condition::EQ);
105 conditions_.push_back(arm::Condition::NE);
106 conditions_.push_back(arm::Condition::CS);
107 conditions_.push_back(arm::Condition::CC);
108 conditions_.push_back(arm::Condition::MI);
109 conditions_.push_back(arm::Condition::PL);
110 conditions_.push_back(arm::Condition::VS);
111 conditions_.push_back(arm::Condition::VC);
112 conditions_.push_back(arm::Condition::HI);
113 conditions_.push_back(arm::Condition::LS);
114 conditions_.push_back(arm::Condition::GE);
115 conditions_.push_back(arm::Condition::LT);
116 conditions_.push_back(arm::Condition::GT);
117 conditions_.push_back(arm::Condition::LE);
118 conditions_.push_back(arm::Condition::AL);
120 conditions_.push_back(arm::Condition::EQ);
121 conditions_.push_back(arm::Condition::NE);
122 conditions_.push_back(arm::Condition::CC);
123 conditions_.push_back(arm::Condition::VC);
124 conditions_.push_back(arm::Condition::HI);
125 conditions_.push_back(arm::Condition::LT);
126 conditions_.push_back(arm::Condition::AL);
129 set_ccs_.push_back(arm::kCcDontCare);
130 set_ccs_.push_back(arm::kCcSet);
131 set_ccs_.push_back(arm::kCcKeep);
133 shifter_operands_.push_back(arm::ShifterOperand(0));
134 shifter_operands_.push_back(arm::ShifterOperand(1));
135 shifter_operands_.push_back(arm::ShifterOperand(2));
136 shifter_operands_.push_back(arm::ShifterOperand(3));
137 shifter_operands_.push_back(arm::ShifterOperand(4));
138 shifter_operands_.push_back(arm::ShifterOperand(5));
139 shifter_operands_.push_back(arm::ShifterOperand(127));
140 shifter_operands_.push_back(arm::ShifterOperand(128));
141 shifter_operands_.push_back(arm::ShifterOperand(254));
142 shifter_operands_.push_back(arm::ShifterOperand(255));
145 shifter_operands_.push_back(arm::ShifterOperand(arm::R0));
146 shifter_operands_.push_back(arm::ShifterOperand(arm::R1));
147 shifter_operands_.push_back(arm::ShifterOperand(arm::R2));
148 shifter_operands_.push_back(arm::ShifterOperand(arm::R3));
149 shifter_operands_.push_back(arm::ShifterOperand(arm::R4));
150 shifter_operands_.push_back(arm::ShifterOperand(arm::R5));
151 shifter_operands_.push_back(arm::ShifterOperand(arm::R6));
152 shifter_operands_.push_back(arm::ShifterOperand(arm::R7));
153 shifter_operands_.push_back(arm::ShifterOperand(arm::R8));
154 shifter_operands_.push_back(arm::ShifterOperand(arm::R9));
155 shifter_operands_.push_back(arm::ShifterOperand(arm::R10));
156 shifter_operands_.push_back(arm::ShifterOperand(arm::R11));
157 shifter_operands_.push_back(arm::ShifterOperand(arm::R12));
158 shifter_operands_.push_back(arm::ShifterOperand(arm::R13));
160 shifter_operands_.push_back(arm::ShifterOperand(arm::R0));
161 shifter_operands_.push_back(arm::ShifterOperand(arm::R1));
162 shifter_operands_.push_back(arm::ShifterOperand(arm::R4));
163 shifter_operands_.push_back(arm::ShifterOperand(arm::R8));
164 shifter_operands_.push_back(arm::ShifterOperand(arm::R11));
165 shifter_operands_.push_back(arm::ShifterOperand(arm::R12));
166 shifter_operands_.push_back(arm::ShifterOperand(arm::R13));
169 std::vector<arm::Shift> shifts {
170 arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR, arm::Shift::ROR, arm::Shift::RRX
174 for (arm::Shift shift : shifts) {
175 for (arm::Register* reg : registers_) { // Note: this will pick up the sparse set.
176 if (*reg == arm::R15) { // Skip PC.
179 if (shift != arm::Shift::RRX) {
182 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, imm));
185 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 1));
186 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 2));
187 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 3));
188 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 7));
189 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 15));
190 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 16));
191 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 30));
192 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 31));
196 shifter_operands_.push_back(arm::ShifterOperand(*reg, shift, 0));
202 std::vector<arm::ShifterOperand> CreateRegisterShifts(std::vector<arm::Register*>& base_regs,
204 std::vector<arm::ShifterOperand> res;
205 static constexpr arm::Shift kShifts[] = { arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR,
206 arm::Shift::ROR };
208 for (arm::Shift shift : kShifts) {
209 for (arm::Register* reg : base_regs) {
211 res.push_back(arm::ShifterOperand(*reg, shift, shift_min));
213 res.push_back(arm::ShifterOperand(*reg, shift, shift_max));
215 res.push_back(arm::ShifterOperand(*reg, shift, middle));
216 res.push_back(arm::ShifterOperand(*reg, shift, middle - 1));
217 res.push_back(arm::ShifterOperand(*reg, shift, middle + 1));
230 std::vector<arm::Register*> GetRegisters() OVERRIDE {
238 std::vector<arm::Condition>& GetConditions() OVERRIDE {
242 std::string GetConditionString(arm::Condition c) OVERRIDE {
248 std::vector<arm::SetCc>& GetSetCcs() OVERRIDE {
252 std::string GetSetCcString(arm::SetCc s) OVERRIDE {
254 return s == arm::kCcSet ? "s" : "";
257 arm::Register GetPCRegister() OVERRIDE {
258 return arm::R15;
261 std::vector<arm::ShifterOperand>& GetShiftOperands() OVERRIDE {
265 std::string GetShiftString(arm::ShifterOperand sop) OVERRIDE {
269 if (sop.GetShift() == arm::Shift::RRX) {
326 void TemplateHelper(std::function<void(arm::Register)> f, int depth ATTRIBUTE_UNUSED,
329 std::vector<arm::Register*> registers = without_pc ? GetRegistersWithoutPC() : GetRegisters();
353 void TemplateHelper(std::function<void(const arm::ShifterOperand&)> f, int depth ATTRIBUTE_UNUSED,
356 for (const arm::ShifterOperand& shift : GetShiftOperands()) {
377 void TemplateHelper(std::function<void(arm::Condition)> f, int depth ATTRIBUTE_UNUSED,
380 for (arm::Condition c : GetConditions()) {
401 void TemplateHelper(std::function<void(arm::SetCc)> f, int depth ATTRIBUTE_UNUSED,
404 for (arm::SetCc s : GetSetCcs()) {
426 void TemplateHelper(std::function<void(arm::Register, Args...)> f, int depth, bool without_pc,
428 std::vector<arm::Register*> registers = without_pc ? GetRegistersWithoutPC() : GetRegisters();
455 void TemplateHelper(std::function<void(const arm::ShifterOperand&, Args...)> f, int depth,
458 for (const arm::ShifterOperand& shift : GetShiftOperands()) {
482 void TemplateHelper(std::function<void(arm::Condition, Args...)> f, int depth, bool without_pc,
484 for (arm::Condition c : GetConditions()) {
508 void TemplateHelper(std::function<void(arm::SetCc, Args...)> f, int depth, bool without_pc,
510 for (arm::SetCc s : GetSetCcs()) {
598 if (std::is_same<T, arm::Register>::value) {
604 } else if (std::is_same<T, const arm::ShifterOperand&>::value) {
606 } else if (std::is_same<T, arm::Condition>::value) {
617 if (std::is_same<T1, arm::Register>::value) {
622 } else if (std::is_same<T1, const arm::ShifterOperand&>::value) {
624 } else if (std::is_same<T1, arm::Condition>::value) {
636 static constexpr const char* kArm32AssemblyHeader = ".arm\n";
638 std::vector<arm::Register*> registers_;
639 std::vector<arm::Condition> conditions_;
640 std::vector<arm::SetCc> set_ccs_;
641 std::vector<arm::ShifterOperand> shifter_operands_;
669 DriverStr(RepeatRRiiC(&arm::Arm32Assembler::sbfx, immediates,
693 DriverStr(RepeatRRiiC(&arm::Arm32Assembler::ubfx, immediates,
698 T4Helper(&arm::Arm32Assembler::mul, true, "mul{cond} {reg1}, {reg2}, {reg3}", "mul");
702 T5Helper(&arm::Arm32Assembler::mla, true, "mla{cond} {reg1}, {reg2}, {reg3}, {reg4}", "mla");
706 T5Helper(&arm::Arm32Assembler::umull, true, "umull{cond} {reg1}, {reg2}, {reg3}, {reg4}",
711 T5Helper(&arm::Arm32Assembler::smull, true, "smull{cond} {reg1}, {reg2}, {reg3}, {reg4}",
716 T4Helper(&arm::Arm32Assembler::sdiv, true, "sdiv{cond} {reg1}, {reg2}, {reg3}", "sdiv");
720 T4Helper(&arm::Arm32Assembler::udiv, true, "udiv{cond} {reg1}, {reg2}, {reg3}", "udiv");
724 T5Helper(&arm::Arm32Assembler::and_, true, "and{cond}{s} {reg1}, {reg2}, {shift}", "and");
728 T4Helper(&arm::Arm32Assembler::ands, true, "and{cond}s {reg1}, {reg2}, {shift}", "ands");
732 T5Helper(&arm::Arm32Assembler::eor, true, "eor{cond}{s} {reg1}, {reg2}, {shift}", "eor");
736 T4Helper(&arm::Arm32Assembler::eors, true, "eor{cond}s {reg1}, {reg2}, {shift}", "eors");
740 T5Helper(&arm::Arm32Assembler::orr, true, "orr{cond}{s} {reg1}, {reg2}, {shift}", "orr");
744 T4Helper(&arm::Arm32Assembler::orrs, true, "orr{cond}s {reg1}, {reg2}, {shift}", "orrs");
748 T5Helper(&arm::Arm32Assembler::bic, true, "bic{cond}{s} {reg1}, {reg2}, {shift}", "bic");
752 T4Helper(&arm::Arm32Assembler::bics, true, "bic{cond}s {reg1}, {reg2}, {shift}", "bics");
756 T4Helper(&arm::Arm32Assembler::mov, true, "mov{cond}{s} {reg1}, {shift}", "mov");
760 T3Helper(&arm::Arm32Assembler::movs, true, "mov{cond}s {reg1}, {shift}", "movs");
764 T4Helper(&arm::Arm32Assembler::mvn, true, "mvn{cond}{s} {reg1}, {shift}", "mvn");
768 T3Helper(&arm::Arm32Assembler::mvns, true, "mvn{cond}s {reg1}, {shift}", "mvns");
772 T5Helper(&arm::Arm32Assembler::add, false, "add{cond}{s} {reg1}, {reg2}, {shift}", "add");
776 T4Helper(&arm::Arm32Assembler::adds, false, "add{cond}s {reg1}, {reg2}, {shift}", "adds");
780 T5Helper(&arm::Arm32Assembler::adc, false, "adc{cond}{s} {reg1}, {reg2}, {shift}", "adc");
784 T4Helper(&arm::Arm32Assembler::adcs, false, "adc{cond}s {reg1}, {reg2}, {shift}", "adcs");
788 T5Helper(&arm::Arm32Assembler::sub, false, "sub{cond}{s} {reg1}, {reg2}, {shift}", "sub");
792 T4Helper(&arm::Arm32Assembler::subs, false, "sub{cond}s {reg1}, {reg2}, {shift}", "subs");
796 T5Helper(&arm::Arm32Assembler::sbc, false, "sbc{cond}{s} {reg1}, {reg2}, {shift}", "sbc");
800 T4Helper(&arm::Arm32Assembler::sbcs, false, "sbc{cond}s {reg1}, {reg2}, {shift}", "sbcs");
804 T5Helper(&arm::Arm32Assembler::rsb, true, "rsb{cond}{s} {reg1}, {reg2}, {shift}", "rsb");
808 T4Helper(&arm::Arm32Assembler::rsbs, true, "rsb{cond}s {reg1}, {reg2}, {shift}", "rsbs");
812 T5Helper(&arm::Arm32Assembler::rsc, true, "rsc{cond}{s} {reg1}, {reg2}, {shift}", "rsc");
816 T4Helper(&arm::Arm32Assembler::rscs, false, "rsc{cond}s {reg1}, {reg2}, {shift}", "rscs");
821 T4Helper(&arm::Arm32Assembler::strex, "strex{cond} {reg1}, {reg2}, [{reg3}]", "strex",
827 T3Helper(&arm::Arm32Assembler::clz, true, "clz{cond} {reg1}, {reg2}", "clz");
831 T3Helper(&arm::Arm32Assembler::tst, true, "tst{cond} {reg1}, {shift}", "tst");
835 T3Helper(&arm::Arm32Assembler::teq, true, "teq{cond} {reg1}, {shift}", "teq");
839 T3Helper(&arm::Arm32Assembler::cmp, true, "cmp{cond} {reg1}, {shift}", "cmp");
843 T3Helper(&arm::Arm32Assembler::cmn, true, "cmn{cond} {reg1}, {shift}", "cmn");
847 T2Helper(&arm::Arm32Assembler::blx, true, "blx{cond} {reg1}", "blx");
851 T2Helper(&arm::Arm32Assembler::bx, true, "bx{cond} {reg1}", "bx");
863 GetAssembler()->ldrexd(arm::R0, arm::R1, arm::R0);
864 GetAssembler()->ldrexd(arm::R0, arm::R1, arm::R1);
865 GetAssembler()->ldrexd(arm::R0, arm::R1, arm::R2);
875 GetAssembler()->strexd(arm::R9, arm::R0, arm::R1, arm::R0);
876 GetAssembler()->strexd(arm::R9, arm::R0, arm::R1, arm::R1);
877 GetAssembler()->strexd(arm::R9, arm::R0, arm::R1, arm::R2);
887 T3Helper(&arm::Arm32Assembler::rbit, true, "rbit{cond} {reg1}, {reg2}", "rbit");
891 T3Helper(&arm::Arm32Assembler::rev, true, "rev{cond} {reg1}, {reg2}", "rev");
895 T3Helper(&arm::Arm32Assembler::rev16, true, "rev16{cond} {reg1}, {reg2}", "rev16");
899 T3Helper(&arm::Arm32Assembler::revsh, true, "revsh{cond} {reg1}, {reg2}", "revsh");