Lines Matching defs:NewReg
319 // be replaced by NewReg. Return true if any of their parent instructions may
324 // the two-address instruction also defines NewReg, as may happen with
328 // both NewReg and AntiDepReg covers it.
332 unsigned NewReg)
338 // operands, in case they may be assigned to NewReg. In this case antidep
343 // Handle cases in which this instruction defines NewReg.
348 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
352 CheckOper.getReg() != NewReg)
355 // Don't allow the instruction to define NewReg and AntiDepReg.
361 // NewReg.
365 // Don't allow inline asm to define NewReg at all. Who knows what it's
384 unsigned NewReg = Order[i];
386 if (NewReg == AntiDepReg) continue;
390 if (NewReg == LastNewReg) continue;
391 // If any instructions that define AntiDepReg also define the NewReg, it's
394 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
395 // If NewReg is dead and NewReg's most recent def is not before
396 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
399 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
400 && "Kill and Def maps aren't consistent for NewReg!");
401 if (KillIndices[NewReg] != ~0u ||
402 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
403 KillIndices[AntiDepReg] > DefIndices[NewReg])
405 // If NewReg overlaps any of the forbidden registers, we can't use it.
409 if (TRI->regsOverlap(NewReg, *it)) {
414 return NewReg;
628 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
635 << " using " << TRI->getName(NewReg) << "!\n");
641 Q->second->setReg(NewReg);
650 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
656 Classes[NewReg] = Classes[AntiDepReg];
657 DefIndices[NewReg] = DefIndices[AntiDepReg];
658 KillIndices[NewReg] = KillIndices[AntiDepReg];
659 assert(((KillIndices[NewReg] == ~0u) !=
660 (DefIndices[NewReg] == ~0u)) &&
661 "Kill and Def maps aren't consistent for NewReg!");
671 LastNewReg[AntiDepReg] = NewReg;