Cross Reference: /external/llvm/lib/Target/AArch64/AArch64FastISel.cpp

Lines Matching defs:Op0IsKill
194   unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
212   unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
214   unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
216   unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
218   unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
220   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
222   unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
224   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
226   unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
228   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1012                                /*Op0IsKill=*/false, Addr.getShift(),
1016                                /*Op0IsKill=*/false, Addr.getShift(),
1020                                /*Op0IsKill=*/false, Addr.getShift());
1486 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,
1490     ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1492     ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1501   ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
3476     bool Op0IsKill = hasTrivialKill(II->getOperand(0));
3478     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
3835 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3851   return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
3855 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3861                           Op0, Op0IsKill, Op1, Op1IsKill,
3865 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3871                           Op0, Op0IsKill, Op1, Op1IsKill,
3875 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3894   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3902                                      bool Op0IsKill, uint64_t Shift,
3925           .addReg(Op0, getKillRegState(Op0IsKill));
3973         .addReg(Op0, getKillRegState(Op0IsKill))
3976     Op0IsKill = true;
3978   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3981 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3997     Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
3999     Op0IsKill = Op1IsKill = true;
4001   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4009                                      bool Op0IsKill, uint64_t Shift,
4032       .addReg(Op0, getKillRegState(Op0IsKill));
4076     Op0IsKill = true;
4094         .addReg(Op0, getKillRegState(Op0IsKill))
4097     Op0IsKill = true;
4099   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4102 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4120     Op0IsKill = Op1IsKill = true;
4122   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4130                                      bool Op0IsKill, uint64_t Shift,
4153       .addReg(Op0, getKillRegState(Op0IsKill));
4203         .addReg(Op0, getKillRegState(Op0IsKill))
4206     Op0IsKill = true;
4208   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4583     bool Op0IsKill = hasTrivialKill(Op0);
4588       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4591       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4594       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4607   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4618     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4621     ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4624     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4666   bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4667   unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);