Cross Reference: /external/llvm/utils/TableGen/RegisterInfoEmitter.cpp

Lines Matching defs:RegisterClasses
105   const auto &RegisterClasses = Bank.getRegClasses();
106   if (!RegisterClasses.empty()) {
109     assert(RegisterClasses.size() <= 0xffff &&
116     for (const auto &RC : RegisterClasses)
949   const auto &RegisterClasses = RegBank.getRegClasses();
957   for (const auto &RC : RegisterClasses) {
997   for (const auto &RC : RegisterClasses) {
1042      << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, "
1104   const auto &RegisterClasses = RegBank.getRegClasses();
1106   if (!RegisterClasses.empty()) {
1107     OS << "namespace " << RegisterClasses.front().Namespace
1110     for (const auto &RC : RegisterClasses) {
1140   const auto &RegisterClasses = RegBank.getRegClasses();
1147   for (const auto &RC : RegisterClasses) {
1156   for (const auto &RC : RegisterClasses)
1182   if (!RegisterClasses.empty()) {
1206     SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
1208     BitVector MaskBV(RegisterClasses.size());
1210     for (const auto &RC : RegisterClasses) {
1237     for (const auto &RC : RegisterClasses) {
1252     for (const auto &RC : RegisterClasses) {
1284     OS << "\nnamespace " << RegisterClasses.front().Namespace
1287     for (const auto &RC : RegisterClasses) {
1313   OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
1314   for (const auto &RC : RegisterClasses)
1351     if (RegisterClasses.size() < UINT8_MAX)
1353     else if (RegisterClasses.size() < UINT16_MAX)
1357     OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
1358     for (const auto &RC : RegisterClasses) {
1395      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1401      << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"