Lines Matching defs:pPortDef

274     pComponentPrivate->pPortDef[G726ENC_INPUT_PORT] = pPortDef_ip;
291 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT] = pPortDef_op;
666 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->nPortIndex) {
667 memcpy(ComponentParameterStructure, pComponentPrivate->pPortDef[G726ENC_INPUT_PORT], sizeof(OMX_PARAM_PORTDEFINITIONTYPE));
670 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->nPortIndex) {
671 memcpy(ComponentParameterStructure, pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT], sizeof(OMX_PARAM_PORTDEFINITIONTYPE));
682 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->nPortIndex) {
692 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->nPortIndex){
830 if(((OMX_PARAM_PORTDEFINITIONTYPE *)(pCompParam))->nPortIndex == pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->nPortIndex) {
832 memcpy(pComponentPrivate->pPortDef[G726ENC_INPUT_PORT], pCompParam, sizeof(OMX_PARAM_PORTDEFINITIONTYPE));
834 else if(((OMX_PARAM_PORTDEFINITIONTYPE *)(pCompParam))->nPortIndex == pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->nPortIndex) {
836 memcpy(pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT], pCompParam, sizeof(OMX_PARAM_PORTDEFINITIONTYPE));
1073 OMX_PARAM_PORTDEFINITIONTYPE *pPortDef = NULL;
1078 pPortDef = ((G726ENC_COMPONENT_PRIVATE*)pComponentPrivate)->pPortDef[G726ENC_INPUT_PORT];
1093 if (!pPortDef->bEnabled) {
1158 OMX_PARAM_PORTDEFINITIONTYPE *pPortDef = NULL;
1162 pPortDef = ((G726ENC_COMPONENT_PRIVATE*)pComponentPrivate)->pPortDef[G726ENC_OUTPUT_PORT];
1179 if (!pPortDef->bEnabled) {
1347 OMX_PARAM_PORTDEFINITIONTYPE *pPortDef = NULL;
1355 pPortDef = ((G726ENC_COMPONENT_PRIVATE*)pComponentPrivate)->pPortDef[nPortIndex];
1357 G726ENC_DPRINT("%d :: pPortDef = %p\n", __LINE__,pPortDef);
1358 G726ENC_DPRINT("%d :: pPortDef->bEnabled = %d\n", __LINE__,pPortDef->bEnabled);
1360 if(!pPortDef->bEnabled) {
1391 if (pComponentPrivate->pInputBufferList->numBuffers == pPortDef->nBufferCountActual) {
1392 pPortDef->bPopulated = OMX_TRUE;
1393 G726ENC_DPRINT("%d :: pPortDef->bPopulated = %d\n", __LINE__, pPortDef->bPopulated);
1402 if (pComponentPrivate->pOutputBufferList->numBuffers == pPortDef->nBufferCountActual) {
1403 pPortDef->bPopulated = OMX_TRUE;
1404 G726ENC_DPRINT("%d :: pPortDef->bPopulated = %d\n", __LINE__, pPortDef->bPopulated);
1413 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bPopulated &&
1414 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bEnabled &&
1415 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->bPopulated &&
1416 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->bEnabled &&
1420 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bPopulated &&
1421 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bEnabled &&
1523 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->nBufferCountMin) {
1525 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->bPopulated = OMX_FALSE;
1527 if(pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->bEnabled &&
1549 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->nBufferCountMin) {
1550 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bPopulated = OMX_FALSE;
1552 if(pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bEnabled &&
1607 OMX_PARAM_PORTDEFINITIONTYPE *pPortDef = NULL;
1615 pPortDef = ((G726ENC_COMPONENT_PRIVATE*)pComponentPrivate)->pPortDef[nPortIndex];
1617 G726ENC_DPRINT("%d :: pPortDef->bPopulated = %d \n",__LINE__,pPortDef->bPopulated);
1619 if(!pPortDef->bEnabled) {
1625 if(nSizeBytes != pPortDef->nBufferSize || pPortDef->bPopulated) {
1640 if (pComponentPrivate->pOutputBufferList->numBuffers == pPortDef->nBufferCountActual) {
1641 pPortDef->bPopulated = OMX_TRUE;
1650 if (pComponentPrivate->pInputBufferList->numBuffers == pPortDef->nBufferCountActual) {
1651 pPortDef->bPopulated = OMX_TRUE;
1656 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bPopulated &&
1657 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bEnabled &&
1658 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->bPopulated &&
1659 pComponentPrivate->pPortDef[G726ENC_INPUT_PORT]->bEnabled &&
1663 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bPopulated &&
1664 pComponentPrivate->pPortDef[G726ENC_OUTPUT_PORT]->bEnabled &&