| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 1986 //return DCI.CombineTo(N, NewSt, true);
3830 TargetLowering::DAGCombinerInfo &DCI,
3833 SelectionDAG &DAG = DCI.DAG;
3936 TargetLowering::DAGCombinerInfo &DCI,
3943 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget,
3949 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3953 TargetLowering::DAGCombinerInfo &DCI) {
4015 Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4021 DCI.CombineTo(N, Val, AddTo);
4028 TargetLowering::DAGCombinerInfo &DCI) {
4161 TryMULWIDECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
4228 PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel) argument
4242 PerformSHLCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, CodeGenOpt::Level OptLevel) argument
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 1260 DAGCombinerInfo &DCI, SDLoc dl) const {
1261 SelectionDAG &DAG = DCI.DAG;
1282 (DCI.isBeforeLegalizeOps() ||
1341 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1395 if (DCI.isBeforeLegalize() &&
1488 if (DCI.isBeforeLegalizeOps() ||
1525 if (!DCI.isCalledByLegalizer())
1526 DCI.AddToWorklist(ZextOp.getNode());
1546 if (DCI.isBeforeLegalizeOps() ||
1636 if ((DCI
1258 SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const argument
[all...] |
| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 529 TargetLowering::DAGCombinerInfo &DCI,
531 if (DCI.isBeforeLegalize())
549 TargetLowering::DAGCombinerInfo &DCI,
664 TargetLowering::DAGCombinerInfo &DCI,
784 TargetLowering::DAGCombinerInfo &DCI,
786 if (DCI.isBeforeLegalize())
835 const TargetLowering::DAGCombinerInfo &DCI,
874 TargetLowering::DAGCombinerInfo &DCI,
897 TargetLowering::DAGCombinerInfo &DCI,
943 TargetLowering::DAGCombinerInfo &DCI,
528 performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
548 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
663 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
783 performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
834 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL) argument
873 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
896 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
942 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
[all...] |
| H A D | MipsISelLowering.cpp | 471 TargetLowering::DAGCombinerInfo &DCI,
473 if (DCI.isBeforeLegalizeOps())
581 TargetLowering::DAGCombinerInfo &DCI,
583 if (DCI.isBeforeLegalizeOps())
660 TargetLowering::DAGCombinerInfo &DCI,
662 if (DCI.isBeforeLegalizeOps())
687 TargetLowering::DAGCombinerInfo &DCI,
692 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
729 TargetLowering::DAGCombinerInfo &DCI,
735 if (DCI
470 performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
580 performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
659 performCMovFPCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
686 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
728 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
784 performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 1091 DAGCombinerInfo &DCI) const {
1098 SelectionDAG &DAG = DCI.DAG;
1128 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1129 !DCI.isCalledByLegalizer())
1149 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1150 !DCI.isCalledByLegalizer())
2316 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) { argument
2318 SelectionDAG &DAG = DCI.DAG;
2326 DCI.CommitTargetLoweringOpt(TLO);
2355 DAGCombinerInfo &DCI) cons
2735 getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const argument
2753 getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const argument
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 7367 TargetLowering::DAGCombinerInfo &DCI,
7369 if (DCI.isBeforeLegalizeOps())
7418 TargetLowering::DAGCombinerInfo &DCI,
7420 if (DCI.isBeforeLegalizeOps())
7715 TargetLowering::DAGCombinerInfo &DCI) {
7716 SelectionDAG &DAG = DCI.DAG;
7755 TargetLowering::DAGCombinerInfo &DCI) {
7757 SelectionDAG &DAG = DCI.DAG;
7801 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, argument
7806 SelectionDAG &DAG = DCI
7366 performXorCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
7417 performMulCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
7714 tryCombineToEXTR(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
7754 tryCombineToBSL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
7823 performBitcastCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
7889 performConcatVectorsCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
7970 tryCombineFixedPointConvert(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
8214 performAddSubLongCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
8263 tryCombineLongOpWithDup(unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
8378 performIntrinsicCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) argument
8434 performExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
8592 split16BStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
8660 performPostLD1Combine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp) argument
8758 performTBISimplification(SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
8773 performSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget) argument
9051 performNEONPostLDSTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
9367 performCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex) argument
9441 performBRCONDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) argument
9531 performSelectCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9156 DAGCombinerInfo &DCI,
9166 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9173 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9179 DAGCombinerInfo &DCI,
9188 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9194 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9444 DAGCombinerInfo &DCI) const {
9445 SelectionDAG &DAG = DCI.DAG;
9722 DAGCombinerInfo &DCI) const {
9723 SelectionDAG &DAG = DCI
9155 getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps, bool &UseOneConstNR) const argument
9178 getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, unsigned &RefinementSteps) const argument
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 8329 // @param DCI Context.
8334 TargetLowering::DAGCombinerInfo &DCI,
8336 SelectionDAG &DAG = DCI.DAG;
8360 TargetLowering::DAGCombinerInfo &DCI) {
8364 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8369 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8379 TargetLowering::DAGCombinerInfo &DCI,
8384 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8438 SelectionDAG &DAG = DCI.DAG;
8477 TargetLowering::DAGCombinerInfo &DCI,
8333 combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI, bool AllOnes = false) argument
8359 combineSelectAndUseCommutative(SDNode *N, bool AllOnes, TargetLowering::DAGCombinerInfo &DCI) argument
8378 AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8476 AddCombineTo64bitMLAL(SDNode *AddcNode, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8614 PerformADDCCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8626 PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8645 PerformADDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8662 PerformSUBCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
8691 PerformVMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8722 PerformMULCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8806 PerformANDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
8850 PerformORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
9047 PerformXORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
9142 PerformBFICombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9201 PerformVMOVRRDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
9277 PerformBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const ARMSubtarget *Subtarget) argument
9312 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9404 PerformInsertEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9486 CombineBaseUpdate(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9691 PerformVLDCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9703 CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9782 PerformVDUPLANECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9812 PerformLOADCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
9826 PerformSTORECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) argument
[all...] |