| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 153 unsigned Lane = (Offset / 4) % 64; local
170 Spill.Lane = Lane;
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| H A D | SIMachineFunctionInfo.h | 108 int Lane; member in struct:llvm::SIMachineFunctionInfo::SpilledReg
109 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { }
110 SpilledReg() : VGPR(0), Lane(-1) { }
111 bool hasLane() { return Lane != -1;}
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| H A D | SIISelLowering.cpp | 2204 unsigned Lane = 0; local
2217 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
2218 // Note that subregs are packed, i.e. Lane==0 is the first bit set
2219 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
2221 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
2225 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
2232 if (Users[Lane])
2235 Users[Lane] = *I;
2255 SDLoc(), Users[Lane]->getValueType(0),
2257 DAG.ReplaceAllUsesWith(Users[Lane], Cop
[all...] |
| /external/gemmlowp/meta/generators/ |
| H A D | neon_emitter.py | 350 def Lane(self, value, lane): member in class:NeonEmitter
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| /external/llvm/lib/Target/ARM/ |
| H A D | A15SDOptimizer.cpp | 72 unsigned Reg, unsigned Lane,
78 unsigned DReg, unsigned Lane,
93 DebugLoc DL, unsigned DReg, unsigned Lane,
433 unsigned Reg, unsigned Lane, bool QPR) {
442 .addImm(Lane));
452 unsigned DReg, unsigned Lane,
459 .addReg(DReg, 0, Lane);
503 DebugLoc DL, unsigned DReg, unsigned Lane,
512 .addImm(Lane);
569 unsigned Lane; local
430 createDupLane(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned Reg, unsigned Lane, bool QPR) argument
449 createExtractSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, const TargetRegisterClass *TRC) argument
501 createInsertSubreg(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, DebugLoc DL, unsigned DReg, unsigned Lane, unsigned ToInsert) argument
[all...] |
| H A D | ARMExpandPseudoInsts.cpp | 510 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); local
514 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
516 Lane -= RegElts;
518 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
563 MIB.addImm(Lane);
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| H A D | ARMISelDAGToDAG.cpp | 2101 unsigned Lane = local
2177 Ops.push_back(getI32Imm(Lane, dl));
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| H A D | ARMBaseInstrInfo.cpp | 4183 unsigned SReg, unsigned &Lane) {
4185 Lane = 0;
4190 Lane = 1;
4205 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4206 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4214 unsigned DReg, unsigned Lane,
4225 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4243 unsigned Lane; local
4285 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4287 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 1
4182 getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI, unsigned SReg, unsigned &Lane) argument
4212 getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI, MachineInstr *MI, unsigned DReg, unsigned Lane, unsigned &ImplicitSReg) argument
[all...] |
| H A D | ARMISelLowering.cpp | 5946 int Lane = SVN->getSplatIndex(); local
5948 if (Lane == -1) Lane = 0;
5951 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5957 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5969 DAG.getConstant(Lane, dl, MVT::i32));
6107 SDValue Lane = Op.getOperand(2); local
6108 if (!isa<ConstantSDNode>(Lane))
6116 SDValue Lane = Op.getOperand(1); local
6117 if (!isa<ConstantSDNode>(Lane))
10347 SDValue Lane = N0.getOperand(1); local
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2102 int Lane = SVN->getSplatIndex(); local
2103 if (Lane == -1) Lane = 0;
2106 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2112 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2123 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 3057 unsigned Lane = MI->getOperand(2).getImm(); local
3059 if (Lane == 0) {
3075 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3101 unsigned Lane = MI->getOperand(2).getImm() * 2; local
3104 if (Lane == 0)
3131 unsigned Lane = MI->getOperand(2).getImm(); local
3143 .addImm(Lane)
3167 unsigned Lane = MI->getOperand(2).getImm(); local
3177 .addImm(Lane)
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| /external/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 3978 uint32_t Lane = cast<ConstantInt>(Ops[2])->getZExtValue(); local
3979 Value *SV = llvm::ConstantVector::get(ConstantInt::get(Int32Ty, 1-Lane));
3988 uint32_t Indices[] = {1 - Lane, Lane};
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| /external/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 523 Scalar(S), User(U), Lane(L){}
529 int Lane; member in struct:__anon12598::BoUpSLP::ExternalUser
944 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) {
945 Value *Scalar = Entry->Scalars[Lane];
964 // instructions. If that is the case, the one in Lane 0 will
981 Lane << " from " << *Scalar << ".\n");
982 ExternalUses.push_back(ExternalUser(Scalar, U, Lane));
1808 I->Lane);
2587 Value *Lane = Builder.getInt32(it->Lane); local
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 5376 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64); local
5377 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5501 int Lane = SVN->getSplatIndex(); local
5503 if (Lane == -1)
5504 Lane = 0;
5506 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5512 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5513 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5522 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5525 unsigned Idx = Lane >
7993 SDValue Lane = Op1.getOperand(1); local
[all...] |