Searched defs:MIa (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp345 bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, argument
347 unsigned MIaG = getCompoundCandidateGroup(MIa, IsExtendedA);
351 unsigned Opca = MIa.getOpcode();
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg()));
H A DHexagonMCDuplexInfo.cpp575 MCInst const &MIa, bool ExtendedA,
587 unsigned MIaG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIa),
593 MCInst SubInst0 = HexagonMCInstrInfo::deriveSubInst(MIa);
613 // Note that MIb (slot1) can be extended and MIa (slot0)
615 if (subInstWouldBeExtended(MIa))
634 // If a store appears, it must be in slot 0 (MIa) 1st, and then slot 1 (MIb);
645 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { argument
646 unsigned MIaG = getDuplexCandidateGroup(MIa),
574 isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa, bool ExtendedA, MCInst const &MIb, bool ExtendedB, bool bisReversable) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp615 AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, argument
623 assert(MIa && MIa->mayLoadOrStore() && "MIa must be a load or store.");
626 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
627 MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())
635 if (getMemOpBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA, TRI) &&
H A DAArch64LoadStoreOptimizer.cpp843 static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb, argument
846 if (!MIa->mayStore() && !MIb->mayStore())
850 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
853 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
856 static bool mayAlias(MachineInstr *MIa, argument
860 if (mayAlias(MIa, MIb, TII))
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h1352 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, argument
1354 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1355 "MIa must load from or modify a memory location");
/external/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp568 const DataLayout &DL, MachineInstr *MIa,
570 const MachineFunction *MF = MIa->getParent()->getParent();
574 if (MIa == MIb)
578 if ((MIa->mayLoad() || MIa->mayStore()) &&
580 if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))
584 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())
587 if (isUnsafeMemoryObject(MIa, MFI, DL) || isUnsafeMemoryObject(MIb, MFI, DL))
592 if (!MIa->mayStore() && !MIb->mayStore())
599 MachineMemOperand *MMOa = *MIa
567 MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo *MFI, const DataLayout &DL, MachineInstr *MIa, MachineInstr *MIb) argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1391 bool HexagonInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, argument
1396 if (MIa->hasUnmodeledSideEffects() || MIb->hasUnmodeledSideEffects() ||
1397 MIa->hasOrderedMemoryRef() || MIa->hasOrderedMemoryRef())
1402 if (MIa->mayLoad() && !isMemOp(MIa) && MIb->mayLoad() && !isMemOp(MIb))
1405 // Get base, offset, and access size in MIa.
1406 unsigned BaseRegA = getBaseAndOffset(MIa, OffsetA, SizeA);
1775 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa, argument
1777 HexagonII::SubInstructionGroup MIaG = getDuplexCandidateGroup(MIa);
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