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Searched defs:NumVecs (Results 1 - 4 of 4) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A D	AArch64ISelDAGToDAG.cpp	150 SDNode SelectTable(SDNode N, unsigned NumVecs, unsigned Opc, bool isExt); 154 SDNode SelectLoad(SDNode N, unsigned NumVecs, unsigned Opc, 156 SDNode SelectPostLoad(SDNode N, unsigned NumVecs, unsigned Opc, 158 SDNode SelectLoadLane(SDNode N, unsigned NumVecs, unsigned Opc); 159 SDNode SelectPostLoadLane(SDNode N, unsigned NumVecs, unsigned Opc); 161 SDNode SelectStore(SDNode N, unsigned NumVecs, unsigned Opc); 162 SDNode SelectPostStore(SDNode N, unsigned NumVecs, unsigned Opc); 163 SDNode SelectStoreLane(SDNode N, unsigned NumVecs, unsigned Opc); 164 SDNode SelectPostStoreLane(SDNode N, unsigned NumVecs, unsigned Opc); 1018 SDNode AArch64DAGToDAGISel::SelectTable(SDNode N, unsigned NumVecs, argument 1134 SelectLoad(SDNode N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument 1155 SelectPostLoad(SDNode N, unsigned NumVecs, unsigned Opc, unsigned SubRegIdx) argument 1187 SelectStore(SDNode N, unsigned NumVecs, unsigned Opc) argument 1203 SelectPostStore(SDNode N, unsigned NumVecs, unsigned Opc) argument 1259 SelectLoadLane(SDNode N, unsigned NumVecs, unsigned Opc) argument 1299 SelectPostLoadLane(SDNode N, unsigned NumVecs, unsigned Opc) argument 1355 SelectStoreLane(SDNode N, unsigned NumVecs, unsigned Opc) argument 1385 SelectPostStoreLane(SDNode N, unsigned NumVecs, unsigned Opc) argument [all...]
H A D	AArch64ISelLowering.cpp	`9078 unsigned NumVecs = 0; local 9083 NumVecs = 2; break; 9085 NumVecs = 3; break; 9087 NumVecs = 4; break; 9089 NumVecs = 2; IsStore = true; break; 9091 NumVecs = 3; IsStore = true; break; 9093 NumVecs = 4; IsStore = true; break; 9095 NumVecs = 2; break; 9097 NumVecs = 3; break; 9099 NumVecs [all...]`
/external/llvm/lib/Target/ARM/
H A D	ARMISelDAGToDAG.cpp	208 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 211 /// For NumVecs <= 2, QOpcodes1 is not used. 212 SDNode SelectVLD(SDNode N, bool isUpdating, unsigned NumVecs, 216 /// SelectVST - Select NEON store intrinsics. NumVecs should 219 /// For NumVecs <= 2, QOpcodes1 is not used. 220 SDNode SelectVST(SDNode N, bool isUpdating, unsigned NumVecs, 224 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 228 bool isUpdating, unsigned NumVecs, 231 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs 234 SDNode SelectVLDDup(SDNode N, bool isUpdating, unsigned NumVecs, 1683 GetVLDSTAlign(SDValue Align, SDLoc dl, unsigned NumVecs, bool is64BitVector) argument 1804 SelectVLD(SDNode N, bool isUpdating, unsigned NumVecs, const uint16_t DOpcodes, const uint16_t QOpcodes0, const uint16_t QOpcodes1) argument 1937 SelectVST(SDNode N, bool isUpdating, unsigned NumVecs, const uint16_t DOpcodes, const uint16_t QOpcodes0, const uint16_t QOpcodes1) argument 2084 SelectVLDSTLane(SDNode N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t DOpcodes, const uint16_t QOpcodes) argument 2203 SelectVLDDup(SDNode N, bool isUpdating, unsigned NumVecs, const uint16_t Opcodes) argument 2286 SelectVTBL(SDNode N, bool IsExt, unsigned NumVecs, unsigned Opc) argument [all...]
H A D	ARMISelLowering.cpp	`9514 unsigned NumVecs = 0; local 9520 NumVecs = 1; break; 9522 NumVecs = 2; break; 9524 NumVecs = 3; break; 9526 NumVecs = 4; break; 9528 NumVecs = 2; isLaneOp = true; break; 9530 NumVecs = 3; isLaneOp = true; break; 9532 NumVecs = 4; isLaneOp = true; break; 9534 NumVecs = 1; isLoadOp = false; break; 9536 NumVecs 9714 unsigned NumVecs = 0; local [all...]`

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