/external/google-breakpad/src/common/linux/ |
H A D | elfutils.h | 51 typedef Elf32_Off Off; typedef in struct:google_breakpad::ElfClass32 64 typedef Elf64_Off Off; typedef in struct:google_breakpad::ElfClass64 114 typename ElfClass::Off offset);
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/external/llvm/include/llvm/MC/ |
H A D | MCWin64EH.h | 50 static WinEH::Instruction SetFPReg(MCSymbol *L, unsigned Reg, unsigned Off) { argument 51 return WinEH::Instruction(UOP_SetFPReg, L, Reg, Off);
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H A D | MCWinEH.h | 29 Instruction(unsigned Op, MCSymbol *L, unsigned Reg, unsigned Off) argument 30 : Label(L), Offset(Off), Register(Reg), Operation(Op) {}
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/external/clang/test/Analysis/ |
H A D | unreachable-code-path.c | 70 enum test_enum { Off, On }; enumerator in enum:test_enum 78 if (Off)
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/external/llvm/lib/MC/MCDisassembler/ |
H A D | MCExternalSymbolizer.cpp | 112 const MCExpr *Off = nullptr; local 114 Off = MCConstantExpr::create(SymbolicOp.Value, Ctx); 123 if (Off) 124 Expr = MCBinaryExpr::createAdd(LHS, Off, Ctx); 128 if (Off) 129 Expr = MCBinaryExpr::createAdd(Add, Off, Ctx); 133 if (Off) 134 Expr = Off;
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/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64ExternalSymbolizer.cpp | 190 const MCExpr *Off = nullptr; local 192 Off = MCConstantExpr::create(SymbolicOp.Value, Ctx); 201 if (Off) 202 Expr = MCBinaryExpr::createAdd(LHS, Off, Ctx); 206 if (Off) 207 Expr = MCBinaryExpr::createAdd(Add, Off, Ctx); 211 if (Off) 212 Expr = Off;
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetObjectFile.cpp | 60 const MCExpr *Off = MCConstantExpr::create(FinalOff, getContext()); local 61 return MCBinaryExpr::createAdd(Res, Off, getContext());
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/external/llvm/lib/IR/ |
H A D | MDBuilder.cpp | 159 ConstantInt *Off = ConstantInt::get(Type::getInt64Ty(Context), Offset); local 161 {createString(Name), Parent, createConstant(Off)}); 169 ConstantInt *Off = ConstantInt::get(Int64, Offset); local 171 return MDNode::get(Context, {BaseType, AccessType, createConstant(Off), 174 return MDNode::get(Context, {BaseType, AccessType, createConstant(Off)});
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 340 int Off = Offset; // ARM doesn't need the general 64-bit offsets local 350 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII);
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SILowerControlFlow.cpp | 433 int Off = MI.getOperand(4).getImm(); local 436 computeIndirectRegAndOffset(Vec, Reg, Off); 443 LoadM0(MI, MovRel, Off); 452 int Off = MI.getOperand(4).getImm(); local 456 computeIndirectRegAndOffset(Dst, Reg, Off); 464 LoadM0(MI, MovRel, Off);
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/external/llvm/lib/MC/MCParser/ |
H A D | COFFAsmParser.cpp | 615 int64_t Off; local 623 if (getParser().parseAbsoluteExpression(Off)) 626 if (Off & 0x0F) 633 getStreamer().EmitWinCFISetFrame(Reg, Off); 656 int64_t Off; local 664 if (getParser().parseAbsoluteExpression(Off)) 667 if (Off & 7) 675 getStreamer().EmitWinCFISaveReg(Reg, Off); 683 int64_t Off; local 691 if (getParser().parseAbsoluteExpression(Off)) [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.cpp | 259 int Off = op(2).getImm(); variable 260 unsigned A = MFI.getObjectAlignment(FI) + std::abs(Off);
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H A D | HexagonStoreWidening.cpp | 440 int64_t Off = FirstSt->getOperand(1).getImm(); local 443 .addImm(Off) 462 int64_t Off = FirstSt->getOperand(1).getImm(); local 465 .addImm(Off)
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H A D | HexagonSplitDouble.cpp | 619 int64_t Off = PostInc ? 0 : MI->getOperand(2).getImm(); local 622 .addImm(Off); 625 .addImm(Off+4); 628 int64_t Off = PostInc ? 0 : MI->getOperand(1).getImm(); local 631 .addImm(Off) 635 .addImm(Off+4)
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H A D | HexagonFrameLowering.cpp | 1291 int Off = MinOffset - RC->getSize(); local 1294 Off &= -Align; 1295 int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), Off); 1296 MinOffset = std::min(MinOffset, Off); 1305 int Off = MFI->getObjectOffset(FI); 1307 if (Off >= 0) 1309 dbgs() << Off;
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/external/llvm/lib/Transforms/Instrumentation/ |
H A D | SafeStack.cpp | 539 Value *Off = IRB.CreateGEP(BasePointer, // BasePointer is i8* local 541 Value *NewArg = IRB.CreateBitCast(Off, Arg->getType(), 549 IRB.CreateMemCpy(Off, Arg, Size, Arg->getParamAlignment()); 570 Value *Off = IRB.CreateGEP(BasePointer, // BasePointer is i8* local 572 Value *NewAI = IRB.CreateBitCast(Off, AI->getType(), AI->getName());
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/external/llvm/include/llvm/Support/ |
H A D | OnDiskHashTable.h | 81 offset_type Off; member in struct:llvm::OnDiskChainedHashTableGenerator::Bucket 162 B.Off = Out.tell(); 163 assert(B.Off && "Cannot write a bucket at offset 0. Please add padding."); 204 LE.write<offset_type>(Buckets[I].Off);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.cpp | 589 int Off = Offset; // ARM doesn't need the general 64-bit offsets local 601 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 604 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
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/external/skia/debugger/QT/ |
H A D | SkDebuggerGUI.cpp | 395 QIcon::Normal, QIcon::Off); member in class:QIcon 406 QSize(), QIcon::Normal, QIcon::Off); member in class:QIcon 414 QIcon::Normal, QIcon::Off); member in class:QIcon 438 QSize(), QIcon::Normal, QIcon::Off); member in class:QIcon 445 QSize(), QIcon::Normal, QIcon::Off); member in class:QIcon 452 QIcon::Normal, QIcon::Off); member in class:QIcon 459 QIcon::Normal, QIcon::Off); member in class:QIcon 467 QIcon::Normal, QIcon::Off); member in class:QIcon 485 QIcon::Normal, QIcon::Off); member in class:QIcon 492 QSize(), QIcon::Normal, QIcon::Off); member in class:QIcon [all...] |
/external/clang/lib/Frontend/ |
H A D | CacheTokens.cpp | 476 static void pwrite32le(raw_pwrite_stream &OS, uint32_t Val, uint64_t &Off) { argument 478 OS.pwrite(reinterpret_cast<const char *>(&LEVal), 4, Off); local 479 Off += 4; 534 uint64_t Off = PrologueOffset; local 535 pwrite32le(Out, IdTableOff.first, Off); 536 pwrite32le(Out, IdTableOff.second, Off); 537 pwrite32le(Out, FileTableOff, Off); 538 pwrite32le(Out, SpellingOff, Off);
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/external/llvm/lib/CodeGen/ |
H A D | MachineFunction.cpp | 703 int64_t Off = SO.SPOffset - ValOffset; local 705 if (Off > 0) 706 OS << "+" << Off; local 707 else if (Off < 0) 708 OS << Off; local
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/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 195 const MCExpr *Off; member in struct:__anon12302::SparcOperand::MemOp 255 return Mem.Off; 407 Op->Mem.Off = nullptr; 416 Op->Mem.Off = nullptr; 428 Op->Mem.Off = Imm;
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/external/skia/include/core/ |
H A D | SkPaint.h | 1072 Off = 0, On member in class:SkPaint::FakeGamma
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 93 uint64_t Off = TempOffsets[i]; local 98 Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize()); 103 Offsets->push_back(Off);
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineCasts.cpp | 135 Value *Off = ConstantInt::get(AI.getArraySize()->getType(), local 137 Amt = AllocaBuilder.CreateAdd(Amt, Off);
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