| /external/valgrind/none/tests/mips64/ |
| H A D | shift_instructions.c | 10 SRA, SRAV, SRL, SRLV enumerator in enum:__anon20152
177 case SRA:
|
| /external/llvm/include/llvm/TableGen/ |
| H A D | Record.h | 727 enum BinaryOp { ADD, AND, SHL, SRA, SRL, LISTCONCAT, STRCONCAT, CONCAT, EQ }; enumerator in enum:llvm::BinOpInit::BinaryOp
|
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1033 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS; local
1048 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift);
1052 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift);
1053 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero;
|
| /external/pcre/dist/sljit/ |
| H A D | sljitNativeSPARC_common.c | 152 #define SRA (OPC1(0x2) | OPC3(0x27)) macro
789 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(SLJIT_R0) | IMM(31), DR(TMP_REG1)));
|
| H A D | sljitNativeMIPS_common.c | 169 #define SRA (HI(0) | LO(3)) macro
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR, enumerator in enum:llvm::ISD::NodeType
405 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 667 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
1602 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1630 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
2305 case ISD::SRA:
4403 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4438 Opc == ISD::SRA
6554 case ISD::SRA:
6559 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6567 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
7345 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(
7404 SDValue SRA = local
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 1114 if (Opc == ISD::SRA)
1386 case ISD::SRA: return visitSRA(N);
1485 case ISD::SRA:
2275 DAG.getNode(ISD::SRA, DL, VT, N0,
2288 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD, local
2295 return SRA;
2297 AddToWorklist(SRA.getNode());
2298 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
2486 return DAG.getNode(ISD::SRA, D
4691 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT, local
[all...] |