Searched defs:Swz (Results 1 - 3 of 3) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_emulate_loops.c | 52 rc_swizzle Swz; member in struct:count_inst
123 (1 << GET_SWZ(count_inst->Swz,0) != mask)){
142 inst->U.I.SrcReg[0].Swizzle == count_inst->Swz){
146 inst->U.I.SrcReg[1].Swizzle == count_inst->Swz){
231 count_inst.Swz = counter->Swizzle;
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1805 SDValue Swz[4], SelectionDAG &DAG,
1813 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1815 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1821 unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
1823 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
1804 OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], SelectionDAG &DAG, SDLoc DL) const argument
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| H A D | R600InstrInfo.cpp | 387 R600InstrInfo::BankSwizzle Swz) {
390 switch (Swz) {
415 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { argument
416 switch (Swz) {
441 /// Swz swizzle sequence.
444 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
451 Swizzle(IGSrcs[i], Swz[i]);
457 if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 &&
458 Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) {
386 Swizzle(std::vector<std::pair<int, unsigned> > Src, R600InstrInfo::BankSwizzle Swz) argument
442 isLegalUpTo( const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs, const std::vector<R600InstrInfo::BankSwizzle> &Swz, const std::vector<std::pair<int, unsigned> > &TransSrcs, R600InstrInfo::BankSwizzle TransSwz) const argument
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