Searched defs:VR1 (Results 1 - 3 of 3) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenInsert.cpp | 203 bool operator() (unsigned VR1, unsigned VR2) const { argument 204 return operator[](VR1) < operator[](VR2); 279 bool operator() (unsigned VR1, unsigned VR2) const; 295 bool operator() (unsigned VR1, unsigned VR2) const; 305 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { argument 315 if (VR1 == VR2) 318 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); 329 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; 333 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { argument 334 if (VR1 [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 191 unsigned VR1 = MRI.createVirtualRegister(RC); local 200 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); 201 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); 216 unsigned VR1 = MRI.createVirtualRegister(RC); local 223 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); 224 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); 248 unsigned VR1 = MRI.createVirtualRegister(RC); local 257 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); 259 .addReg(VR1, RegState::Kill);
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H A D | MipsSEISelLowering.cpp | 2960 unsigned VR1 = RegInfo.createVirtualRegister(RC); local 2961 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2967 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
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