Searched refs:SRL (Results 51 - 62 of 62) sorted by relevance
123
| /external/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1567 case LShr: return ISD::SRL;
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| /external/pcre/dist/sljit/ |
| H A D | sljitNativeSPARC_common.c | 154 #define SRL (OPC1(0x2) | OPC3(0x26)) macro
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| /external/v8/src/mips/ |
| H A D | assembler-mips.cc | 1672 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
1696 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
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| H A D | simulator-mips.cc | 3482 case SRL:
3489 // is special case of SRL instruction, added in MIPS32 Release 2.
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| /external/v8/src/mips64/ |
| H A D | assembler-mips64.cc | 1800 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SRL);
1824 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
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| H A D | simulator-mips64.cc | 3424 case SRL:
3432 // is special case of SRL instruction, added in MIPS32 Release 2.
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 3334 emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), Instructions);
3343 SecondShift = Mips::SRL;
3346 FirstShift = Mips::SRL;
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAGNodes.h | 1026 case ISD::SRL:
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| /external/llvm/lib/TableGen/ |
| H A D | TGParser.cpp | 898 case tgtok::XSRL: Code = BinOpInit::SRL; Type = IntRecTy::get(); break;
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1174 case ISD::SRL:
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
2370 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
3720 ISD::SRL, dl, MVT::i32, t0,
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| H A D | LegalizeFloatTypes.cpp | 255 DAG.getNode(ISD::SRL, dl, RVT, SignBit,
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