Searched refs:f11 (Results 76 - 100 of 110) sorted by relevance

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/external/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips5.s12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
49 floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
88 sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dinvalid-mips3.s12 ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
H A Dvalid.s34 cvt.d.w $f26,$f11
/external/llvm/test/MC/Mips/mips32r6/
H A Dinvalid-mips32.s15 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/v8/test/mjsunit/harmony/
H A Ddestructuring.js818 var f11 = function f({x = f}) { var f; return x; } function
819 assertSame(f11, f11({}));
875 function f11({a = b}, {b}) { return a }
876 assertThrows(() => f11({}, {b: 4}), ReferenceError);
877 assertEquals(4, f11({a: 4}, {b: 5}));
985 function f11({x}, y) { var z = y; var y = 2; return z; }
986 assertEquals(1, f11({x: 6}, 1));
/external/llvm/test/MC/Mips/mips3/
H A Dvalid.s46 ceil.w.d $f11,$f25
52 cvt.d.w $f26,$f11
54 cvt.l.s $f11,$f29
113 floor.w.d $f14,$f11
123 ldc1 $f11,16391($s0)
/external/llvm/test/MC/ARM/
H A Dldr-pseudo-darwin.s104 @ CHECK-LABEL: f11:
105 f11: label
/external/clang/test/Analysis/
H A Ddead-stores.c97 int f11() { function
/external/clang/test/CodeGen/
H A Dx86_32-arguments-darwin.c73 // CHECK: i32 @f11()
80 T11 f11(void) { while (1) {} } function
H A Dx86_64-arguments.c66 // CHECK-LABEL: define void @f11(%union.anon* noalias sret %agg.result)
67 union { long double a; float b; } f11() { while (1) {} } function
H A Darm64-arguments.c50 // CHECK: define i64 @f11()
52 struct s11 f11(void) {} function
/external/llvm/test/MC/SystemZ/
H A Dregs-bad.s151 #CHECK: lxr %f0,%f11
174 lxr %f0,%f11
/external/valgrind/none/tests/mips32/
H A DMoveIns.c294 TESTINSNMOVE("mfc1 $s2, $f11", 44, f11, s2);
323 TESTINSNMOVEt("mtc1 $s2, $f11", 44, f11, s2);
352 TESTINSNMOVE1s("mov.s $f10, $f11", 44, f10, f11);
353 TESTINSNMOVE1s("mov.s $f11, $f12", 48, f11, f12);
H A DMoveIns.stdout.exp13 mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
41 mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
69 mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
70 mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
/external/libcxxabi/test/
H A Dcatch_pointer_reference.pass.cpp357 void f11() function
441 f11();
/external/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips64.s27 movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/clang/test/CodeGenCXX/
H A Dtemporaries.cpp244 void f11(H h) { function
/external/elfutils/tests/
H A Drun-allregs.sh203 43: f11 (f11), float 64 bits
1226 43: f11 (f11), float 64 bits
2233 29: %f11 (f11), float 64 bits
2306 29: %f11 (f11), float 64 bits
2393 43: %f11 (f11), floa
[all...]
H A Drun-readelf-mixed-corenote.sh144 f10: 0x0000000000000000 f11: 0x0000000000000000
205 f10: 0x0000000000000000 f11: 0x0000000000000000
/external/libunwind/src/ia64/
H A DGinstall_cursor.S315 ldf.fill f11 = [r3], 32
/external/v8/src/mips/
H A Dsimulator-mips.h147 f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, enumerator in enum:v8::internal::Simulator::FPURegister
/external/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips3.s12 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
/external/valgrind/VEX/priv/
H A Dhost_s390_isel.c2691 HReg op1_hi, op1_lo, op2_hi, op2_lo, f9, f11, f12, f13, f14, f15; local
2693 /* We use non-virtual registers as pairs with (f9, f11) as op1,
2696 f11 = make_fpr(11);
2712 /* 1st operand --> (f9, f11) */
2714 addInstr(env, s390_insn_move(8, f11, op1_lo));
2731 addInstr(env, s390_insn_dfp128_binop(16, dfpop, f13, f15, f9, f11,
2778 HReg op1_hi, op1_lo, op2, f9, f11, f13, f15; local
2802 /* We use non-virtual registers as pairs (f9, f11) and (f13, f15)) */
2804 f11 = make_fpr(11);
2811 /* op1 -> (f9,f11) */
[all...]
/external/valgrind/memcheck/
H A Dmc_machine.c1119 if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
1207 if (o >= GOF(f11) && o+sz <= GOF(f11)+SZB(f11)) return GOF(f11);
/external/valgrind/memcheck/tests/
H A Ddeep-backtrace.c11 int f11(int *p) { return f10(p); } function
12 int f12(int *p) { return f11(p); }

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